2 * @file op_model_xscale.c
3 * XScale Performance Monitor Driver
5 * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
6 * @remark Copyright 2000-2004 MontaVista Software Inc
7 * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com>
8 * @remark Copyright 2004 Intel Corporation
9 * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
10 * @remark Copyright 2004 OProfile Authors
12 * @remark Read the file COPYING
14 * @author Zwane Mwaikambo
18 #include <linux/types.h>
19 #include <linux/errno.h>
20 #include <linux/err.h>
21 #include <linux/sched.h>
22 #include <linux/oprofile.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
26 #include <asm/cputype.h>
29 #include "op_counter.h"
30 #include "op_arm_model.h"
32 #define PMU_ENABLE 0x001 /* Enable counters */
33 #define PMN_RESET 0x002 /* Reset event counters */
34 #define CCNT_RESET 0x004 /* Reset clock counter */
35 #define PMU_RESET (CCNT_RESET | PMN_RESET)
36 #define PMU_CNT64 0x008 /* Make CCNT count every 64th cycle */
39 * Different types of events that can be counted by the XScale PMU
40 * as used by Oprofile userspace. Here primarily for documentation
44 #define EVT_ICACHE_MISS 0x00
45 #define EVT_ICACHE_NO_DELIVER 0x01
46 #define EVT_DATA_STALL 0x02
47 #define EVT_ITLB_MISS 0x03
48 #define EVT_DTLB_MISS 0x04
49 #define EVT_BRANCH 0x05
50 #define EVT_BRANCH_MISS 0x06
51 #define EVT_INSTRUCTION 0x07
52 #define EVT_DCACHE_FULL_STALL 0x08
53 #define EVT_DCACHE_FULL_STALL_CONTIG 0x09
54 #define EVT_DCACHE_ACCESS 0x0A
55 #define EVT_DCACHE_MISS 0x0B
56 #define EVT_DCACE_WRITE_BACK 0x0C
57 #define EVT_PC_CHANGED 0x0D
58 #define EVT_BCU_REQUEST 0x10
59 #define EVT_BCU_FULL 0x11
60 #define EVT_BCU_DRAIN 0x12
61 #define EVT_BCU_ECC_NO_ELOG 0x14
62 #define EVT_BCU_1_BIT_ERR 0x15
64 /* EVT_CCNT is not hardware defined */
66 #define EVT_UNUSED 0xFF
69 volatile unsigned long ovf;
70 unsigned long reset_counter;
73 enum { CCNT, PMN0, PMN1, PMN2, PMN3, MAX_COUNTERS };
75 static struct pmu_counter results[MAX_COUNTERS];
78 * There are two versions of the PMU in current XScale processors
79 * with differing register layouts and number of performance counters.
80 * e.g. IOP32x is xsc1 whilst IOP33x is xsc2.
81 * We detect which register layout to use in xscale_detect_pmu()
83 enum { PMU_XSC1, PMU_XSC2 };
89 unsigned int int_enable;
90 unsigned int cnt_ovf[MAX_COUNTERS];
91 unsigned int int_mask[MAX_COUNTERS];
94 static struct pmu_type pmu_parms[] = {
97 .name = "arm/xscale1",
99 .int_mask = { [PMN0] = 0x10, [PMN1] = 0x20,
101 .cnt_ovf = { [CCNT] = 0x400, [PMN0] = 0x100,
106 .name = "arm/xscale2",
108 .int_mask = { [CCNT] = 0x01, [PMN0] = 0x02,
109 [PMN1] = 0x04, [PMN2] = 0x08,
111 .cnt_ovf = { [CCNT] = 0x01, [PMN0] = 0x02,
112 [PMN1] = 0x04, [PMN2] = 0x08,
117 static struct pmu_type *pmu;
119 static void write_pmnc(u32 val)
121 if (pmu->id == PMU_XSC1) {
122 /* upper 4bits and 7, 11 are write-as-0 */
124 __asm__ __volatile__ ("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
126 /* bits 4-23 are write-as-0, 24-31 are write ignored */
128 __asm__ __volatile__ ("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
132 static u32 read_pmnc(void)
136 if (pmu->id == PMU_XSC1)
137 __asm__ __volatile__ ("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
139 __asm__ __volatile__ ("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
140 /* bits 1-2 and 4-23 are read-unpredictable */
147 static u32 __xsc1_read_counter(int counter)
153 __asm__ __volatile__ ("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
156 __asm__ __volatile__ ("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
159 __asm__ __volatile__ ("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
165 static u32 __xsc2_read_counter(int counter)
171 __asm__ __volatile__ ("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
174 __asm__ __volatile__ ("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
177 __asm__ __volatile__ ("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
180 __asm__ __volatile__ ("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
183 __asm__ __volatile__ ("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
189 static u32 read_counter(int counter)
193 if (pmu->id == PMU_XSC1)
194 val = __xsc1_read_counter(counter);
196 val = __xsc2_read_counter(counter);
201 static void __xsc1_write_counter(int counter, u32 val)
205 __asm__ __volatile__ ("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
208 __asm__ __volatile__ ("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
211 __asm__ __volatile__ ("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
216 static void __xsc2_write_counter(int counter, u32 val)
220 __asm__ __volatile__ ("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
223 __asm__ __volatile__ ("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
226 __asm__ __volatile__ ("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
229 __asm__ __volatile__ ("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
232 __asm__ __volatile__ ("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
237 static void write_counter(int counter, u32 val)
239 if (pmu->id == PMU_XSC1)
240 __xsc1_write_counter(counter, val);
242 __xsc2_write_counter(counter, val);
245 static int xscale_setup_ctrs(void)
250 for (i = CCNT; i < MAX_COUNTERS; i++) {
251 if (counter_config[i].enabled)
254 counter_config[i].event = EVT_UNUSED;
259 pmnc = (counter_config[PMN1].event << 20) | (counter_config[PMN0].event << 12);
260 pr_debug("xscale_setup_ctrs: pmnc: %#08x\n", pmnc);
265 evtsel = counter_config[PMN0].event | (counter_config[PMN1].event << 8) |
266 (counter_config[PMN2].event << 16) | (counter_config[PMN3].event << 24);
268 pr_debug("xscale_setup_ctrs: evtsel %#08x\n", evtsel);
269 __asm__ __volatile__ ("mcr p14, 0, %0, c8, c1, 0" : : "r" (evtsel));
273 for (i = CCNT; i < MAX_COUNTERS; i++) {
274 if (counter_config[i].event == EVT_UNUSED) {
275 counter_config[i].event = 0;
276 pmu->int_enable &= ~pmu->int_mask[i];
280 results[i].reset_counter = counter_config[i].count;
281 write_counter(i, -(u32)counter_config[i].count);
282 pmu->int_enable |= pmu->int_mask[i];
283 pr_debug("xscale_setup_ctrs: counter%d %#08x from %#08lx\n", i,
284 read_counter(i), counter_config[i].count);
290 static void inline __xsc1_check_ctrs(void)
293 u32 pmnc = read_pmnc();
295 /* NOTE: there's an A stepping errata that states if an overflow */
296 /* bit already exists and another occurs, the previous */
297 /* Overflow bit gets cleared. There's no workaround. */
298 /* Fixed in B stepping or later */
300 /* Write the value back to clear the overflow flags. Overflow */
301 /* flags remain in pmnc for use below */
302 write_pmnc(pmnc & ~PMU_ENABLE);
304 for (i = CCNT; i <= PMN1; i++) {
305 if (!(pmu->int_mask[i] & pmu->int_enable))
308 if (pmnc & pmu->cnt_ovf[i])
313 static void inline __xsc2_check_ctrs(void)
316 u32 flag = 0, pmnc = read_pmnc();
321 /* read overflow flag register */
322 __asm__ __volatile__ ("mrc p14, 0, %0, c5, c1, 0" : "=r" (flag));
324 for (i = CCNT; i <= PMN3; i++) {
325 if (!(pmu->int_mask[i] & pmu->int_enable))
328 if (flag & pmu->cnt_ovf[i])
332 /* writeback clears overflow bits */
333 __asm__ __volatile__ ("mcr p14, 0, %0, c5, c1, 0" : : "r" (flag));
336 static irqreturn_t xscale_pmu_interrupt(int irq, void *arg)
341 if (pmu->id == PMU_XSC1)
346 for (i = CCNT; i < MAX_COUNTERS; i++) {
350 write_counter(i, -(u32)results[i].reset_counter);
351 oprofile_add_sample(get_irq_regs(), i);
355 pmnc = read_pmnc() | PMU_ENABLE;
361 static const struct pmu_irqs *pmu_irqs;
363 static void xscale_pmu_stop(void)
365 u32 pmnc = read_pmnc();
370 free_irq(pmu_irqs->irqs[0], results);
371 release_pmu(pmu_irqs);
375 static int xscale_pmu_start(void)
380 pmu_irqs = reserve_pmu();
381 if (IS_ERR(pmu_irqs))
382 return PTR_ERR(pmu_irqs);
386 ret = request_irq(pmu_irqs->irqs[0], xscale_pmu_interrupt,
387 IRQF_DISABLED, "XScale PMU", (void *)results);
390 printk(KERN_ERR "oprofile: unable to request IRQ%d for XScale PMU\n",
392 release_pmu(pmu_irqs);
397 if (pmu->id == PMU_XSC1)
398 pmnc |= pmu->int_enable;
400 __asm__ __volatile__ ("mcr p14, 0, %0, c4, c1, 0" : : "r" (pmu->int_enable));
406 pr_debug("xscale_pmu_start: pmnc: %#08x mask: %08x\n", pmnc, pmu->int_enable);
410 static int xscale_detect_pmu(void)
415 id = (read_cpuid(CPUID_ID) >> 13) & 0x7;
419 pmu = &pmu_parms[PMU_XSC1];
422 pmu = &pmu_parms[PMU_XSC2];
430 op_xscale_spec.name = pmu->name;
431 op_xscale_spec.num_counters = pmu->num_counters;
432 pr_debug("xscale_detect_pmu: detected %s PMU\n", pmu->name);
438 struct op_arm_model_spec op_xscale_spec = {
439 .init = xscale_detect_pmu,
440 .setup_ctrs = xscale_setup_ctrs,
441 .start = xscale_pmu_start,
442 .stop = xscale_pmu_stop,