2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 #include <linux/init.h>
24 #include <linux/irq.h>
25 #include <linux/gpio.h>
26 #include <mach/hardware.h>
27 #include <asm-generic/bug.h>
29 static struct mxc_gpio_port *mxc_gpio_ports;
30 static int gpio_table_size;
32 #define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2())
34 #define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00)
35 #define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04)
36 #define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08)
37 #define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
38 #define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10)
39 #define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14)
40 #define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
42 #define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0)
43 #define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1)
44 #define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2)
45 #define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3)
46 #define GPIO_INT_NONE 0x4
48 /* Note: This driver assumes 32 GPIOs are handled in one register */
50 static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
52 __raw_writel(1 << index, port->base + GPIO_ISR);
55 static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
60 l = __raw_readl(port->base + GPIO_IMR);
61 l = (l & (~(1 << index))) | (!!enable << index);
62 __raw_writel(l, port->base + GPIO_IMR);
65 static void gpio_ack_irq(u32 irq)
67 u32 gpio = irq_to_gpio(irq);
68 _clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);
71 static void gpio_mask_irq(u32 irq)
73 u32 gpio = irq_to_gpio(irq);
74 _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
77 static void gpio_unmask_irq(u32 irq)
79 u32 gpio = irq_to_gpio(irq);
80 _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
83 static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
85 static int gpio_set_irq_type(u32 irq, u32 type)
87 u32 gpio = irq_to_gpio(irq);
88 struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
91 void __iomem *reg = port->base;
93 port->both_edges &= ~(1 << (gpio & 31));
95 case IRQ_TYPE_EDGE_RISING:
96 edge = GPIO_INT_RISE_EDGE;
98 case IRQ_TYPE_EDGE_FALLING:
99 edge = GPIO_INT_FALL_EDGE;
101 case IRQ_TYPE_EDGE_BOTH:
102 val = mxc_gpio_get(&port->chip, gpio & 31);
104 edge = GPIO_INT_LOW_LEV;
105 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
107 edge = GPIO_INT_HIGH_LEV;
108 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
110 port->both_edges |= 1 << (gpio & 31);
112 case IRQ_TYPE_LEVEL_LOW:
113 edge = GPIO_INT_LOW_LEV;
115 case IRQ_TYPE_LEVEL_HIGH:
116 edge = GPIO_INT_HIGH_LEV;
122 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
124 val = __raw_readl(reg) & ~(0x3 << (bit << 1));
125 __raw_writel(val | (edge << (bit << 1)), reg);
126 _clear_gpio_irqstatus(port, gpio & 0x1f);
131 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
133 void __iomem *reg = port->base;
137 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
139 val = __raw_readl(reg);
140 edge = (val >> (bit << 1)) & 3;
141 val &= ~(0x3 << (bit << 1));
142 if (edge == GPIO_INT_HIGH_LEV) {
143 edge = GPIO_INT_LOW_LEV;
144 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
145 } else if (edge == GPIO_INT_LOW_LEV) {
146 edge = GPIO_INT_HIGH_LEV;
147 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
149 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
153 __raw_writel(val | (edge << (bit << 1)), reg);
156 /* handle 32 interrupts in one status register */
157 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
159 u32 gpio_irq_no_base = port->virtual_irq_start;
161 while (irq_stat != 0) {
162 int irqoffset = fls(irq_stat) - 1;
164 if (port->both_edges & (1 << irqoffset))
165 mxc_flip_edge(port, irqoffset);
167 generic_handle_irq(gpio_irq_no_base + irqoffset);
169 irq_stat &= ~(1 << irqoffset);
173 /* MX1 and MX3 has one interrupt *per* gpio port */
174 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
177 struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
179 irq_stat = __raw_readl(port->base + GPIO_ISR) &
180 __raw_readl(port->base + GPIO_IMR);
182 mxc_gpio_irq_handler(port, irq_stat);
185 /* MX2 has one interrupt *for all* gpio ports */
186 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
189 u32 irq_msk, irq_stat;
190 struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
192 /* walk through all interrupt status registers */
193 for (i = 0; i < gpio_table_size; i++) {
194 irq_msk = __raw_readl(port[i].base + GPIO_IMR);
198 irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk;
200 mxc_gpio_irq_handler(&port[i], irq_stat);
204 static struct irq_chip gpio_irq_chip = {
206 .mask = gpio_mask_irq,
207 .unmask = gpio_unmask_irq,
208 .set_type = gpio_set_irq_type,
211 static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
214 struct mxc_gpio_port *port =
215 container_of(chip, struct mxc_gpio_port, chip);
219 spin_lock_irqsave(&port->lock, flags);
220 l = __raw_readl(port->base + GPIO_GDIR);
225 __raw_writel(l, port->base + GPIO_GDIR);
226 spin_unlock_irqrestore(&port->lock, flags);
229 static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
231 struct mxc_gpio_port *port =
232 container_of(chip, struct mxc_gpio_port, chip);
233 void __iomem *reg = port->base + GPIO_DR;
237 spin_lock_irqsave(&port->lock, flags);
238 l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
239 __raw_writel(l, reg);
240 spin_unlock_irqrestore(&port->lock, flags);
243 static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
245 struct mxc_gpio_port *port =
246 container_of(chip, struct mxc_gpio_port, chip);
248 return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1;
251 static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
253 _set_gpio_direction(chip, offset, 0);
257 static int mxc_gpio_direction_output(struct gpio_chip *chip,
258 unsigned offset, int value)
260 mxc_gpio_set(chip, offset, value);
261 _set_gpio_direction(chip, offset, 1);
265 int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
269 /* save for local usage */
270 mxc_gpio_ports = port;
271 gpio_table_size = cnt;
273 printk(KERN_INFO "MXC GPIO hardware\n");
275 for (i = 0; i < cnt; i++) {
276 /* disable the interrupt and clear the status */
277 __raw_writel(0, port[i].base + GPIO_IMR);
278 __raw_writel(~0, port[i].base + GPIO_ISR);
279 for (j = port[i].virtual_irq_start;
280 j < port[i].virtual_irq_start + 32; j++) {
281 set_irq_chip(j, &gpio_irq_chip);
282 set_irq_handler(j, handle_level_irq);
283 set_irq_flags(j, IRQF_VALID);
286 /* register gpio chip */
287 port[i].chip.direction_input = mxc_gpio_direction_input;
288 port[i].chip.direction_output = mxc_gpio_direction_output;
289 port[i].chip.get = mxc_gpio_get;
290 port[i].chip.set = mxc_gpio_set;
291 port[i].chip.base = i * 32;
292 port[i].chip.ngpio = 32;
294 spin_lock_init(&port[i].lock);
296 /* its a serious configuration bug when it fails */
297 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
299 if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
300 /* setup one handler for each entry */
301 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
302 set_irq_data(port[i].irq, &port[i]);
303 if (port[i].irq_high) {
304 /* setup handler for GPIO 16 to 31 */
305 set_irq_chained_handler(port[i].irq_high,
306 mx3_gpio_irq_handler);
307 set_irq_data(port[i].irq_high, &port[i]);
313 /* setup one handler for all GPIO interrupts */
314 set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
315 set_irq_data(port[0].irq, port);