2 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 * Auto Generate file, please don't edit it
22 #ifndef __MACH_IOMUX_MX6Q_H__
23 #define __MACH_IOMUX_MX6Q_H__
25 #include <mach/iomux-v3.h>
28 * various IOMUX alternate output functions (1-7)
30 typedef enum iomux_config {
39 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
42 #define NON_MUX_I 0x3FF
43 #define NON_PAD_I 0x7FF
44 #define MX6Q_CCM_CLK0_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
45 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
46 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
48 #define MX6Q_HIGH_DRV (PAD_CTL_DSE_120ohm)
50 #define MX6Q_MLB150_PAD_CTRL (PAD_CTL_SPEED_LOW | \
51 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) \
53 #define MX6Q_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
54 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
55 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
57 #define MX6Q_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
58 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
59 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
61 #define MX6Q_USDHC_PAD_CTRL_100MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \
62 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \
63 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
65 #define MX6Q_USDHC_PAD_CTRL_200MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \
66 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
67 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
69 #define MX6Q_ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
70 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
71 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
73 #define MX6Q_DISP_PAD_CLT MX6Q_HIGH_DRV
75 #define MX6Q_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
76 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_40ohm | \
77 PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_SPEED_MED)
79 #define MX6Q_ESAI_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
80 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
82 #define MX6Q_GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
83 #define MX6Q_GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
84 #define MX6Q_GPMI_PAD_CTRL2 (MX6Q_GPMI_PAD_CTRL0 | MX6Q_GPMI_PAD_CTRL1)
86 #define MX6Q_SPDIF_OUT_PAD_CTRL (PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
87 #define MX6Q_USB_HSIC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
90 #define MX6Q_ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
91 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
93 #define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
94 IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
95 #define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
96 IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0)
97 #define _MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \
98 IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0)
99 #define _MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \
100 IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0)
101 #define _MX6Q_PAD_SD2_DAT1__KPP_COL_7 \
102 IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0)
103 #define _MX6Q_PAD_SD2_DAT1__GPIO_1_14 \
104 IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0)
105 #define _MX6Q_PAD_SD2_DAT1__CCM_WAIT \
106 IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0)
107 #define _MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \
108 IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0)
110 #define _MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \
111 IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0)
112 #define _MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \
113 IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0)
114 #define _MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \
115 IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0)
116 #define _MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \
117 IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0)
118 #define _MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \
119 IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0)
120 #define _MX6Q_PAD_SD2_DAT2__GPIO_1_13 \
121 IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0)
122 #define _MX6Q_PAD_SD2_DAT2__CCM_STOP \
123 IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0)
124 #define _MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \
125 IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0)
127 #define _MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \
128 IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0)
129 #define _MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \
130 IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0)
131 #define _MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
132 IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0)
133 #define _MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \
134 IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0)
135 #define _MX6Q_PAD_SD2_DAT0__GPIO_1_15 \
136 IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0)
137 #define _MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \
138 IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0)
139 #define _MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \
140 IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0)
142 #define _MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \
143 IOMUX_PAD(0x036C, 0x0058, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
144 #define _MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \
145 IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0)
146 #define _MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \
147 IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0)
148 #define _MX6Q_PAD_RGMII_TXC__GPIO_6_19 \
149 IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0)
150 #define _MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \
151 IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0)
152 #define _MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \
153 IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0)
155 #define _MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \
156 IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0)
157 #define _MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \
158 IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0)
159 #define _MX6Q_PAD_RGMII_TD0__GPIO_6_20 \
160 IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0)
161 #define _MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \
162 IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0)
164 #define _MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \
165 IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0)
166 #define _MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \
167 IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0)
168 #define _MX6Q_PAD_RGMII_TD1__GPIO_6_21 \
169 IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0)
170 #define _MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \
171 IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0)
172 #define _MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \
173 IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0)
175 #define _MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \
176 IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0)
177 #define _MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \
178 IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0)
179 #define _MX6Q_PAD_RGMII_TD2__GPIO_6_22 \
180 IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0)
181 #define _MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \
182 IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0)
183 #define _MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \
184 IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0)
186 #define _MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \
187 IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0)
188 #define _MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \
189 IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0)
190 #define _MX6Q_PAD_RGMII_TD3__GPIO_6_23 \
191 IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0)
192 #define _MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \
193 IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0)
195 #define _MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \
196 IOMUX_PAD(0x0380, 0x006C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
197 #define _MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \
198 IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0)
199 #define _MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \
200 IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0)
201 #define _MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \
202 IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0)
204 #define _MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \
205 IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0)
206 #define _MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \
207 IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0)
208 #define _MX6Q_PAD_RGMII_RD0__GPIO_6_25 \
209 IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0)
210 #define _MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \
211 IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0)
213 #define _MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \
214 IOMUX_PAD(0x0388, 0x0074, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
215 #define _MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \
216 IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0)
217 #define _MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \
218 IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0)
219 #define _MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \
220 IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0)
221 #define _MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \
222 IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0)
224 #define _MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \
225 IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0)
226 #define _MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \
227 IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0)
228 #define _MX6Q_PAD_RGMII_RD1__GPIO_6_27 \
229 IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0)
230 #define _MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \
231 IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0)
232 #define _MX6Q_PAD_RGMII_RD1__SJC_FAIL \
233 IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0)
235 #define _MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \
236 IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0)
237 #define _MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \
238 IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0)
239 #define _MX6Q_PAD_RGMII_RD2__GPIO_6_28 \
240 IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0)
241 #define _MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \
242 IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0)
244 #define _MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \
245 IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0)
246 #define _MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \
247 IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0)
248 #define _MX6Q_PAD_RGMII_RD3__GPIO_6_29 \
249 IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0)
250 #define _MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \
251 IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0)
253 #define _MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \
254 IOMUX_PAD(0x0398, 0x0084, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
255 #define _MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \
256 IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0)
257 #define _MX6Q_PAD_RGMII_RXC__GPIO_6_30 \
258 IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0)
259 #define _MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \
260 IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0)
262 #define _MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \
263 IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0)
264 #define _MX6Q_PAD_EIM_A25__ECSPI4_SS1 \
265 IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0)
266 #define _MX6Q_PAD_EIM_A25__ECSPI2_RDY \
267 IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0)
268 #define _MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \
269 IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0)
270 #define _MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \
271 IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0)
272 #define _MX6Q_PAD_EIM_A25__GPIO_5_2 \
273 IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0)
274 #define _MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \
275 IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0)
276 #define _MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \
277 IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0)
279 #define _MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \
280 IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0)
281 #define _MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \
282 IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0)
283 #define _MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \
284 IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0)
285 #define _MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \
286 IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0)
287 #define _MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \
288 IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0)
289 #define _MX6Q_PAD_EIM_EB2__GPIO_2_30 \
290 IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0)
291 #define _MX6Q_PAD_EIM_EB2__I2C2_SCL \
292 IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0)
293 #define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \
294 IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0)
296 #define _MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \
297 IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0)
298 #define _MX6Q_PAD_EIM_D16__ECSPI1_SCLK \
299 IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0)
300 #define _MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \
301 IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0)
302 #define _MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \
303 IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0)
304 #define _MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \
305 IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0)
306 #define _MX6Q_PAD_EIM_D16__GPIO_3_16 \
307 IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0)
308 #define _MX6Q_PAD_EIM_D16__I2C2_SDA \
309 IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0)
311 #define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \
312 IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0)
313 #define _MX6Q_PAD_EIM_D17__ECSPI1_MISO \
314 IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0)
315 #define _MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \
316 IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0)
317 #define _MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \
318 IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0)
319 #define _MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \
320 IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0)
321 #define _MX6Q_PAD_EIM_D17__GPIO_3_17 \
322 IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0)
323 #define _MX6Q_PAD_EIM_D17__I2C3_SCL \
324 IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0)
325 #define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \
326 IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0)
328 #define _MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \
329 IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0)
330 #define _MX6Q_PAD_EIM_D18__ECSPI1_MOSI \
331 IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0)
332 #define _MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \
333 IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0)
334 #define _MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \
335 IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0)
336 #define _MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \
337 IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0)
338 #define _MX6Q_PAD_EIM_D18__GPIO_3_18 \
339 IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0)
340 #define _MX6Q_PAD_EIM_D18__I2C3_SDA \
341 IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0)
342 #define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \
343 IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0)
345 #define _MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \
346 IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0)
347 #define _MX6Q_PAD_EIM_D19__ECSPI1_SS1 \
348 IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0)
349 #define _MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \
350 IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0)
351 #define _MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \
352 IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0)
353 #define _MX6Q_PAD_EIM_D19__UART1_CTS \
354 IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0)
355 #define _MX6Q_PAD_EIM_D19__GPIO_3_19 \
356 IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0)
357 #define _MX6Q_PAD_EIM_D19__EPIT1_EPITO \
358 IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0)
359 #define _MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \
360 IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0)
362 #define _MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \
363 IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0)
364 #define _MX6Q_PAD_EIM_D20__ECSPI4_SS0 \
365 IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0)
366 #define _MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \
367 IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0)
368 #define _MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \
369 IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0)
370 #define _MX6Q_PAD_EIM_D20__UART1_CTS \
371 IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0)
372 #define _MX6Q_PAD_EIM_D20__UART1_RTS \
373 IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0)
374 #define _MX6Q_PAD_EIM_D20__GPIO_3_20 \
375 IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0)
376 #define _MX6Q_PAD_EIM_D20__EPIT2_EPITO \
377 IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0)
379 #define _MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \
380 IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0)
381 #define _MX6Q_PAD_EIM_D21__ECSPI4_SCLK \
382 IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0)
383 #define _MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \
384 IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0)
385 #define _MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \
386 IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0)
387 #define _MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \
388 IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0)
389 #define _MX6Q_PAD_EIM_D21__GPIO_3_21 \
390 IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0)
391 #define _MX6Q_PAD_EIM_D21__I2C1_SCL \
392 IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0)
393 #define _MX6Q_PAD_EIM_D21__SPDIF_IN1 \
394 IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0)
396 #define _MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \
397 IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0)
398 #define _MX6Q_PAD_EIM_D22__ECSPI4_MISO \
399 IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0)
400 #define _MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \
401 IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0)
402 #define _MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \
403 IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0)
404 #define _MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \
405 IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0)
406 #define _MX6Q_PAD_EIM_D22__GPIO_3_22 \
407 IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0)
408 #define _MX6Q_PAD_EIM_D22__SPDIF_OUT1 \
409 IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0)
410 #define _MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \
411 IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0)
413 #define _MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \
414 IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0)
415 #define _MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \
416 IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0)
417 #define _MX6Q_PAD_EIM_D23__UART3_CTS \
418 IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0)
419 #define _MX6Q_PAD_EIM_D23__UART1_DCD \
420 IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0)
421 #define _MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \
422 IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0)
423 #define _MX6Q_PAD_EIM_D23__GPIO_3_23 \
424 IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0)
425 #define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \
426 IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0)
427 #define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \
428 IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0)
430 #define _MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \
431 IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0)
432 #define _MX6Q_PAD_EIM_EB3__ECSPI4_RDY \
433 IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0)
434 #define _MX6Q_PAD_EIM_EB3__UART3_CTS \
435 IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0)
436 #define _MX6Q_PAD_EIM_EB3__UART3_RTS \
437 IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0)
438 #define _MX6Q_PAD_EIM_EB3__UART1_RI \
439 IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0)
440 #define _MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \
441 IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0)
442 #define _MX6Q_PAD_EIM_EB3__GPIO_2_31 \
443 IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0)
444 #define _MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \
445 IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0)
446 #define _MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \
447 IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0)
449 #define _MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \
450 IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0)
451 #define _MX6Q_PAD_EIM_D24__ECSPI4_SS2 \
452 IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0)
453 #define _MX6Q_PAD_EIM_D24__UART3_TXD \
454 IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0)
455 #define _MX6Q_PAD_EIM_D24__UART3_RXD \
456 IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0)
457 #define _MX6Q_PAD_EIM_D24__ECSPI1_SS2 \
458 IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0)
459 #define _MX6Q_PAD_EIM_D24__ECSPI2_SS2 \
460 IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0)
461 #define _MX6Q_PAD_EIM_D24__GPIO_3_24 \
462 IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0)
463 #define _MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \
464 IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0)
465 #define _MX6Q_PAD_EIM_D24__UART1_DTR \
466 IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0)
468 #define _MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \
469 IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0)
470 #define _MX6Q_PAD_EIM_D25__ECSPI4_SS3 \
471 IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0)
472 #define _MX6Q_PAD_EIM_D25__UART3_TXD \
473 IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0)
474 #define _MX6Q_PAD_EIM_D25__UART3_RXD \
475 IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0)
476 #define _MX6Q_PAD_EIM_D25__ECSPI1_SS3 \
477 IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0)
478 #define _MX6Q_PAD_EIM_D25__ECSPI2_SS3 \
479 IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0)
480 #define _MX6Q_PAD_EIM_D25__GPIO_3_25 \
481 IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0)
482 #define _MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \
483 IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0)
484 #define _MX6Q_PAD_EIM_D25__UART1_DSR \
485 IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0)
487 #define _MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \
488 IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0)
489 #define _MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \
490 IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0)
491 #define _MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \
492 IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0)
493 #define _MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \
494 IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0)
495 #define _MX6Q_PAD_EIM_D26__UART2_TXD \
496 IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0)
497 #define _MX6Q_PAD_EIM_D26__UART2_RXD \
498 IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0)
499 #define _MX6Q_PAD_EIM_D26__GPIO_3_26 \
500 IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0)
501 #define _MX6Q_PAD_EIM_D26__IPU1_SISG_2 \
502 IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0)
503 #define _MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \
504 IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0)
506 #define _MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \
507 IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0)
508 #define _MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \
509 IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0)
510 #define _MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \
511 IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0)
512 #define _MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \
513 IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0)
514 #define _MX6Q_PAD_EIM_D27__UART2_TXD \
515 IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0)
516 #define _MX6Q_PAD_EIM_D27__UART2_RXD \
517 IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0)
518 #define _MX6Q_PAD_EIM_D27__GPIO_3_27 \
519 IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0)
520 #define _MX6Q_PAD_EIM_D27__IPU1_SISG_3 \
521 IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0)
522 #define _MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \
523 IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0)
525 #define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \
526 IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0)
527 #define _MX6Q_PAD_EIM_D28__I2C1_SDA \
528 IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0)
529 #define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI \
530 IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0)
531 #define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \
532 IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0)
533 #define _MX6Q_PAD_EIM_D28__UART2_CTS \
534 IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0)
535 #define _MX6Q_PAD_EIM_D28__UART2_RTS \
536 IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0)
537 #define _MX6Q_PAD_EIM_D28__GPIO_3_28 \
538 IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0)
539 #define _MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \
540 IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0)
541 #define _MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \
542 IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0)
544 #define _MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \
545 IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0)
546 #define _MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \
547 IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0)
548 #define _MX6Q_PAD_EIM_D29__ECSPI4_SS0 \
549 IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0)
550 #define _MX6Q_PAD_EIM_D29__UART2_CTS \
551 IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0)
552 #define _MX6Q_PAD_EIM_D29__UART2_RTS \
553 IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0)
554 #define _MX6Q_PAD_EIM_D29__GPIO_3_29 \
555 IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0)
556 #define _MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \
557 IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0)
558 #define _MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \
559 IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0)
561 #define _MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \
562 IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0)
563 #define _MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
564 IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0)
565 #define _MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \
566 IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0)
567 #define _MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \
568 IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0)
569 #define _MX6Q_PAD_EIM_D30__UART3_CTS \
570 IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0)
571 #define _MX6Q_PAD_EIM_D30__GPIO_3_30 \
572 IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0)
573 #define _MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \
574 IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0)
575 #define _MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \
576 IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0)
578 #define _MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \
579 IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0)
580 #define _MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
581 IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0)
582 #define _MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \
583 IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0)
584 #define _MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \
585 IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0)
586 #define _MX6Q_PAD_EIM_D31__UART3_CTS \
587 IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0)
588 #define _MX6Q_PAD_EIM_D31__UART3_RTS \
589 IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0)
590 #define _MX6Q_PAD_EIM_D31__GPIO_3_31 \
591 IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0)
592 #define _MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \
593 IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0)
594 #define _MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \
595 IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0)
597 #define _MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \
598 IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0)
599 #define _MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \
600 IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0)
601 #define _MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \
602 IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0)
603 #define _MX6Q_PAD_EIM_A24__IPU2_SISG_2 \
604 IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0)
605 #define _MX6Q_PAD_EIM_A24__IPU1_SISG_2 \
606 IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0)
607 #define _MX6Q_PAD_EIM_A24__GPIO_5_4 \
608 IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0)
609 #define _MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \
610 IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0)
611 #define _MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \
612 IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0)
614 #define _MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \
615 IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0)
616 #define _MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \
617 IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0)
618 #define _MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \
619 IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0)
620 #define _MX6Q_PAD_EIM_A23__IPU2_SISG_3 \
621 IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0)
622 #define _MX6Q_PAD_EIM_A23__IPU1_SISG_3 \
623 IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0)
624 #define _MX6Q_PAD_EIM_A23__GPIO_6_6 \
625 IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0)
626 #define _MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \
627 IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0)
628 #define _MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \
629 IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0)
631 #define _MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \
632 IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0)
633 #define _MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \
634 IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0)
635 #define _MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \
636 IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0)
637 #define _MX6Q_PAD_EIM_A22__GPIO_2_16 \
638 IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0)
639 #define _MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \
640 IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0)
641 #define _MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \
642 IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0)
644 #define _MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \
645 IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0)
646 #define _MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \
647 IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0)
648 #define _MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \
649 IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0)
650 #define _MX6Q_PAD_EIM_A21__RESERVED_RESERVED \
651 IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0)
652 #define _MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \
653 IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0)
654 #define _MX6Q_PAD_EIM_A21__GPIO_2_17 \
655 IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0)
656 #define _MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \
657 IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0)
658 #define _MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \
659 IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0)
661 #define _MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \
662 IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0)
663 #define _MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \
664 IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0)
665 #define _MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \
666 IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0)
667 #define _MX6Q_PAD_EIM_A20__RESERVED_RESERVED \
668 IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0)
669 #define _MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \
670 IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0)
671 #define _MX6Q_PAD_EIM_A20__GPIO_2_18 \
672 IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0)
673 #define _MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \
674 IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0)
675 #define _MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \
676 IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0)
678 #define _MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \
679 IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0)
680 #define _MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \
681 IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0)
682 #define _MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \
683 IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0)
684 #define _MX6Q_PAD_EIM_A19__RESERVED_RESERVED \
685 IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0)
686 #define _MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \
687 IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0)
688 #define _MX6Q_PAD_EIM_A19__GPIO_2_19 \
689 IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0)
690 #define _MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \
691 IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0)
692 #define _MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \
693 IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0)
695 #define _MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \
696 IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0)
697 #define _MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \
698 IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0)
699 #define _MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \
700 IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0)
701 #define _MX6Q_PAD_EIM_A18__RESERVED_RESERVED \
702 IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0)
703 #define _MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \
704 IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0)
705 #define _MX6Q_PAD_EIM_A18__GPIO_2_20 \
706 IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0)
707 #define _MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \
708 IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0)
709 #define _MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \
710 IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0)
712 #define _MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \
713 IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0)
714 #define _MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \
715 IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0)
716 #define _MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \
717 IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0)
718 #define _MX6Q_PAD_EIM_A17__RESERVED_RESERVED \
719 IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0)
720 #define _MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \
721 IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0)
722 #define _MX6Q_PAD_EIM_A17__GPIO_2_21 \
723 IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0)
724 #define _MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \
725 IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0)
726 #define _MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \
727 IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0)
729 #define _MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \
730 IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0)
731 #define _MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \
732 IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0)
733 #define _MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \
734 IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0)
735 #define _MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \
736 IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0)
737 #define _MX6Q_PAD_EIM_A16__GPIO_2_22 \
738 IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0)
739 #define _MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \
740 IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0)
741 #define _MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \
742 IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0)
744 #define _MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \
745 IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0)
746 #define _MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \
747 IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0)
748 #define _MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \
749 IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0)
750 #define _MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \
751 IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0)
752 #define _MX6Q_PAD_EIM_CS0__GPIO_2_23 \
753 IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0)
754 #define _MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \
755 IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0)
757 #define _MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \
758 IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0)
759 #define _MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \
760 IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0)
761 #define _MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \
762 IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0)
763 #define _MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \
764 IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0)
765 #define _MX6Q_PAD_EIM_CS1__GPIO_2_24 \
766 IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0)
767 #define _MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \
768 IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0)
770 #define _MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \
771 IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0)
772 #define _MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \
773 IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0)
774 #define _MX6Q_PAD_EIM_OE__ECSPI2_MISO \
775 IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0)
776 #define _MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \
777 IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0)
778 #define _MX6Q_PAD_EIM_OE__GPIO_2_25 \
779 IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0)
780 #define _MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \
781 IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0)
783 #define _MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \
784 IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0)
785 #define _MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \
786 IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0)
787 #define _MX6Q_PAD_EIM_RW__ECSPI2_SS0 \
788 IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0)
789 #define _MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \
790 IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0)
791 #define _MX6Q_PAD_EIM_RW__GPIO_2_26 \
792 IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0)
793 #define _MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \
794 IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0)
795 #define _MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \
796 IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0)
798 #define _MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \
799 IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0)
800 #define _MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \
801 IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0)
802 #define _MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \
803 IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0)
804 #define _MX6Q_PAD_EIM_LBA__GPIO_2_27 \
805 IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0)
806 #define _MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \
807 IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0)
808 #define _MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \
809 IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0)
811 #define _MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \
812 IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0)
813 #define _MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \
814 IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0)
815 #define _MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \
816 IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0)
817 #define _MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \
818 IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0)
819 #define _MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \
820 IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0)
821 #define _MX6Q_PAD_EIM_EB0__GPIO_2_28 \
822 IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0)
823 #define _MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \
824 IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0)
825 #define _MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \
826 IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0)
828 #define _MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \
829 IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0)
830 #define _MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \
831 IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0)
832 #define _MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \
833 IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0)
834 #define _MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \
835 IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0)
836 #define _MX6Q_PAD_EIM_EB1__GPIO_2_29 \
837 IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0)
838 #define _MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \
839 IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0)
840 #define _MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \
841 IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0)
843 #define _MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \
844 IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0)
845 #define _MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \
846 IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0)
847 #define _MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \
848 IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0)
849 #define _MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \
850 IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0)
851 #define _MX6Q_PAD_EIM_DA0__GPIO_3_0 \
852 IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0)
853 #define _MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \
854 IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0)
855 #define _MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \
856 IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0)
858 #define _MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \
859 IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0)
860 #define _MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \
861 IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0)
862 #define _MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \
863 IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0)
864 #define _MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \
865 IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0)
866 #define _MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \
867 IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0)
868 #define _MX6Q_PAD_EIM_DA1__GPIO_3_1 \
869 IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0)
870 #define _MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \
871 IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0)
872 #define _MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \
873 IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0)
875 #define _MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \
876 IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0)
877 #define _MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \
878 IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0)
879 #define _MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \
880 IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0)
881 #define _MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \
882 IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0)
883 #define _MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \
884 IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0)
885 #define _MX6Q_PAD_EIM_DA2__GPIO_3_2 \
886 IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0)
887 #define _MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \
888 IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0)
889 #define _MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \
890 IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0)
892 #define _MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \
893 IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0)
894 #define _MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \
895 IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0)
896 #define _MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \
897 IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0)
898 #define _MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \
899 IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0)
900 #define _MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \
901 IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0)
902 #define _MX6Q_PAD_EIM_DA3__GPIO_3_3 \
903 IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0)
904 #define _MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \
905 IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0)
906 #define _MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \
907 IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0)
909 #define _MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \
910 IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0)
911 #define _MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \
912 IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0)
913 #define _MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \
914 IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0)
915 #define _MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \
916 IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0)
917 #define _MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \
918 IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0)
919 #define _MX6Q_PAD_EIM_DA4__GPIO_3_4 \
920 IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0)
921 #define _MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \
922 IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0)
923 #define _MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \
924 IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0)
926 #define _MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \
927 IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0)
928 #define _MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \
929 IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0)
930 #define _MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \
931 IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0)
932 #define _MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \
933 IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0)
934 #define _MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \
935 IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0)
936 #define _MX6Q_PAD_EIM_DA5__GPIO_3_5 \
937 IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0)
938 #define _MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \
939 IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0)
940 #define _MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \
941 IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0)
943 #define _MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \
944 IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0)
945 #define _MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \
946 IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0)
947 #define _MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \
948 IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0)
949 #define _MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \
950 IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0)
951 #define _MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \
952 IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0)
953 #define _MX6Q_PAD_EIM_DA6__GPIO_3_6 \
954 IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0)
955 #define _MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \
956 IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0)
957 #define _MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \
958 IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0)
960 #define _MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \
961 IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0)
962 #define _MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \
963 IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0)
964 #define _MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \
965 IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0)
966 #define _MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \
967 IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0)
968 #define _MX6Q_PAD_EIM_DA7__GPIO_3_7 \
969 IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0)
970 #define _MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \
971 IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0)
972 #define _MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \
973 IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0)
975 #define _MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \
976 IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0)
977 #define _MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \
978 IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0)
979 #define _MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \
980 IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0)
981 #define _MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \
982 IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0)
983 #define _MX6Q_PAD_EIM_DA8__GPIO_3_8 \
984 IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0)
985 #define _MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \
986 IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0)
987 #define _MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \
988 IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0)
990 #define _MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \
991 IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0)
992 #define _MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \
993 IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0)
994 #define _MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \
995 IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0)
996 #define _MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \
997 IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0)
998 #define _MX6Q_PAD_EIM_DA9__GPIO_3_9 \
999 IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0)
1000 #define _MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \
1001 IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0)
1002 #define _MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \
1003 IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0)
1005 #define _MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \
1006 IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0)
1007 #define _MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \
1008 IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0)
1009 #define _MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \
1010 IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0)
1011 #define _MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \
1012 IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0)
1013 #define _MX6Q_PAD_EIM_DA10__GPIO_3_10 \
1014 IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0)
1015 #define _MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \
1016 IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0)
1017 #define _MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \
1018 IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0)
1020 #define _MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \
1021 IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0)
1022 #define _MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \
1023 IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0)
1024 #define _MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \
1025 IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0)
1026 #define _MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \
1027 IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0)
1028 #define _MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \
1029 IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0)
1030 #define _MX6Q_PAD_EIM_DA11__GPIO_3_11 \
1031 IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0)
1032 #define _MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \
1033 IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0)
1034 #define _MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \
1035 IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0)
1037 #define _MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \
1038 IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0)
1039 #define _MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \
1040 IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0)
1041 #define _MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \
1042 IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0)
1043 #define _MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \
1044 IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0)
1045 #define _MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \
1046 IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0)
1047 #define _MX6Q_PAD_EIM_DA12__GPIO_3_12 \
1048 IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0)
1049 #define _MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \
1050 IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0)
1051 #define _MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \
1052 IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0)
1054 #define _MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \
1055 IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0)
1056 #define _MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \
1057 IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0)
1058 #define _MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \
1059 IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0)
1060 #define _MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \
1061 IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0)
1062 #define _MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \
1063 IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0)
1064 #define _MX6Q_PAD_EIM_DA13__GPIO_3_13 \
1065 IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0)
1066 #define _MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \
1067 IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0)
1068 #define _MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \
1069 IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0)
1071 #define _MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \
1072 IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0)
1073 #define _MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \
1074 IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0)
1075 #define _MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \
1076 IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0)
1077 #define _MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \
1078 IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0)
1079 #define _MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \
1080 IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0)
1081 #define _MX6Q_PAD_EIM_DA14__GPIO_3_14 \
1082 IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0)
1083 #define _MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \
1084 IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0)
1085 #define _MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \
1086 IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0)
1088 #define _MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \
1089 IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0)
1090 #define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \
1091 IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0)
1092 #define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \
1093 IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0)
1094 #define _MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \
1095 IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0)
1096 #define _MX6Q_PAD_EIM_DA15__GPIO_3_15 \
1097 IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0)
1098 #define _MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \
1099 IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0)
1100 #define _MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \
1101 IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0)
1103 #define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \
1104 IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0)
1105 #define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \
1106 IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0)
1107 #define _MX6Q_PAD_EIM_WAIT__GPIO_5_0 \
1108 IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0)
1109 #define _MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \
1110 IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0)
1111 #define _MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \
1112 IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0)
1114 #define _MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \
1115 IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0)
1116 #define _MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \
1117 IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0)
1118 #define _MX6Q_PAD_EIM_BCLK__GPIO_6_31 \
1119 IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0)
1120 #define _MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \
1121 IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0)
1123 #define _MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \
1124 IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0)
1125 #define _MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \
1126 IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0)
1127 #define _MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \
1128 IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0)
1129 #define _MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \
1130 IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0)
1131 #define _MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \
1132 IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0)
1133 #define _MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \
1134 IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0)
1136 #define _MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \
1137 IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0)
1138 #define _MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \
1139 IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0)
1140 #define _MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \
1141 IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0)
1142 #define _MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \
1143 IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0)
1144 #define _MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \
1145 IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0)
1146 #define _MX6Q_PAD_DI0_PIN15__GPIO_4_17 \
1147 IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0)
1148 #define _MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \
1149 IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0)
1151 #define _MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \
1152 IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0)
1153 #define _MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \
1154 IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0)
1155 #define _MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \
1156 IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0)
1157 #define _MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \
1158 IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0)
1159 #define _MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \
1160 IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0)
1161 #define _MX6Q_PAD_DI0_PIN2__GPIO_4_18 \
1162 IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0)
1163 #define _MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \
1164 IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0)
1165 #define _MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \
1166 IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0)
1168 #define _MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \
1169 IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0)
1170 #define _MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \
1171 IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0)
1172 #define _MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \
1173 IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0)
1174 #define _MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \
1175 IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0)
1176 #define _MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \
1177 IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0)
1178 #define _MX6Q_PAD_DI0_PIN3__GPIO_4_19 \
1179 IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0)
1180 #define _MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \
1181 IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0)
1182 #define _MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \
1183 IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0)
1185 #define _MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \
1186 IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0)
1187 #define _MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \
1188 IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0)
1189 #define _MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \
1190 IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0)
1191 #define _MX6Q_PAD_DI0_PIN4__USDHC1_WP \
1192 IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0)
1193 #define _MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \
1194 IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0)
1195 #define _MX6Q_PAD_DI0_PIN4__GPIO_4_20 \
1196 IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0)
1197 #define _MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \
1198 IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0)
1199 #define _MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \
1200 IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0)
1202 #define _MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \
1203 IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0)
1204 #define _MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \
1205 IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0)
1206 #define _MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \
1207 IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0)
1208 #define _MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \
1209 IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0)
1210 #define _MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \
1211 IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0)
1212 #define _MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \
1213 IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0)
1214 #define _MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \
1215 IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0)
1217 #define _MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \
1218 IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0)
1219 #define _MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \
1220 IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0)
1221 #define _MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \
1222 IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0)
1223 #define _MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \
1224 IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0)
1225 #define _MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
1226 IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0)
1227 #define _MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \
1228 IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0)
1229 #define _MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \
1230 IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0)
1231 #define _MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \
1232 IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0)
1234 #define _MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \
1235 IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0)
1236 #define _MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \
1237 IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0)
1238 #define _MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \
1239 IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0)
1240 #define _MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \
1241 IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0)
1242 #define _MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \
1243 IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0)
1244 #define _MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \
1245 IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0)
1246 #define _MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \
1247 IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0)
1248 #define _MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \
1249 IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0)
1251 #define _MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \
1252 IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0)
1253 #define _MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \
1254 IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0)
1255 #define _MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \
1256 IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0)
1257 #define _MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \
1258 IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0)
1259 #define _MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \
1260 IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0)
1261 #define _MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \
1262 IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0)
1263 #define _MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \
1264 IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0)
1265 #define _MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \
1266 IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0)
1268 #define _MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \
1269 IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0)
1270 #define _MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \
1271 IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0)
1272 #define _MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \
1273 IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0)
1274 #define _MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \
1275 IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0)
1276 #define _MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \
1277 IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0)
1278 #define _MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \
1279 IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0)
1280 #define _MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \
1281 IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0)
1282 #define _MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \
1283 IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0)
1285 #define _MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \
1286 IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0)
1287 #define _MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \
1288 IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0)
1289 #define _MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \
1290 IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0)
1291 #define _MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \
1292 IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0)
1293 #define _MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \
1294 IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0)
1295 #define _MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \
1296 IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0)
1297 #define _MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \
1298 IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0)
1299 #define _MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \
1300 IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0)
1302 #define _MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \
1303 IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0)
1304 #define _MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \
1305 IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0)
1306 #define _MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \
1307 IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0)
1308 #define _MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \
1309 IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0)
1310 #define _MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \
1311 IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0)
1312 #define _MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \
1313 IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0)
1314 #define _MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \
1315 IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0)
1316 #define _MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \
1317 IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0)
1319 #define _MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \
1320 IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0)
1321 #define _MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \
1322 IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0)
1323 #define _MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \
1324 IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0)
1325 #define _MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \
1326 IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0)
1327 #define _MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \
1328 IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0)
1329 #define _MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \
1330 IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0)
1331 #define _MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \
1332 IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0)
1333 #define _MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \
1334 IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0)
1336 #define _MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \
1337 IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0)
1338 #define _MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \
1339 IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0)
1340 #define _MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \
1341 IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0)
1342 #define _MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \
1343 IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0)
1344 #define _MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \
1345 IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0)
1346 #define _MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \
1347 IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0)
1348 #define _MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \
1349 IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0)
1350 #define _MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \
1351 IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0)
1353 #define _MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \
1354 IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0)
1355 #define _MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \
1356 IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0)
1357 #define _MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \
1358 IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0)
1359 #define _MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \
1360 IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0)
1361 #define _MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \
1362 IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0)
1363 #define _MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \
1364 IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0)
1365 #define _MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \
1366 IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0)
1367 #define _MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \
1368 IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0)
1370 #define _MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \
1371 IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0)
1372 #define _MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \
1373 IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0)
1374 #define _MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \
1375 IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0)
1376 #define _MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
1377 IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0)
1378 #define _MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \
1379 IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0)
1380 #define _MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \
1381 IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0)
1382 #define _MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \
1383 IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0)
1385 #define _MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \
1386 IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0)
1387 #define _MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \
1388 IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0)
1389 #define _MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \
1390 IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0)
1391 #define _MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
1392 IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0)
1393 #define _MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \
1394 IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0)
1395 #define _MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \
1396 IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0)
1397 #define _MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \
1398 IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0)
1400 #define _MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \
1401 IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0)
1402 #define _MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \
1403 IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0)
1404 #define _MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED \
1405 IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0)
1406 #define _MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
1407 IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0)
1408 #define _MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \
1409 IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0)
1410 #define _MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \
1411 IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0)
1412 #define _MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \
1413 IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0)
1415 #define _MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \
1416 IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0)
1417 #define _MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \
1418 IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0)
1419 #define _MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \
1420 IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0)
1421 #define _MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
1422 IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0)
1423 #define _MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \
1424 IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0)
1425 #define _MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \
1426 IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0)
1427 #define _MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \
1428 IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0)
1430 #define _MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \
1431 IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0)
1432 #define _MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \
1433 IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0)
1434 #define _MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \
1435 IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0)
1436 #define _MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
1437 IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0)
1438 #define _MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \
1439 IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0)
1440 #define _MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \
1441 IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0)
1443 #define _MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \
1444 IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0)
1445 #define _MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \
1446 IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0)
1447 #define _MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \
1448 IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0)
1449 #define _MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \
1450 IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0)
1451 #define _MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
1452 IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0)
1453 #define _MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \
1454 IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0)
1455 #define _MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \
1456 IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0)
1457 #define _MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \
1458 IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0)
1460 #define _MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \
1461 IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0)
1462 #define _MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \
1463 IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0)
1464 #define _MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \
1465 IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0)
1466 #define _MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \
1467 IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0)
1468 #define _MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \
1469 IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0)
1470 #define _MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \
1471 IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0)
1472 #define _MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \
1473 IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0)
1474 #define _MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \
1475 IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0)
1477 #define _MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \
1478 IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0)
1479 #define _MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \
1480 IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0)
1481 #define _MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \
1482 IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0)
1483 #define _MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \
1484 IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0)
1485 #define _MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \
1486 IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0)
1487 #define _MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \
1488 IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0)
1489 #define _MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \
1490 IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0)
1491 #define _MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \
1492 IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0)
1494 #define _MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \
1495 IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0)
1496 #define _MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \
1497 IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0)
1498 #define _MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \
1499 IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0)
1500 #define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \
1501 IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0)
1502 #define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \
1503 IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0)
1504 #define _MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \
1505 IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0)
1506 #define _MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \
1507 IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0)
1508 #define _MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \
1509 IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0)
1511 #define _MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \
1512 IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0)
1513 #define _MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \
1514 IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0)
1515 #define _MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \
1516 IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0)
1517 #define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \
1518 IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0)
1519 #define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \
1520 IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0)
1521 #define _MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \
1522 IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0)
1523 #define _MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \
1524 IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0)
1525 #define _MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \
1526 IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0)
1528 #define _MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \
1529 IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0)
1530 #define _MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \
1531 IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0)
1532 #define _MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \
1533 IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0)
1534 #define _MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \
1535 IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0)
1536 #define _MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
1537 IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0)
1538 #define _MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \
1539 IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0)
1540 #define _MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \
1541 IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0)
1542 #define _MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \
1543 IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0)
1545 #define _MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \
1546 IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0)
1547 #define _MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \
1548 IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0)
1549 #define _MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \
1550 IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0)
1551 #define _MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \
1552 IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0)
1553 #define _MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \
1554 IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0)
1555 #define _MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \
1556 IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0)
1557 #define _MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \
1558 IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0)
1559 #define _MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \
1560 IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0)
1562 #define _MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \
1563 IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0)
1564 #define _MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \
1565 IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0)
1566 #define _MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \
1567 IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0)
1568 #define _MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \
1569 IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0)
1570 #define _MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \
1571 IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0)
1572 #define _MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \
1573 IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0)
1574 #define _MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \
1575 IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0)
1576 #define _MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \
1577 IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0)
1579 #define _MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \
1580 IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0)
1581 #define _MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \
1582 IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0)
1583 #define _MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \
1584 IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0)
1585 #define _MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \
1586 IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0)
1587 #define _MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \
1588 IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0)
1589 #define _MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \
1590 IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0)
1591 #define _MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \
1592 IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0)
1593 #define _MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \
1594 IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0)
1596 #define _MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED \
1597 IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0)
1598 #define _MX6Q_PAD_ENET_MDIO__ENET_MDIO \
1599 IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0)
1600 #define _MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \
1601 IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0)
1602 #define _MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \
1603 IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0)
1604 #define _MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \
1605 IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0)
1606 #define _MX6Q_PAD_ENET_MDIO__GPIO_1_22 \
1607 IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0)
1608 #define _MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \
1609 IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0)
1611 #define _MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED \
1612 IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0)
1613 #define _MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \
1614 IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0)
1615 #define _MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \
1616 IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0)
1617 #define _MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \
1618 IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0)
1619 #define _MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \
1620 IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0)
1621 #define _MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \
1622 IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0)
1623 #define _MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \
1624 IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0)
1626 #define _MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \
1627 IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0)
1628 #define _MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \
1629 IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0)
1630 #define _MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \
1631 IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0)
1632 #define _MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \
1633 IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0)
1634 #define _MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \
1635 IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0)
1636 #define _MX6Q_PAD_ENET_RX_ER__PHY_TDI \
1637 IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0)
1638 #define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \
1639 IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0)
1641 #define _MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED \
1642 IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0)
1643 #define _MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \
1644 IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0)
1645 #define _MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \
1646 IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0)
1647 #define _MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \
1648 IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0)
1649 #define _MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \
1650 IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0)
1651 #define _MX6Q_PAD_ENET_CRS_DV__PHY_TDO \
1652 IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0)
1653 #define _MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \
1654 IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0)
1656 #define _MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \
1657 IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0)
1658 #define _MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \
1659 IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0)
1660 #define _MX6Q_PAD_ENET_RXD1__ESAI1_FST \
1661 IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0)
1662 #define _MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \
1663 IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0)
1664 #define _MX6Q_PAD_ENET_RXD1__GPIO_1_26 \
1665 IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0)
1666 #define _MX6Q_PAD_ENET_RXD1__PHY_TCK \
1667 IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0)
1668 #define _MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \
1669 IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0)
1671 #define _MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \
1672 IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0)
1673 #define _MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \
1674 IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0)
1675 #define _MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \
1676 IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0)
1677 #define _MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \
1678 IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0)
1679 #define _MX6Q_PAD_ENET_RXD0__GPIO_1_27 \
1680 IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0)
1681 #define _MX6Q_PAD_ENET_RXD0__PHY_TMS \
1682 IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0)
1683 #define _MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \
1684 IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0)
1686 #define _MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED \
1687 IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0)
1688 #define _MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \
1689 IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0)
1690 #define _MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \
1691 IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0)
1692 #define _MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \
1693 IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0)
1694 #define _MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \
1695 IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0)
1696 #define _MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \
1697 IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0)
1699 #define _MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \
1700 IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0)
1701 #define _MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \
1702 IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0)
1703 #define _MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \
1704 IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0)
1705 #define _MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \
1706 IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0)
1707 #define _MX6Q_PAD_ENET_TXD1__GPIO_1_29 \
1708 IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0)
1709 #define _MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \
1710 IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0)
1711 #define _MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \
1712 IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0)
1714 #define _MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED \
1715 IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0)
1716 #define _MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \
1717 IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0)
1718 #define _MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \
1719 IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0)
1720 #define _MX6Q_PAD_ENET_TXD0__GPIO_1_30 \
1721 IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0)
1722 #define _MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \
1723 IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0)
1724 #define _MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \
1725 IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0)
1727 #define _MX6Q_PAD_ENET_MDC__MLB_MLBDAT \
1728 IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0)
1729 #define _MX6Q_PAD_ENET_MDC__ENET_MDC \
1730 IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0)
1731 #define _MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \
1732 IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0)
1733 #define _MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \
1734 IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0)
1735 #define _MX6Q_PAD_ENET_MDC__GPIO_1_31 \
1736 IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0)
1737 #define _MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \
1738 IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0)
1739 #define _MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \
1740 IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0)
1742 #define _MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \
1743 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1745 #define _MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \
1746 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1748 #define _MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \
1749 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1751 #define _MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \
1752 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1754 #define _MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \
1755 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1757 #define _MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \
1758 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1760 #define _MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \
1761 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1763 #define _MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \
1764 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1766 #define _MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \
1767 IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0)
1769 #define _MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \
1770 IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0)
1772 #define _MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \
1773 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1775 #define _MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \
1776 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1778 #define _MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \
1779 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1781 #define _MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \
1782 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1784 #define _MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \
1785 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1787 #define _MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \
1788 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1790 #define _MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \
1791 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1793 #define _MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \
1794 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1796 #define _MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \
1797 IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0)
1799 #define _MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \
1800 IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0)
1802 #define _MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \
1803 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1805 #define _MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \
1806 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1808 #define _MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \
1809 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1811 #define _MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \
1812 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1814 #define _MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \
1815 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1817 #define _MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \
1818 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1820 #define _MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \
1821 IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0)
1823 #define _MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \
1824 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1826 #define _MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \
1827 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1829 #define _MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \
1830 IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0)
1832 #define _MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \
1833 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1835 #define _MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \
1836 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1838 #define _MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \
1839 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1841 #define _MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \
1842 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1844 #define _MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \
1845 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1847 #define _MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \
1848 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1850 #define _MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \
1851 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1853 #define _MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \
1854 IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0)
1856 #define _MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \
1857 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1859 #define _MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \
1860 IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0)
1862 #define _MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \
1863 IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0)
1865 #define _MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \
1866 IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0)
1868 #define _MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \
1869 IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0)
1871 #define _MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \
1872 IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0)
1874 #define _MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \
1875 IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0)
1877 #define _MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \
1878 IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0)
1880 #define _MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \
1881 IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0)
1883 #define _MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \
1884 IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0)
1886 #define _MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \
1887 IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0)
1889 #define _MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \
1890 IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0)
1892 #define _MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \
1893 IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0)
1895 #define _MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \
1896 IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0)
1898 #define _MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \
1899 IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0)
1901 #define _MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \
1902 IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0)
1904 #define _MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \
1905 IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0)
1907 #define _MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \
1908 IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0)
1910 #define _MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \
1911 IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0)
1913 #define _MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \
1914 IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0)
1916 #define _MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \
1917 IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0)
1919 #define _MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \
1920 IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0)
1922 #define _MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \
1923 IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0)
1925 #define _MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \
1926 IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0)
1928 #define _MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \
1929 IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0)
1931 #define _MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \
1932 IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0)
1934 #define _MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \
1935 IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0)
1937 #define _MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \
1938 IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0)
1940 #define _MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \
1941 IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0)
1943 #define _MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \
1944 IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0)
1946 #define _MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \
1947 IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0)
1949 #define _MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \
1950 IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0)
1952 #define _MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \
1953 IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0)
1955 #define _MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \
1956 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1958 #define _MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \
1959 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1961 #define _MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \
1962 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1964 #define _MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \
1965 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1967 #define _MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \
1968 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1970 #define _MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \
1971 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1973 #define _MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \
1974 IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0)
1976 #define _MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \
1977 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1979 #define _MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \
1980 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1982 #define _MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \
1983 IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0)
1985 #define _MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \
1986 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1988 #define _MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \
1989 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1991 #define _MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \
1992 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1994 #define _MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \
1995 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1997 #define _MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \
1998 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2000 #define _MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \
2001 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2003 #define _MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \
2004 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2006 #define _MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \
2007 IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0)
2009 #define _MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \
2010 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2012 #define _MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \
2013 IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0)
2015 #define _MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \
2016 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2018 #define _MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \
2019 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2021 #define _MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \
2022 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2024 #define _MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \
2025 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2027 #define _MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \
2028 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2030 #define _MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \
2031 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2033 #define _MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \
2034 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2036 #define _MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \
2037 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2039 #define _MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \
2040 IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0)
2042 #define _MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \
2043 IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0)
2045 #define _MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \
2046 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2048 #define _MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \
2049 IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0)
2051 #define _MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \
2052 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2054 #define _MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \
2055 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2057 #define _MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \
2058 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2060 #define _MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \
2061 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2063 #define _MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \
2064 IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0)
2066 #define _MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \
2067 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2069 #define _MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \
2070 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2072 #define _MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \
2073 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2075 #define _MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \
2076 IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0)
2077 #define _MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \
2078 IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0)
2079 #define _MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \
2080 IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0)
2081 #define _MX6Q_PAD_KEY_COL0__KPP_COL_0 \
2082 IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0)
2083 #define _MX6Q_PAD_KEY_COL0__UART4_TXD \
2084 IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0)
2085 #define _MX6Q_PAD_KEY_COL0__UART4_RXD \
2086 IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0)
2087 #define _MX6Q_PAD_KEY_COL0__GPIO_4_6 \
2088 IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0)
2089 #define _MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \
2090 IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0)
2091 #define _MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \
2092 IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0)
2094 #define _MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \
2095 IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0)
2096 #define _MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \
2097 IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0)
2098 #define _MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \
2099 IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0)
2100 #define _MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \
2101 IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0)
2102 #define _MX6Q_PAD_KEY_ROW0__UART4_TXD \
2103 IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0)
2104 #define _MX6Q_PAD_KEY_ROW0__UART4_RXD \
2105 IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0)
2106 #define _MX6Q_PAD_KEY_ROW0__GPIO_4_7 \
2107 IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0)
2108 #define _MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \
2109 IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0)
2110 #define _MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \
2111 IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0)
2113 #define _MX6Q_PAD_KEY_COL1__ECSPI1_MISO \
2114 IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0)
2115 #define _MX6Q_PAD_KEY_COL1__ENET_MDIO \
2116 IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0)
2117 #define _MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \
2118 IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0)
2119 #define _MX6Q_PAD_KEY_COL1__KPP_COL_1 \
2120 IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0)
2121 #define _MX6Q_PAD_KEY_COL1__UART5_TXD \
2122 IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0)
2123 #define _MX6Q_PAD_KEY_COL1__UART5_RXD \
2124 IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0)
2125 #define _MX6Q_PAD_KEY_COL1__GPIO_4_8 \
2126 IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0)
2127 #define _MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \
2128 IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0)
2129 #define _MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \
2130 IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0)
2132 #define _MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \
2133 IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0)
2134 #define _MX6Q_PAD_KEY_ROW1__ENET_COL \
2135 IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0)
2136 #define _MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \
2137 IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0)
2138 #define _MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \
2139 IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0)
2140 #define _MX6Q_PAD_KEY_ROW1__UART5_TXD \
2141 IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0)
2142 #define _MX6Q_PAD_KEY_ROW1__UART5_RXD \
2143 IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0)
2144 #define _MX6Q_PAD_KEY_ROW1__GPIO_4_9 \
2145 IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0)
2146 #define _MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \
2147 IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0)
2148 #define _MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \
2149 IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0)
2151 #define _MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \
2152 IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0)
2153 #define _MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \
2154 IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0)
2155 #define _MX6Q_PAD_KEY_COL2__CAN1_TXCAN \
2156 IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0)
2157 #define _MX6Q_PAD_KEY_COL2__KPP_COL_2 \
2158 IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0)
2159 #define _MX6Q_PAD_KEY_COL2__ENET_MDC \
2160 IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0)
2161 #define _MX6Q_PAD_KEY_COL2__GPIO_4_10 \
2162 IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0)
2163 #define _MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \
2164 IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0)
2165 #define _MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \
2166 IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0)
2168 #define _MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \
2169 IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0)
2170 #define _MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \
2171 IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0)
2172 #define _MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \
2173 IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0)
2174 #define _MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \
2175 IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0)
2176 #define _MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \
2177 IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0)
2178 #define _MX6Q_PAD_KEY_ROW2__GPIO_4_11 \
2179 IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0)
2180 #define _MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \
2181 IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0)
2182 #define _MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \
2183 IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0)
2185 #define _MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \
2186 IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0)
2187 #define _MX6Q_PAD_KEY_COL3__ENET_CRS \
2188 IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0)
2189 #define _MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \
2190 IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0)
2191 #define _MX6Q_PAD_KEY_COL3__KPP_COL_3 \
2192 IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0)
2193 #define _MX6Q_PAD_KEY_COL3__I2C2_SCL \
2194 IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0)
2195 #define _MX6Q_PAD_KEY_COL3__GPIO_4_12 \
2196 IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0)
2197 #define _MX6Q_PAD_KEY_COL3__SPDIF_IN1 \
2198 IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0)
2199 #define _MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \
2200 IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0)
2202 #define _MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \
2203 IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0)
2204 #define _MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \
2205 IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0)
2206 #define _MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \
2207 IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0)
2208 #define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \
2209 IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0)
2210 #define _MX6Q_PAD_KEY_ROW3__I2C2_SDA \
2211 IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0)
2212 #define _MX6Q_PAD_KEY_ROW3__GPIO_4_13 \
2213 IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0)
2214 #define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \
2215 IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0)
2216 #define _MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \
2217 IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0)
2219 #define _MX6Q_PAD_KEY_COL4__CAN2_TXCAN \
2220 IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0)
2221 #define _MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \
2222 IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0)
2223 #define _MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \
2224 IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0)
2225 #define _MX6Q_PAD_KEY_COL4__KPP_COL_4 \
2226 IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0)
2227 #define _MX6Q_PAD_KEY_COL4__UART5_CTS \
2228 IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0)
2229 #define _MX6Q_PAD_KEY_COL4__UART5_RTS \
2230 IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0)
2231 #define _MX6Q_PAD_KEY_COL4__GPIO_4_14 \
2232 IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0)
2233 #define _MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \
2234 IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0)
2235 #define _MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \
2236 IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0)
2238 #define _MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \
2239 IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0)
2240 #define _MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \
2241 IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0)
2242 #define _MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \
2243 IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0)
2244 #define _MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \
2245 IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0)
2246 #define _MX6Q_PAD_KEY_ROW4__UART5_CTS \
2247 IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0)
2248 #define _MX6Q_PAD_KEY_ROW4__GPIO_4_15 \
2249 IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0)
2250 #define _MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \
2251 IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0)
2252 #define _MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \
2253 IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0)
2255 #define _MX6Q_PAD_GPIO_0__CCM_CLKO \
2256 IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0)
2257 #define _MX6Q_PAD_GPIO_0__KPP_COL_5 \
2258 IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0)
2259 #define _MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \
2260 IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0)
2261 #define _MX6Q_PAD_GPIO_0__EPIT1_EPITO \
2262 IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0)
2263 #define _MX6Q_PAD_GPIO_0__GPIO_1_0 \
2264 IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0)
2265 #define _MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \
2266 IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0)
2267 #define _MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \
2268 IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0)
2270 #define _MX6Q_PAD_GPIO_1__ESAI1_SCKR \
2271 IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0)
2272 #define _MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \
2273 IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0)
2274 #define _MX6Q_PAD_GPIO_1__KPP_ROW_5 \
2275 IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0)
2276 #define MX6Q_PAD_GPIO_1__USBOTG_ID \
2277 IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, MX6Q_USDHC_PAD_CTRL)
2278 #define _MX6Q_PAD_GPIO_1__PWM2_PWMO \
2279 IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0)
2280 #define _MX6Q_PAD_GPIO_1__GPIO_1_1 \
2281 IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0)
2282 #define _MX6Q_PAD_GPIO_1__USDHC1_CD \
2283 IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0)
2284 #define _MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \
2285 IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0)
2287 #define _MX6Q_PAD_GPIO_9__ESAI1_FSR \
2288 IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0)
2289 #define _MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \
2290 IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0)
2291 #define _MX6Q_PAD_GPIO_9__KPP_COL_6 \
2292 IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0)
2293 #define _MX6Q_PAD_GPIO_9__CCM_REF_EN_B \
2294 IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0)
2295 #define _MX6Q_PAD_GPIO_9__PWM1_PWMO \
2296 IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0)
2297 #define _MX6Q_PAD_GPIO_9__GPIO_1_9 \
2298 IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0)
2299 #define _MX6Q_PAD_GPIO_9__USDHC1_WP \
2300 IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0)
2301 #define _MX6Q_PAD_GPIO_9__SRC_EARLY_RST \
2302 IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0)
2304 #define _MX6Q_PAD_GPIO_3__ESAI1_HCKR \
2305 IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0)
2306 #define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \
2307 IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0)
2308 #define _MX6Q_PAD_GPIO_3__I2C3_SCL \
2309 IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0)
2310 #define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \
2311 IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0)
2312 #define _MX6Q_PAD_GPIO_3__CCM_CLKO2 \
2313 IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0)
2314 #define _MX6Q_PAD_GPIO_3__GPIO_1_3 \
2315 IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0)
2316 #define _MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \
2317 IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0)
2318 #define _MX6Q_PAD_GPIO_3__MLB_MLBCLK \
2319 IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0)
2321 #define _MX6Q_PAD_GPIO_6__ESAI1_SCKT \
2322 IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0)
2323 #define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
2324 IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0)
2325 #define _MX6Q_PAD_GPIO_6__I2C3_SDA \
2326 IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0)
2327 #define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \
2328 IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0)
2329 #define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \
2330 IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0)
2331 #define _MX6Q_PAD_GPIO_6__GPIO_1_6 \
2332 IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0)
2333 #define _MX6Q_PAD_GPIO_6__USDHC2_LCTL \
2334 IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0)
2335 #define _MX6Q_PAD_GPIO_6__MLB_MLBSIG \
2336 IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0)
2338 #define _MX6Q_PAD_GPIO_2__ESAI1_FST \
2339 IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0)
2340 #define _MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \
2341 IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0)
2342 #define _MX6Q_PAD_GPIO_2__KPP_ROW_6 \
2343 IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0)
2344 #define _MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \
2345 IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0)
2346 #define _MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \
2347 IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0)
2348 #define _MX6Q_PAD_GPIO_2__GPIO_1_2 \
2349 IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0)
2350 #define _MX6Q_PAD_GPIO_2__USDHC2_WP \
2351 IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0)
2352 #define _MX6Q_PAD_GPIO_2__MLB_MLBDAT \
2353 IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0)
2355 #define _MX6Q_PAD_GPIO_4__ESAI1_HCKT \
2356 IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0)
2357 #define _MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \
2358 IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0)
2359 #define _MX6Q_PAD_GPIO_4__KPP_COL_7 \
2360 IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0)
2361 #define _MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \
2362 IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0)
2363 #define _MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \
2364 IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0)
2365 #define _MX6Q_PAD_GPIO_4__GPIO_1_4 \
2366 IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0)
2367 #define _MX6Q_PAD_GPIO_4__USDHC2_CD \
2368 IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0)
2369 #define _MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \
2370 IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0)
2372 #define _MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \
2373 IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0)
2374 #define _MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \
2375 IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0)
2376 #define _MX6Q_PAD_GPIO_5__KPP_ROW_7 \
2377 IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0)
2378 #define _MX6Q_PAD_GPIO_5__CCM_CLKO \
2379 IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0)
2380 #define _MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \
2381 IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0)
2382 #define _MX6Q_PAD_GPIO_5__GPIO_1_5 \
2383 IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0)
2384 #define _MX6Q_PAD_GPIO_5__I2C3_SCL \
2385 IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0)
2386 #define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \
2387 IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0)
2389 #define _MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \
2390 IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0)
2391 #define _MX6Q_PAD_GPIO_7__ECSPI5_RDY \
2392 IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0)
2393 #define _MX6Q_PAD_GPIO_7__EPIT1_EPITO \
2394 IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0)
2395 #define _MX6Q_PAD_GPIO_7__CAN1_TXCAN \
2396 IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0)
2397 #define _MX6Q_PAD_GPIO_7__UART2_TXD \
2398 IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0)
2399 #define _MX6Q_PAD_GPIO_7__UART2_RXD \
2400 IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0)
2401 #define _MX6Q_PAD_GPIO_7__GPIO_1_7 \
2402 IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0)
2403 #define _MX6Q_PAD_GPIO_7__SPDIF_PLOCK \
2404 IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0)
2405 #define _MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \
2406 IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0)
2408 #define _MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \
2409 IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0)
2410 #define _MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \
2411 IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0)
2412 #define _MX6Q_PAD_GPIO_8__EPIT2_EPITO \
2413 IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0)
2414 #define _MX6Q_PAD_GPIO_8__CAN1_RXCAN \
2415 IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0)
2416 #define _MX6Q_PAD_GPIO_8__UART2_TXD \
2417 IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0)
2418 #define _MX6Q_PAD_GPIO_8__UART2_RXD \
2419 IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0)
2420 #define _MX6Q_PAD_GPIO_8__GPIO_1_8 \
2421 IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0)
2422 #define _MX6Q_PAD_GPIO_8__SPDIF_SRCLK \
2423 IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0)
2424 #define _MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \
2425 IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0)
2427 #define _MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \
2428 IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0)
2429 #define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \
2430 IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0)
2431 #define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
2432 IOMUX_PAD(0x0618, 0x0248, 0x12, 0x083C, 1, 0)
2433 #define _MX6Q_PAD_GPIO_16__USDHC1_LCTL \
2434 IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0)
2435 #define _MX6Q_PAD_GPIO_16__SPDIF_IN1 \
2436 IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0)
2437 #define _MX6Q_PAD_GPIO_16__GPIO_7_11 \
2438 IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0)
2439 #define _MX6Q_PAD_GPIO_16__I2C3_SDA \
2440 IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0)
2441 #define _MX6Q_PAD_GPIO_16__SJC_DE_B \
2442 IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0)
2444 #define _MX6Q_PAD_GPIO_17__ESAI1_TX0 \
2445 IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0)
2446 #define _MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \
2447 IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0)
2448 #define _MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \
2449 IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0)
2450 #define _MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \
2451 IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0)
2452 #define _MX6Q_PAD_GPIO_17__SPDIF_OUT1 \
2453 IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0)
2454 #define _MX6Q_PAD_GPIO_17__GPIO_7_12 \
2455 IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0)
2456 #define _MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \
2457 IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0)
2459 #define _MX6Q_PAD_GPIO_18__ESAI1_TX1 \
2460 IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0)
2461 #define _MX6Q_PAD_GPIO_18__ENET_RX_CLK \
2462 IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0)
2463 #define _MX6Q_PAD_GPIO_18__USDHC3_VSELECT \
2464 IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0)
2465 #define _MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \
2466 IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0)
2467 #define _MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \
2468 IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0)
2469 #define _MX6Q_PAD_GPIO_18__GPIO_7_13 \
2470 IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0)
2471 #define _MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \
2472 IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0)
2473 #define _MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \
2474 IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0)
2476 #define _MX6Q_PAD_GPIO_19__KPP_COL_5 \
2477 IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0)
2478 #define _MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \
2479 IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0)
2480 #define _MX6Q_PAD_GPIO_19__SPDIF_OUT1 \
2481 IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0)
2482 #define _MX6Q_PAD_GPIO_19__CCM_CLKO \
2483 IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0)
2484 #define _MX6Q_PAD_GPIO_19__ECSPI1_RDY \
2485 IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0)
2486 #define _MX6Q_PAD_GPIO_19__GPIO_4_5 \
2487 IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0)
2488 #define _MX6Q_PAD_GPIO_19__ENET_TX_ER \
2489 IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0)
2490 #define _MX6Q_PAD_GPIO_19__SRC_INT_BOOT \
2491 IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0)
2493 #define _MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \
2494 IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0)
2495 #define _MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \
2496 IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0)
2497 #define _MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \
2498 IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0)
2499 #define _MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \
2500 IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0)
2501 #define _MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \
2502 IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0)
2503 #define _MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \
2504 IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0)
2506 #define _MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \
2507 IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0)
2508 #define _MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \
2509 IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0)
2510 #define _MX6Q_PAD_CSI0_MCLK__CCM_CLKO \
2511 IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0)
2512 #define _MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \
2513 IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0)
2514 #define _MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \
2515 IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0)
2516 #define _MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \
2517 IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0)
2518 #define _MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \
2519 IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0)
2521 #define _MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \
2522 IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0)
2523 #define _MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \
2524 IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0)
2525 #define _MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \
2526 IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0)
2527 #define _MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \
2528 IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0)
2529 #define _MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \
2530 IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0)
2531 #define _MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \
2532 IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0)
2533 #define _MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \
2534 IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0)
2536 #define _MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \
2537 IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0)
2538 #define _MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \
2539 IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0)
2540 #define _MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \
2541 IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0)
2542 #define _MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \
2543 IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0)
2544 #define _MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \
2545 IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0)
2546 #define _MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \
2547 IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0)
2548 #define _MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \
2549 IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0)
2551 #define _MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \
2552 IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0)
2553 #define _MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \
2554 IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0)
2555 #define _MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \
2556 IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0)
2557 #define _MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \
2558 IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0)
2559 #define _MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \
2560 IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0)
2561 #define _MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \
2562 IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0)
2563 #define _MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \
2564 IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0)
2565 #define _MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \
2566 IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0)
2568 #define _MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \
2569 IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0)
2570 #define _MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \
2571 IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0)
2572 #define _MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \
2573 IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0)
2574 #define _MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \
2575 IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0)
2576 #define _MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \
2577 IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0)
2578 #define _MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \
2579 IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0)
2580 #define _MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \
2581 IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0)
2582 #define _MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \
2583 IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0)
2585 #define _MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \
2586 IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0)
2587 #define _MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \
2588 IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0)
2589 #define _MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \
2590 IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0)
2591 #define _MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \
2592 IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0)
2593 #define _MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \
2594 IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0)
2595 #define _MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \
2596 IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0)
2597 #define _MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \
2598 IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0)
2599 #define _MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \
2600 IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0)
2602 #define _MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \
2603 IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0)
2604 #define _MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \
2605 IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0)
2606 #define _MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \
2607 IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0)
2608 #define _MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \
2609 IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0)
2610 #define _MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \
2611 IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0)
2612 #define _MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \
2613 IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0)
2614 #define _MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \
2615 IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0)
2616 #define _MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \
2617 IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0)
2619 #define _MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \
2620 IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0)
2621 #define _MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \
2622 IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0)
2623 #define _MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \
2624 IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0)
2625 #define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \
2626 IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0)
2627 #define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA \
2628 IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0)
2629 #define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \
2630 IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0)
2631 #define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \
2632 IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0)
2633 #define _MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \
2634 IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0)
2636 #define _MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \
2637 IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0)
2638 #define _MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \
2639 IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0)
2640 #define _MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \
2641 IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0)
2642 #define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \
2643 IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0)
2644 #define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL \
2645 IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0)
2646 #define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \
2647 IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0)
2648 #define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \
2649 IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0)
2650 #define _MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \
2651 IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0)
2653 #define _MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \
2654 IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0)
2655 #define _MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \
2656 IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0)
2657 #define _MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \
2658 IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0)
2659 #define _MX6Q_PAD_CSI0_DAT10__UART1_TXD \
2660 IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0)
2661 #define _MX6Q_PAD_CSI0_DAT10__UART1_RXD \
2662 IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0)
2663 #define _MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \
2664 IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0)
2665 #define _MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \
2666 IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0)
2667 #define _MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \
2668 IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0)
2669 #define _MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \
2670 IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0)
2672 #define _MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \
2673 IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0)
2674 #define _MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \
2675 IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0)
2676 #define _MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \
2677 IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0)
2678 #define _MX6Q_PAD_CSI0_DAT11__UART1_TXD \
2679 IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0)
2680 #define _MX6Q_PAD_CSI0_DAT11__UART1_RXD \
2681 IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0)
2682 #define _MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \
2683 IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0)
2684 #define _MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \
2685 IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0)
2686 #define _MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \
2687 IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0)
2688 #define _MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \
2689 IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0)
2691 #define _MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \
2692 IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0)
2693 #define _MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \
2694 IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0)
2695 #define _MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \
2696 IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0)
2697 #define _MX6Q_PAD_CSI0_DAT12__UART4_TXD \
2698 IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0)
2699 #define _MX6Q_PAD_CSI0_DAT12__UART4_RXD \
2700 IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0)
2701 #define _MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \
2702 IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0)
2703 #define _MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \
2704 IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0)
2705 #define _MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \
2706 IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0)
2707 #define _MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \
2708 IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0)
2710 #define _MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \
2711 IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0)
2712 #define _MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \
2713 IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0)
2714 #define _MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \
2715 IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0)
2716 #define _MX6Q_PAD_CSI0_DAT13__UART4_TXD \
2717 IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0)
2718 #define _MX6Q_PAD_CSI0_DAT13__UART4_RXD \
2719 IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0)
2720 #define _MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \
2721 IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0)
2722 #define _MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \
2723 IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0)
2724 #define _MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \
2725 IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0)
2726 #define _MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \
2727 IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0)
2729 #define _MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \
2730 IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0)
2731 #define _MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \
2732 IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0)
2733 #define _MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \
2734 IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0)
2735 #define _MX6Q_PAD_CSI0_DAT14__UART5_TXD \
2736 IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0)
2737 #define _MX6Q_PAD_CSI0_DAT14__UART5_RXD \
2738 IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0)
2739 #define _MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \
2740 IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0)
2741 #define _MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \
2742 IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0)
2743 #define _MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \
2744 IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0)
2745 #define _MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \
2746 IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0)
2748 #define _MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \
2749 IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0)
2750 #define _MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \
2751 IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0)
2752 #define _MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \
2753 IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0)
2754 #define _MX6Q_PAD_CSI0_DAT15__UART5_TXD \
2755 IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0)
2756 #define _MX6Q_PAD_CSI0_DAT15__UART5_RXD \
2757 IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0)
2758 #define _MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \
2759 IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0)
2760 #define _MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \
2761 IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0)
2762 #define _MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \
2763 IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0)
2764 #define _MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \
2765 IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0)
2767 #define _MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \
2768 IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0)
2769 #define _MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \
2770 IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0)
2771 #define _MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \
2772 IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0)
2773 #define _MX6Q_PAD_CSI0_DAT16__UART4_CTS \
2774 IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0)
2775 #define _MX6Q_PAD_CSI0_DAT16__UART4_RTS \
2776 IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0)
2777 #define _MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \
2778 IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0)
2779 #define _MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \
2780 IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0)
2781 #define _MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \
2782 IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0)
2783 #define _MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \
2784 IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0)
2786 #define _MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \
2787 IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0)
2788 #define _MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \
2789 IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0)
2790 #define _MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \
2791 IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0)
2792 #define _MX6Q_PAD_CSI0_DAT17__UART4_CTS \
2793 IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0)
2794 #define _MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \
2795 IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0)
2796 #define _MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \
2797 IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0)
2798 #define _MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \
2799 IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0)
2800 #define _MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \
2801 IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0)
2803 #define _MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \
2804 IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0)
2805 #define _MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \
2806 IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0)
2807 #define _MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \
2808 IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0)
2809 #define _MX6Q_PAD_CSI0_DAT18__UART5_CTS \
2810 IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0)
2811 #define _MX6Q_PAD_CSI0_DAT18__UART5_RTS \
2812 IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0)
2813 #define _MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \
2814 IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0)
2815 #define _MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \
2816 IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0)
2817 #define _MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \
2818 IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0)
2819 #define _MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \
2820 IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0)
2822 #define _MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \
2823 IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0)
2824 #define _MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \
2825 IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0)
2826 #define _MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \
2827 IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0)
2828 #define _MX6Q_PAD_CSI0_DAT19__UART5_CTS \
2829 IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0)
2830 #define _MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \
2831 IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0)
2832 #define _MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \
2833 IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0)
2834 #define _MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \
2835 IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0)
2836 #define _MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \
2837 IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0)
2839 #define _MX6Q_PAD_JTAG_TMS__SJC_TMS \
2840 IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0)
2842 #define _MX6Q_PAD_JTAG_MOD__SJC_MOD \
2843 IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0)
2845 #define _MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \
2846 IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0)
2848 #define _MX6Q_PAD_JTAG_TDI__SJC_TDI \
2849 IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0)
2851 #define _MX6Q_PAD_JTAG_TCK__SJC_TCK \
2852 IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0)
2854 #define _MX6Q_PAD_JTAG_TDO__SJC_TDO \
2855 IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0)
2857 #define _MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \
2858 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2860 #define _MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \
2861 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2863 #define _MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \
2864 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2866 #define _MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \
2867 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2869 #define _MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \
2870 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2872 #define _MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \
2873 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2875 #define _MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \
2876 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2878 #define _MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \
2879 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2881 #define _MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \
2882 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2884 #define _MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \
2885 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2887 #define _MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \
2888 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2890 #define _MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \
2891 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2893 #define _MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \
2894 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2896 #define _MX6Q_PAD_POR_B__SRC_POR_B \
2897 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2899 #define _MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \
2900 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2902 #define _MX6Q_PAD_RESET_IN_B__SRC_RESET_B \
2903 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2905 #define _MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \
2906 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2908 #define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \
2909 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2911 #define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 \
2912 IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0)
2913 #define _MX6Q_PAD_SD3_DAT7__UART1_TXD \
2914 IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0)
2915 #define _MX6Q_PAD_SD3_DAT7__UART1_RXD \
2916 IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0)
2917 #define _MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \
2918 IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0)
2919 #define _MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \
2920 IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0)
2921 #define _MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \
2922 IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0)
2923 #define _MX6Q_PAD_SD3_DAT7__GPIO_6_17 \
2924 IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
2925 #define _MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \
2926 IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0)
2927 #define _MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \
2928 IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0)
2930 #define _MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 \
2931 IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0)
2932 #define _MX6Q_PAD_SD3_DAT6__UART1_TXD \
2933 IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0)
2934 #define _MX6Q_PAD_SD3_DAT6__UART1_RXD \
2935 IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0)
2936 #define _MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \
2937 IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0)
2938 #define _MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \
2939 IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0)
2940 #define _MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \
2941 IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0)
2942 #define _MX6Q_PAD_SD3_DAT6__GPIO_6_18 \
2943 IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0)
2944 #define _MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \
2945 IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0)
2946 #define _MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \
2947 IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0)
2949 #define _MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 \
2950 IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0)
2951 #define _MX6Q_PAD_SD3_DAT5__UART2_TXD \
2952 IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0)
2953 #define _MX6Q_PAD_SD3_DAT5__UART2_RXD \
2954 IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0)
2955 #define _MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \
2956 IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0)
2957 #define _MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \
2958 IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0)
2959 #define _MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \
2960 IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0)
2961 #define _MX6Q_PAD_SD3_DAT5__GPIO_7_0 \
2962 IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0)
2963 #define _MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \
2964 IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0)
2965 #define _MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \
2966 IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0)
2968 #define _MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 \
2969 IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0)
2970 #define _MX6Q_PAD_SD3_DAT4__UART2_TXD \
2971 IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0)
2972 #define _MX6Q_PAD_SD3_DAT4__UART2_RXD \
2973 IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0)
2974 #define _MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \
2975 IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0)
2976 #define _MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \
2977 IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0)
2978 #define _MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \
2979 IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0)
2980 #define _MX6Q_PAD_SD3_DAT4__GPIO_7_1 \
2981 IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0)
2982 #define _MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \
2983 IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0)
2984 #define _MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \
2985 IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0)
2987 #define _MX6Q_PAD_SD3_CMD__USDHC3_CMD \
2988 IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
2989 #define _MX6Q_PAD_SD3_CMD__UART2_CTS \
2990 IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0)
2991 #define _MX6Q_PAD_SD3_CMD__CAN1_TXCAN \
2992 IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0)
2993 #define _MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \
2994 IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0)
2995 #define _MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \
2996 IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0)
2997 #define _MX6Q_PAD_SD3_CMD__GPIO_7_2 \
2998 IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0)
2999 #define _MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \
3000 IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0)
3001 #define _MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \
3002 IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0)
3004 #define _MX6Q_PAD_SD3_CLK__USDHC3_CLK \
3005 IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0)
3006 #define _MX6Q_PAD_SD3_CLK__UART2_CTS \
3007 IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0)
3008 #define _MX6Q_PAD_SD3_CLK__UART2_RTS \
3009 IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0)
3010 #define _MX6Q_PAD_SD3_CLK__CAN1_RXCAN \
3011 IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0)
3012 #define _MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \
3013 IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0)
3014 #define _MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \
3015 IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0)
3016 #define _MX6Q_PAD_SD3_CLK__GPIO_7_3 \
3017 IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0)
3018 #define _MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \
3019 IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0)
3020 #define _MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \
3021 IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0)
3023 #define _MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 \
3024 IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0)
3025 #define _MX6Q_PAD_SD3_DAT0__UART1_CTS \
3026 IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0)
3027 #define _MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \
3028 IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0)
3029 #define _MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
3030 IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0)
3031 #define _MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \
3032 IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0)
3033 #define _MX6Q_PAD_SD3_DAT0__GPIO_7_4 \
3034 IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0)
3035 #define _MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \
3036 IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0)
3037 #define _MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \
3038 IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0)
3040 #define _MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 \
3041 IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0)
3042 #define _MX6Q_PAD_SD3_DAT1__UART1_CTS \
3043 IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0)
3044 #define _MX6Q_PAD_SD3_DAT1__UART1_RTS \
3045 IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0)
3046 #define _MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \
3047 IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0)
3048 #define _MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \
3049 IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0)
3050 #define _MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \
3051 IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0)
3052 #define _MX6Q_PAD_SD3_DAT1__GPIO_7_5 \
3053 IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0)
3054 #define _MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \
3055 IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0)
3056 #define _MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \
3057 IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0)
3059 #define _MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 \
3060 IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0)
3061 #define _MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \
3062 IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0)
3063 #define _MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \
3064 IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0)
3065 #define _MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \
3066 IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0)
3067 #define _MX6Q_PAD_SD3_DAT2__GPIO_7_6 \
3068 IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0)
3069 #define _MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \
3070 IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0)
3071 #define _MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \
3072 IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0)
3074 #define _MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 \
3075 IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0)
3076 #define _MX6Q_PAD_SD3_DAT3__UART3_CTS \
3077 IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0)
3078 #define _MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \
3079 IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0)
3080 #define _MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \
3081 IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0)
3082 #define _MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \
3083 IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0)
3084 #define _MX6Q_PAD_SD3_DAT3__GPIO_7_7 \
3085 IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0)
3086 #define _MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \
3087 IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0)
3088 #define _MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \
3089 IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0)
3091 #define _MX6Q_PAD_SD3_RST__USDHC3_RST \
3092 IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0)
3093 #define _MX6Q_PAD_SD3_RST__UART3_CTS \
3094 IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0)
3095 #define _MX6Q_PAD_SD3_RST__UART3_RTS \
3096 IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0)
3097 #define _MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \
3098 IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0)
3099 #define _MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \
3100 IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0)
3101 #define _MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \
3102 IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0)
3103 #define _MX6Q_PAD_SD3_RST__GPIO_7_8 \
3104 IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0)
3105 #define _MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \
3106 IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0)
3107 #define _MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \
3108 IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0)
3110 #define _MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \
3111 IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0)
3112 #define _MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \
3113 IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0)
3114 #define _MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \
3115 IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0)
3116 #define _MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \
3117 IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0)
3118 #define _MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \
3119 IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0)
3120 #define _MX6Q_PAD_NANDF_CLE__GPIO_6_7 \
3121 IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0)
3122 #define _MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \
3123 IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0)
3124 #define _MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \
3125 IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0)
3127 #define _MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \
3128 IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0)
3129 #define _MX6Q_PAD_NANDF_ALE__USDHC4_RST \
3130 IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0)
3131 #define _MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \
3132 IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0)
3133 #define _MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \
3134 IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0)
3135 #define _MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \
3136 IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0)
3137 #define _MX6Q_PAD_NANDF_ALE__GPIO_6_8 \
3138 IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0)
3139 #define _MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \
3140 IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0)
3141 #define _MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \
3142 IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0)
3144 #define _MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \
3145 IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0)
3146 #define _MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \
3147 IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0)
3148 #define _MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \
3149 IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0)
3150 #define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \
3151 IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0)
3152 #define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \
3153 IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0)
3154 #define _MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \
3155 IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0)
3156 #define _MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \
3157 IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0)
3158 #define _MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \
3159 IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0)
3161 #define _MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \
3162 IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0)
3163 #define _MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \
3164 IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0)
3165 #define _MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \
3166 IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0)
3167 #define _MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \
3168 IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0)
3169 #define _MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \
3170 IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0)
3171 #define _MX6Q_PAD_NANDF_RB0__GPIO_6_10 \
3172 IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0)
3173 #define _MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \
3174 IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0)
3175 #define _MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \
3176 IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0)
3178 #define _MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \
3179 IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0)
3180 #define _MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \
3181 IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0)
3182 #define _MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \
3183 IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0)
3184 #define _MX6Q_PAD_NANDF_CS0__GPIO_6_11 \
3185 IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0)
3186 #define _MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \
3187 IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0)
3189 #define _MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \
3190 IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0)
3191 #define _MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \
3192 IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0)
3193 #define _MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \
3194 IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0)
3195 #define _MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \
3196 IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0)
3197 #define _MX6Q_PAD_NANDF_CS1__GPIO_6_14 \
3198 IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0)
3199 #define _MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \
3200 IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0)
3202 #define _MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \
3203 IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0)
3204 #define _MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \
3205 IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0)
3206 #define _MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \
3207 IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0)
3208 #define _MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \
3209 IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0)
3210 #define _MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \
3211 IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0)
3212 #define _MX6Q_PAD_NANDF_CS2__GPIO_6_15 \
3213 IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0)
3214 #define _MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \
3215 IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0)
3217 #define _MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \
3218 IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0)
3219 #define _MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \
3220 IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0)
3221 #define _MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \
3222 IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0)
3223 #define _MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \
3224 IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0)
3225 #define _MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \
3226 IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0)
3227 #define _MX6Q_PAD_NANDF_CS3__GPIO_6_16 \
3228 IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0)
3229 #define _MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \
3230 IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0)
3231 #define _MX6Q_PAD_NANDF_CS3__TPSMP_CLK \
3232 IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0)
3234 #define _MX6Q_PAD_SD4_CMD__USDHC4_CMD \
3235 IOMUX_PAD(0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
3236 #define _MX6Q_PAD_SD4_CMD__RAWNAND_RDN \
3237 IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0)
3238 #define _MX6Q_PAD_SD4_CMD__UART3_TXD \
3239 IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0)
3240 #define _MX6Q_PAD_SD4_CMD__UART3_RXD \
3241 IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0)
3242 #define _MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \
3243 IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0)
3244 #define _MX6Q_PAD_SD4_CMD__GPIO_7_9 \
3245 IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0)
3246 #define _MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \
3247 IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0)
3249 #define _MX6Q_PAD_SD4_CLK__USDHC4_CLK \
3250 IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0)
3251 #define _MX6Q_PAD_SD4_CLK__RAWNAND_WRN \
3252 IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0)
3253 #define _MX6Q_PAD_SD4_CLK__UART3_TXD \
3254 IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0)
3255 #define _MX6Q_PAD_SD4_CLK__UART3_RXD \
3256 IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0)
3257 #define _MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \
3258 IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0)
3259 #define _MX6Q_PAD_SD4_CLK__GPIO_7_10 \
3260 IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0)
3262 #define _MX6Q_PAD_NANDF_D0__RAWNAND_D0 \
3263 IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0)
3264 #define _MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \
3265 IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0)
3266 #define _MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \
3267 IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0)
3268 #define _MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \
3269 IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0)
3270 #define _MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \
3271 IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0)
3272 #define _MX6Q_PAD_NANDF_D0__GPIO_2_0 \
3273 IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0)
3274 #define _MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \
3275 IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0)
3276 #define _MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \
3277 IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0)
3279 #define _MX6Q_PAD_NANDF_D1__RAWNAND_D1 \
3280 IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0)
3281 #define _MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \
3282 IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0)
3283 #define _MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \
3284 IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0)
3285 #define _MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \
3286 IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0)
3287 #define _MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \
3288 IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0)
3289 #define _MX6Q_PAD_NANDF_D1__GPIO_2_1 \
3290 IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0)
3291 #define _MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \
3292 IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0)
3293 #define _MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \
3294 IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0)
3296 #define _MX6Q_PAD_NANDF_D2__RAWNAND_D2 \
3297 IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0)
3298 #define _MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \
3299 IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0)
3300 #define _MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \
3301 IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0)
3302 #define _MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \
3303 IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0)
3304 #define _MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \
3305 IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0)
3306 #define _MX6Q_PAD_NANDF_D2__GPIO_2_2 \
3307 IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0)
3308 #define _MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \
3309 IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0)
3310 #define _MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \
3311 IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0)
3313 #define _MX6Q_PAD_NANDF_D3__RAWNAND_D3 \
3314 IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0)
3315 #define _MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \
3316 IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0)
3317 #define _MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \
3318 IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0)
3319 #define _MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \
3320 IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0)
3321 #define _MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \
3322 IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0)
3323 #define _MX6Q_PAD_NANDF_D3__GPIO_2_3 \
3324 IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0)
3325 #define _MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \
3326 IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0)
3327 #define _MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \
3328 IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0)
3330 #define _MX6Q_PAD_NANDF_D4__RAWNAND_D4 \
3331 IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0)
3332 #define _MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \
3333 IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0)
3334 #define _MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \
3335 IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0)
3336 #define _MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \
3337 IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0)
3338 #define _MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \
3339 IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0)
3340 #define _MX6Q_PAD_NANDF_D4__GPIO_2_4 \
3341 IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0)
3342 #define _MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \
3343 IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0)
3344 #define _MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \
3345 IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0)
3347 #define _MX6Q_PAD_NANDF_D5__RAWNAND_D5 \
3348 IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0)
3349 #define _MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \
3350 IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0)
3351 #define _MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \
3352 IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0)
3353 #define _MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \
3354 IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0)
3355 #define _MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \
3356 IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0)
3357 #define _MX6Q_PAD_NANDF_D5__GPIO_2_5 \
3358 IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0)
3359 #define _MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \
3360 IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0)
3361 #define _MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \
3362 IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0)
3364 #define _MX6Q_PAD_NANDF_D6__RAWNAND_D6 \
3365 IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0)
3366 #define _MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \
3367 IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0)
3368 #define _MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \
3369 IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0)
3370 #define _MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \
3371 IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0)
3372 #define _MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \
3373 IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0)
3374 #define _MX6Q_PAD_NANDF_D6__GPIO_2_6 \
3375 IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0)
3376 #define _MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \
3377 IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0)
3378 #define _MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \
3379 IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0)
3381 #define _MX6Q_PAD_NANDF_D7__RAWNAND_D7 \
3382 IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0)
3383 #define _MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \
3384 IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0)
3385 #define _MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \
3386 IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0)
3387 #define _MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \
3388 IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0)
3389 #define _MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \
3390 IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0)
3391 #define _MX6Q_PAD_NANDF_D7__GPIO_2_7 \
3392 IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0)
3393 #define _MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \
3394 IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0)
3395 #define _MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \
3396 IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0)
3398 #define _MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \
3399 IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0)
3400 #define _MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 \
3401 IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0)
3402 #define _MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \
3403 IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0)
3404 #define _MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \
3405 IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0)
3406 #define _MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \
3407 IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0)
3408 #define _MX6Q_PAD_SD4_DAT0__GPIO_2_8 \
3409 IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0)
3410 #define _MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \
3411 IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0)
3412 #define _MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \
3413 IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0)
3415 #define _MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \
3416 IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0)
3417 #define _MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 \
3418 IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0)
3419 #define _MX6Q_PAD_SD4_DAT1__PWM3_PWMO \
3420 IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0)
3421 #define _MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \
3422 IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0)
3423 #define _MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \
3424 IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0)
3425 #define _MX6Q_PAD_SD4_DAT1__GPIO_2_9 \
3426 IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0)
3427 #define _MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \
3428 IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0)
3429 #define _MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \
3430 IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0)
3432 #define _MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \
3433 IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0)
3434 #define _MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 \
3435 IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0)
3436 #define _MX6Q_PAD_SD4_DAT2__PWM4_PWMO \
3437 IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0)
3438 #define _MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \
3439 IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0)
3440 #define _MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \
3441 IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0)
3442 #define _MX6Q_PAD_SD4_DAT2__GPIO_2_10 \
3443 IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0)
3444 #define _MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \
3445 IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0)
3446 #define _MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \
3447 IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0)
3449 #define _MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \
3450 IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0)
3451 #define _MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 \
3452 IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0)
3453 #define _MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \
3454 IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0)
3455 #define _MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \
3456 IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0)
3457 #define _MX6Q_PAD_SD4_DAT3__GPIO_2_11 \
3458 IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0)
3459 #define _MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \
3460 IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0)
3461 #define _MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \
3462 IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0)
3464 #define _MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \
3465 IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0)
3466 #define _MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 \
3467 IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0)
3468 #define _MX6Q_PAD_SD4_DAT4__UART2_TXD \
3469 IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0)
3470 #define _MX6Q_PAD_SD4_DAT4__UART2_RXD \
3471 IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0)
3472 #define _MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \
3473 IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0)
3474 #define _MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \
3475 IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0)
3476 #define _MX6Q_PAD_SD4_DAT4__GPIO_2_12 \
3477 IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0)
3478 #define _MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \
3479 IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0)
3480 #define _MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \
3481 IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0)
3483 #define _MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \
3484 IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0)
3485 #define _MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 \
3486 IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0)
3487 #define _MX6Q_PAD_SD4_DAT5__UART2_CTS \
3488 IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0)
3489 #define _MX6Q_PAD_SD4_DAT5__UART2_RTS \
3490 IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0)
3491 #define _MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \
3492 IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0)
3493 #define _MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \
3494 IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0)
3495 #define _MX6Q_PAD_SD4_DAT5__GPIO_2_13 \
3496 IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0)
3497 #define _MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \
3498 IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0)
3499 #define _MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \
3500 IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0)
3502 #define _MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \
3503 IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0)
3504 #define _MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 \
3505 IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0)
3506 #define _MX6Q_PAD_SD4_DAT6__UART2_CTS \
3507 IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0)
3508 #define _MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \
3509 IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0)
3510 #define _MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \
3511 IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0)
3512 #define _MX6Q_PAD_SD4_DAT6__GPIO_2_14 \
3513 IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0)
3514 #define _MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \
3515 IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0)
3516 #define _MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \
3517 IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0)
3519 #define _MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \
3520 IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0)
3521 #define _MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 \
3522 IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0)
3523 #define _MX6Q_PAD_SD4_DAT7__UART2_TXD \
3524 IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0)
3525 #define _MX6Q_PAD_SD4_DAT7__UART2_RXD \
3526 IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0)
3527 #define _MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \
3528 IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0)
3529 #define _MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \
3530 IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0)
3531 #define _MX6Q_PAD_SD4_DAT7__GPIO_2_15 \
3532 IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0)
3533 #define _MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \
3534 IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0)
3535 #define _MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \
3536 IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0)
3538 #define _MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \
3539 IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0)
3540 #define _MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \
3541 IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0)
3542 #define _MX6Q_PAD_SD1_DAT1__PWM3_PWMO \
3543 IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0)
3544 #define _MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \
3545 IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0)
3546 #define _MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \
3547 IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0)
3548 #define _MX6Q_PAD_SD1_DAT1__GPIO_1_17 \
3549 IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0)
3550 #define _MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \
3551 IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0)
3552 #define _MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \
3553 IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0)
3555 #define _MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \
3556 IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0)
3557 #define _MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \
3558 IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0)
3559 #define _MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \
3560 IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0)
3561 #define _MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \
3562 IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0)
3563 #define _MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \
3564 IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0)
3565 #define _MX6Q_PAD_SD1_DAT0__GPIO_1_16 \
3566 IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0)
3567 #define _MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \
3568 IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0)
3569 #define _MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \
3570 IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0)
3572 #define _MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \
3573 IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0)
3574 #define _MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \
3575 IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0)
3576 #define _MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \
3577 IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0)
3578 #define _MX6Q_PAD_SD1_DAT3__PWM1_PWMO \
3579 IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0)
3580 #define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \
3581 IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0)
3582 #define _MX6Q_PAD_SD1_DAT3__GPIO_1_21 \
3583 IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0)
3584 #define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \
3585 IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0)
3586 #define _MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \
3587 IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0)
3589 #define _MX6Q_PAD_SD1_CMD__USDHC1_CMD \
3590 IOMUX_PAD(0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
3591 #define _MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \
3592 IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0)
3593 #define _MX6Q_PAD_SD1_CMD__PWM4_PWMO \
3594 IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0)
3595 #define _MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \
3596 IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0)
3597 #define _MX6Q_PAD_SD1_CMD__GPIO_1_18 \
3598 IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0)
3599 #define _MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \
3600 IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0)
3602 #define _MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \
3603 IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0)
3604 #define _MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \
3605 IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0)
3606 #define _MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \
3607 IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0)
3608 #define _MX6Q_PAD_SD1_DAT2__PWM2_PWMO \
3609 IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0)
3610 #define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \
3611 IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0)
3612 #define _MX6Q_PAD_SD1_DAT2__GPIO_1_19 \
3613 IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0)
3614 #define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \
3615 IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0)
3616 #define _MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \
3617 IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0)
3619 #define _MX6Q_PAD_SD1_CLK__USDHC1_CLK \
3620 IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0)
3621 #define _MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \
3622 IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0)
3623 #define _MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \
3624 IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0)
3625 #define _MX6Q_PAD_SD1_CLK__GPT_CLKIN \
3626 IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0)
3627 #define _MX6Q_PAD_SD1_CLK__GPIO_1_20 \
3628 IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0)
3629 #define _MX6Q_PAD_SD1_CLK__PHY_DTB_0 \
3630 IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0)
3631 #define _MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \
3632 IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0)
3634 #define _MX6Q_PAD_SD2_CLK__USDHC2_CLK \
3635 IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0)
3636 #define _MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \
3637 IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0)
3638 #define _MX6Q_PAD_SD2_CLK__KPP_COL_5 \
3639 IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0)
3640 #define _MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \
3641 IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0)
3642 #define _MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \
3643 IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0)
3644 #define _MX6Q_PAD_SD2_CLK__GPIO_1_10 \
3645 IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0)
3646 #define _MX6Q_PAD_SD2_CLK__PHY_DTB_1 \
3647 IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0)
3648 #define _MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \
3649 IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0)
3651 #define _MX6Q_PAD_SD2_CMD__USDHC2_CMD \
3652 IOMUX_PAD(0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
3653 #define _MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \
3654 IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0)
3655 #define _MX6Q_PAD_SD2_CMD__KPP_ROW_5 \
3656 IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0)
3657 #define _MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \
3658 IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0)
3659 #define _MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \
3660 IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0)
3661 #define _MX6Q_PAD_SD2_CMD__GPIO_1_11 \
3662 IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0)
3664 #define _MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \
3665 IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0)
3666 #define _MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \
3667 IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0)
3668 #define _MX6Q_PAD_SD2_DAT3__KPP_COL_6 \
3669 IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0)
3670 #define _MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \
3671 IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0)
3672 #define _MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \
3673 IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0)
3674 #define _MX6Q_PAD_SD2_DAT3__GPIO_1_12 \
3675 IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0)
3676 #define _MX6Q_PAD_SD2_DAT3__SJC_DONE \
3677 IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0)
3678 #define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \
3679 IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0)
3683 #define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
3684 (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
3685 #define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
3686 (_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3687 #define MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \
3688 (_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3689 #define MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \
3690 (_MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
3691 #define MX6Q_PAD_SD2_DAT1__KPP_COL_7 \
3692 (_MX6Q_PAD_SD2_DAT1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
3693 #define MX6Q_PAD_SD2_DAT1__GPIO_1_14 \
3694 (_MX6Q_PAD_SD2_DAT1__GPIO_1_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
3695 #define MX6Q_PAD_SD2_DAT1__CCM_WAIT \
3696 (_MX6Q_PAD_SD2_DAT1__CCM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
3697 #define MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \
3698 (_MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3700 #define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \
3701 (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
3702 #define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \
3703 (_MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3704 #define MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \
3705 (_MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
3706 #define MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \
3707 (_MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
3708 #define MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \
3709 (_MX6Q_PAD_SD2_DAT2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
3710 #define MX6Q_PAD_SD2_DAT2__GPIO_1_13 \
3711 (_MX6Q_PAD_SD2_DAT2__GPIO_1_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
3712 #define MX6Q_PAD_SD2_DAT2__CCM_STOP \
3713 (_MX6Q_PAD_SD2_DAT2__CCM_STOP | MUX_PAD_CTRL(NO_PAD_CTRL))
3714 #define MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \
3715 (_MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3717 #define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \
3718 (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
3719 #define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \
3720 (_MX6Q_PAD_SD2_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
3721 #define MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
3722 (_MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
3723 #define MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \
3724 (_MX6Q_PAD_SD2_DAT0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
3725 #define MX6Q_PAD_SD2_DAT0__GPIO_1_15 \
3726 (_MX6Q_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
3727 #define MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \
3728 (_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
3729 #define MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \
3730 (_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3733 #define MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \
3734 (_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
3735 #define MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \
3736 (_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3737 #define MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \
3738 (_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
3739 #define MX6Q_PAD_RGMII_TXC__GPIO_6_19 \
3740 (_MX6Q_PAD_RGMII_TXC__GPIO_6_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
3741 #define MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \
3742 (_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3743 #define MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \
3744 (_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
3747 #define MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \
3748 (_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
3749 #define MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \
3750 (_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3751 #define MX6Q_PAD_RGMII_TD0__GPIO_6_20 \
3752 (_MX6Q_PAD_RGMII_TD0__GPIO_6_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
3753 #define MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \
3754 (_MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3756 #define MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \
3757 (_MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
3758 #define MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \
3759 (_MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3760 #define MX6Q_PAD_RGMII_TD1__GPIO_6_21 \
3761 (_MX6Q_PAD_RGMII_TD1__GPIO_6_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
3762 #define MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \
3763 (_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3764 #define MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \
3765 (_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
3768 #define MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \
3769 (_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
3770 #define MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \
3771 (_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3772 #define MX6Q_PAD_RGMII_TD2__GPIO_6_22 \
3773 (_MX6Q_PAD_RGMII_TD2__GPIO_6_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
3774 #define MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \
3775 (_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
3776 #define MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \
3777 (_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
3780 #define MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \
3781 (_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
3782 #define MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \
3783 (_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3784 #define MX6Q_PAD_RGMII_TD3__GPIO_6_23 \
3785 (_MX6Q_PAD_RGMII_TD3__GPIO_6_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
3786 #define MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \
3787 (_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
3790 #define MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \
3791 (_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
3792 #define MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \
3793 (_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3794 #define MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \
3795 (_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
3796 #define MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \
3797 (_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
3800 #define MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \
3801 (_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
3802 #define MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \
3803 (_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3804 #define MX6Q_PAD_RGMII_RD0__GPIO_6_25 \
3805 (_MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
3806 #define MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \
3807 (_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
3810 #define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \
3811 (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
3812 #define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START \
3813 (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | \
3814 MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP)\
3816 #define MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \
3817 (_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3818 #define MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \
3819 (_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
3820 #define MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \
3821 (_MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
3822 #define MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \
3823 (_MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
3825 #define MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \
3826 (_MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
3827 #define MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \
3828 (_MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3829 #define MX6Q_PAD_RGMII_RD1__GPIO_6_27 \
3830 (_MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
3831 #define MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \
3832 (_MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
3833 #define MX6Q_PAD_RGMII_RD1__SJC_FAIL \
3834 (_MX6Q_PAD_RGMII_RD1__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL))
3836 #define MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \
3837 (_MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
3838 #define MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \
3839 (_MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3840 #define MX6Q_PAD_RGMII_RD2__GPIO_6_28 \
3841 (_MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
3842 #define MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \
3843 (_MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
3845 #define MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \
3846 (_MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
3847 #define MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \
3848 (_MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3849 #define MX6Q_PAD_RGMII_RD3__GPIO_6_29 \
3850 (_MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
3851 #define MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \
3852 (_MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
3854 #define MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \
3855 (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
3856 #define MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE_START \
3857 (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP))
3858 #define MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \
3859 (_MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3860 #define MX6Q_PAD_RGMII_RXC__GPIO_6_30 \
3861 (_MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
3862 #define MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \
3863 (_MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
3865 #define MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \
3866 (_MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
3867 #define MX6Q_PAD_EIM_A25__ECSPI4_SS1 \
3868 (_MX6Q_PAD_EIM_A25__ECSPI4_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3869 #define MX6Q_PAD_EIM_A25__ECSPI2_RDY \
3870 (_MX6Q_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
3871 #define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \
3872 (_MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
3873 #define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \
3874 (_MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
3875 #define MX6Q_PAD_EIM_A25__GPIO_5_2 \
3876 (_MX6Q_PAD_EIM_A25__GPIO_5_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3877 #define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \
3878 (_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
3879 #define MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \
3880 (_MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3882 #define MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \
3883 (_MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3884 #define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \
3885 (_MX6Q_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
3886 #define MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \
3887 (_MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
3888 #define MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \
3889 (_MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
3890 #define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \
3891 (_MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
3892 #define MX6Q_PAD_EIM_EB2__GPIO_2_30 \
3893 (_MX6Q_PAD_EIM_EB2__GPIO_2_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
3894 #define MX6Q_PAD_EIM_EB2__I2C2_SCL \
3895 (_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
3896 #define MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \
3897 (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
3899 #define MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \
3900 (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
3901 #define MX6Q_PAD_EIM_D16__ECSPI1_SCLK \
3902 (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
3903 #define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \
3904 (_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
3905 #define MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \
3906 (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
3907 #define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \
3908 (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
3909 #define MX6Q_PAD_EIM_D16__GPIO_3_16 \
3910 (_MX6Q_PAD_EIM_D16__GPIO_3_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
3911 #define MX6Q_PAD_EIM_D16__I2C2_SDA \
3912 (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
3914 #define MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \
3915 (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
3916 #define MX6Q_PAD_EIM_D17__ECSPI1_MISO \
3917 (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
3918 #define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \
3919 (_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
3920 #define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \
3921 (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
3922 #define MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \
3923 (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
3924 #define MX6Q_PAD_EIM_D17__GPIO_3_17 \
3925 (_MX6Q_PAD_EIM_D17__GPIO_3_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
3926 #define MX6Q_PAD_EIM_D17__I2C3_SCL \
3927 (_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
3928 #define MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \
3929 (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3931 #define MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \
3932 (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
3933 #define MX6Q_PAD_EIM_D18__ECSPI1_MOSI \
3934 (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
3935 #define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \
3936 (_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
3937 #define MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \
3938 (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
3939 #define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \
3940 (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
3941 #define MX6Q_PAD_EIM_D18__GPIO_3_18 \
3942 (_MX6Q_PAD_EIM_D18__GPIO_3_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
3943 #define MX6Q_PAD_EIM_D18__I2C3_SDA \
3944 (_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
3945 #define MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \
3946 (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3948 #define MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \
3949 (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
3950 #define MX6Q_PAD_EIM_D19__ECSPI1_SS1 \
3951 (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
3952 #define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \
3953 (_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
3954 #define MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \
3955 (_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
3956 #define MX6Q_PAD_EIM_D19__UART1_CTS \
3957 (_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3958 #define MX6Q_PAD_EIM_D19__GPIO_3_19 \
3959 (_MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
3960 #define MX6Q_PAD_EIM_D19__EPIT1_EPITO \
3961 (_MX6Q_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
3962 #define MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \
3963 (_MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP | MUX_PAD_CTRL(NO_PAD_CTRL))
3965 #define MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \
3966 (_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
3967 #define MX6Q_PAD_EIM_D20__ECSPI4_SS0 \
3968 (_MX6Q_PAD_EIM_D20__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3969 #define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \
3970 (_MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
3971 #define MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \
3972 (_MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
3973 #define MX6Q_PAD_EIM_D20__UART1_CTS \
3974 (_MX6Q_PAD_EIM_D20__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3975 #define MX6Q_PAD_EIM_D20__UART1_RTS \
3976 (_MX6Q_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3977 #define MX6Q_PAD_EIM_D20__GPIO_3_20 \
3978 (_MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
3979 #define MX6Q_PAD_EIM_D20__EPIT2_EPITO \
3980 (_MX6Q_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
3982 #define MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \
3983 (_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
3984 #define MX6Q_PAD_EIM_D21__ECSPI4_SCLK \
3985 (_MX6Q_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
3986 #define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \
3987 (_MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
3988 #define MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \
3989 (_MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
3990 #define MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \
3991 (_MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
3992 #define MX6Q_PAD_EIM_D21__GPIO_3_21 \
3993 (_MX6Q_PAD_EIM_D21__GPIO_3_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
3994 #define MX6Q_PAD_EIM_D21__I2C1_SCL \
3995 (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
3996 #define MX6Q_PAD_EIM_D21__SPDIF_IN1 \
3997 (_MX6Q_PAD_EIM_D21__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3999 #define MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \
4000 (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4001 #define MX6Q_PAD_EIM_D22__ECSPI4_MISO \
4002 (_MX6Q_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
4003 #define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \
4004 (_MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4005 #define MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \
4006 (_MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4007 #define MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \
4008 (_MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
4009 #define MX6Q_PAD_EIM_D22__GPIO_3_22 \
4010 (_MX6Q_PAD_EIM_D22__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4011 #define MX6Q_PAD_EIM_D22__SPDIF_OUT1 \
4012 (_MX6Q_PAD_EIM_D22__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4013 #define MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \
4014 (_MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
4016 #define MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \
4017 (_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4018 #define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \
4019 (_MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
4020 #define MX6Q_PAD_EIM_D23__UART3_CTS \
4021 (_MX6Q_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4022 #define MX6Q_PAD_EIM_D23__UART1_DCD \
4023 (_MX6Q_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4024 #define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \
4025 (_MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
4026 #define MX6Q_PAD_EIM_D23__GPIO_3_23 \
4027 (_MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4028 #define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \
4029 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4030 #define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \
4031 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4033 #define MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \
4034 (_MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4035 #define MX6Q_PAD_EIM_EB3__ECSPI4_RDY \
4036 (_MX6Q_PAD_EIM_EB3__ECSPI4_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
4037 #define MX6Q_PAD_EIM_EB3__UART3_CTS \
4038 (_MX6Q_PAD_EIM_EB3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4039 #define MX6Q_PAD_EIM_EB3__UART3_RTS \
4040 (_MX6Q_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4041 #define MX6Q_PAD_EIM_EB3__UART1_RI \
4042 (_MX6Q_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4043 #define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \
4044 (_MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
4045 #define MX6Q_PAD_EIM_EB3__GPIO_2_31 \
4046 (_MX6Q_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4047 #define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \
4048 (_MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4049 #define MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \
4050 (_MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4052 #define MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \
4053 (_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4054 #define MX6Q_PAD_EIM_D24__ECSPI4_SS2 \
4055 (_MX6Q_PAD_EIM_D24__ECSPI4_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4056 #define MX6Q_PAD_EIM_D24__UART3_TXD \
4057 (_MX6Q_PAD_EIM_D24__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4058 #define MX6Q_PAD_EIM_D24__UART3_RXD \
4059 (_MX6Q_PAD_EIM_D24__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4060 #define MX6Q_PAD_EIM_D24__ECSPI1_SS2 \
4061 (_MX6Q_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4062 #define MX6Q_PAD_EIM_D24__ECSPI2_SS2 \
4063 (_MX6Q_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4064 #define MX6Q_PAD_EIM_D24__GPIO_3_24 \
4065 (_MX6Q_PAD_EIM_D24__GPIO_3_24 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
4066 #define MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \
4067 (_MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
4068 #define MX6Q_PAD_EIM_D24__UART1_DTR \
4069 (_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4071 #define MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \
4072 (_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4073 #define MX6Q_PAD_EIM_D25__ECSPI4_SS3 \
4074 (_MX6Q_PAD_EIM_D25__ECSPI4_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4075 #define MX6Q_PAD_EIM_D25__UART3_TXD \
4076 (_MX6Q_PAD_EIM_D25__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4077 #define MX6Q_PAD_EIM_D25__UART3_RXD \
4078 (_MX6Q_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4079 #define MX6Q_PAD_EIM_D25__ECSPI1_SS3 \
4080 (_MX6Q_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4081 #define MX6Q_PAD_EIM_D25__ECSPI2_SS3 \
4082 (_MX6Q_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4083 #define MX6Q_PAD_EIM_D25__GPIO_3_25 \
4084 (_MX6Q_PAD_EIM_D25__GPIO_3_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4085 #define MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \
4086 (_MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
4087 #define MX6Q_PAD_EIM_D25__UART1_DSR \
4088 (_MX6Q_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4090 #define MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \
4091 (_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4092 #define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \
4093 (_MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4094 #define MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \
4095 (_MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4096 #define MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \
4097 (_MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4098 #define MX6Q_PAD_EIM_D26__UART2_TXD \
4099 (_MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4100 #define MX6Q_PAD_EIM_D26__UART2_RXD \
4101 (_MX6Q_PAD_EIM_D26__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4102 #define MX6Q_PAD_EIM_D26__GPIO_3_26 \
4103 (_MX6Q_PAD_EIM_D26__GPIO_3_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4104 #define MX6Q_PAD_EIM_D26__IPU1_SISG_2 \
4105 (_MX6Q_PAD_EIM_D26__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4106 #define MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \
4107 (_MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4109 #define MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \
4110 (_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4111 #define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \
4112 (_MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4113 #define MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \
4114 (_MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4115 #define MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \
4116 (_MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4117 #define MX6Q_PAD_EIM_D27__UART2_TXD \
4118 (_MX6Q_PAD_EIM_D27__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4119 #define MX6Q_PAD_EIM_D27__UART2_RXD \
4120 (_MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4121 #define MX6Q_PAD_EIM_D27__GPIO_3_27 \
4122 (_MX6Q_PAD_EIM_D27__GPIO_3_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4123 #define MX6Q_PAD_EIM_D27__IPU1_SISG_3 \
4124 (_MX6Q_PAD_EIM_D27__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4125 #define MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \
4126 (_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4128 #define MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \
4129 (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4130 #define MX6Q_PAD_EIM_D28__I2C1_SDA \
4131 (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
4132 #define MX6Q_PAD_EIM_D28__ECSPI4_MOSI \
4133 (_MX6Q_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
4134 #define MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \
4135 (_MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4136 #define MX6Q_PAD_EIM_D28__UART2_CTS \
4137 (_MX6Q_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4138 #define MX6Q_PAD_EIM_D28__UART2_RTS \
4139 (_MX6Q_PAD_EIM_D28__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4140 #define MX6Q_PAD_EIM_D28__GPIO_3_28 \
4141 (_MX6Q_PAD_EIM_D28__GPIO_3_28 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
4142 #define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \
4143 (_MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
4144 #define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \
4145 (_MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4147 #define MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \
4148 (_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4149 #define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \
4150 (_MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4151 #define MX6Q_PAD_EIM_D29__ECSPI4_SS0 \
4152 (_MX6Q_PAD_EIM_D29__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4153 #define MX6Q_PAD_EIM_D29__UART2_CTS \
4154 (_MX6Q_PAD_EIM_D29__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4155 #define MX6Q_PAD_EIM_D29__UART2_RTS \
4156 (_MX6Q_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4157 #define MX6Q_PAD_EIM_D29__GPIO_3_29 \
4158 (_MX6Q_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4159 #define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \
4160 (_MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
4161 #define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \
4162 (_MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4164 #define MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \
4165 (_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
4166 #define MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
4167 (_MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4168 #define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \
4169 (_MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4170 #define MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \
4171 (_MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4172 #define MX6Q_PAD_EIM_D30__UART3_CTS \
4173 (_MX6Q_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4174 #define MX6Q_PAD_EIM_D30__GPIO_3_30 \
4175 (_MX6Q_PAD_EIM_D30__GPIO_3_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
4176 #define MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \
4177 (_MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
4178 #define MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \
4179 (_MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4181 #define MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \
4182 (_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4183 #define MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
4184 (_MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4185 #define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \
4186 (_MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4187 #define MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \
4188 (_MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4189 #define MX6Q_PAD_EIM_D31__UART3_CTS \
4190 (_MX6Q_PAD_EIM_D31__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4191 #define MX6Q_PAD_EIM_D31__UART3_RTS \
4192 (_MX6Q_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4193 #define MX6Q_PAD_EIM_D31__GPIO_3_31 \
4194 (_MX6Q_PAD_EIM_D31__GPIO_3_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4195 #define MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \
4196 (_MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
4197 #define MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \
4198 (_MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4200 #define MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \
4201 (_MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4202 #define MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \
4203 (_MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4204 #define MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \
4205 (_MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4206 #define MX6Q_PAD_EIM_A24__IPU2_SISG_2 \
4207 (_MX6Q_PAD_EIM_A24__IPU2_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4208 #define MX6Q_PAD_EIM_A24__IPU1_SISG_2 \
4209 (_MX6Q_PAD_EIM_A24__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4210 #define MX6Q_PAD_EIM_A24__GPIO_5_4 \
4211 (_MX6Q_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4212 #define MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \
4213 (_MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4214 #define MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \
4215 (_MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4217 #define MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \
4218 (_MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4219 #define MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \
4220 (_MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4221 #define MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \
4222 (_MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4223 #define MX6Q_PAD_EIM_A23__IPU2_SISG_3 \
4224 (_MX6Q_PAD_EIM_A23__IPU2_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4225 #define MX6Q_PAD_EIM_A23__IPU1_SISG_3 \
4226 (_MX6Q_PAD_EIM_A23__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4227 #define MX6Q_PAD_EIM_A23__GPIO_6_6 \
4228 (_MX6Q_PAD_EIM_A23__GPIO_6_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4229 #define MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \
4230 (_MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4231 #define MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \
4232 (_MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4234 #define MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \
4235 (_MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4236 #define MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \
4237 (_MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4238 #define MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \
4239 (_MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4240 #define MX6Q_PAD_EIM_A22__GPIO_2_16 \
4241 (_MX6Q_PAD_EIM_A22__GPIO_2_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4242 #define MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \
4243 (_MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4244 #define MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \
4245 (_MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4247 #define MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \
4248 (_MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4249 #define MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \
4250 (_MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4251 #define MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \
4252 (_MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4253 #define MX6Q_PAD_EIM_A21__RESERVED_RESERVED \
4254 (_MX6Q_PAD_EIM_A21__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4255 #define MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \
4256 (_MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4257 #define MX6Q_PAD_EIM_A21__GPIO_2_17 \
4258 (_MX6Q_PAD_EIM_A21__GPIO_2_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4259 #define MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \
4260 (_MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4261 #define MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \
4262 (_MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4264 #define MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \
4265 (_MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4266 #define MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \
4267 (_MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4268 #define MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \
4269 (_MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4270 #define MX6Q_PAD_EIM_A20__RESERVED_RESERVED \
4271 (_MX6Q_PAD_EIM_A20__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4272 #define MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \
4273 (_MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4274 #define MX6Q_PAD_EIM_A20__GPIO_2_18 \
4275 (_MX6Q_PAD_EIM_A20__GPIO_2_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4276 #define MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \
4277 (_MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4278 #define MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \
4279 (_MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4281 #define MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \
4282 (_MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4283 #define MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \
4284 (_MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4285 #define MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \
4286 (_MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4287 #define MX6Q_PAD_EIM_A19__RESERVED_RESERVED \
4288 (_MX6Q_PAD_EIM_A19__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4289 #define MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \
4290 (_MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4291 #define MX6Q_PAD_EIM_A19__GPIO_2_19 \
4292 (_MX6Q_PAD_EIM_A19__GPIO_2_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4293 #define MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \
4294 (_MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4295 #define MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \
4296 (_MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4298 #define MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \
4299 (_MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4300 #define MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \
4301 (_MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4302 #define MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \
4303 (_MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4304 #define MX6Q_PAD_EIM_A18__RESERVED_RESERVED \
4305 (_MX6Q_PAD_EIM_A18__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4306 #define MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \
4307 (_MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4308 #define MX6Q_PAD_EIM_A18__GPIO_2_20 \
4309 (_MX6Q_PAD_EIM_A18__GPIO_2_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4310 #define MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \
4311 (_MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4312 #define MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \
4313 (_MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4315 #define MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \
4316 (_MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4317 #define MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \
4318 (_MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4319 #define MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \
4320 (_MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4321 #define MX6Q_PAD_EIM_A17__RESERVED_RESERVED \
4322 (_MX6Q_PAD_EIM_A17__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4323 #define MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \
4324 (_MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4325 #define MX6Q_PAD_EIM_A17__GPIO_2_21 \
4326 (_MX6Q_PAD_EIM_A17__GPIO_2_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4327 #define MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \
4328 (_MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4329 #define MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \
4330 (_MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4332 #define MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \
4333 (_MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4334 #define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \
4335 (_MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4336 #define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \
4337 (_MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4338 #define MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \
4339 (_MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4340 #define MX6Q_PAD_EIM_A16__GPIO_2_22 \
4341 (_MX6Q_PAD_EIM_A16__GPIO_2_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4342 #define MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \
4343 (_MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4344 #define MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \
4345 (_MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4347 #define MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \
4348 (_MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4349 #define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \
4350 (_MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4351 #define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \
4352 (_MX6Q_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4353 #define MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \
4354 (_MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4355 #define MX6Q_PAD_EIM_CS0__GPIO_2_23 \
4356 (_MX6Q_PAD_EIM_CS0__GPIO_2_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4357 #define MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \
4358 (_MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4360 #define MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \
4361 (_MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4362 #define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \
4363 (_MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4364 #define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \
4365 (_MX6Q_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
4366 #define MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \
4367 (_MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4368 #define MX6Q_PAD_EIM_CS1__GPIO_2_24 \
4369 (_MX6Q_PAD_EIM_CS1__GPIO_2_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4370 #define MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \
4371 (_MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4373 #define MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \
4374 (_MX6Q_PAD_EIM_OE__WEIM_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
4375 #define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \
4376 (_MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4377 #define MX6Q_PAD_EIM_OE__ECSPI2_MISO \
4378 (_MX6Q_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
4379 #define MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \
4380 (_MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4381 #define MX6Q_PAD_EIM_OE__GPIO_2_25 \
4382 (_MX6Q_PAD_EIM_OE__GPIO_2_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4383 #define MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \
4384 (_MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4386 #define MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \
4387 (_MX6Q_PAD_EIM_RW__WEIM_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL))
4388 #define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \
4389 (_MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4390 #define MX6Q_PAD_EIM_RW__ECSPI2_SS0 \
4391 (_MX6Q_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4392 #define MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \
4393 (_MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4394 #define MX6Q_PAD_EIM_RW__GPIO_2_26 \
4395 (_MX6Q_PAD_EIM_RW__GPIO_2_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4396 #define MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \
4397 (_MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4398 #define MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \
4399 (_MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4401 #define MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \
4402 (_MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
4403 #define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \
4404 (_MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4405 #define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \
4406 (_MX6Q_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4407 #define MX6Q_PAD_EIM_LBA__GPIO_2_27 \
4408 (_MX6Q_PAD_EIM_LBA__GPIO_2_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4409 #define MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \
4410 (_MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4411 #define MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \
4412 (_MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4414 #define MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \
4415 (_MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4416 #define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \
4417 (_MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4418 #define MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \
4419 (_MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4420 #define MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \
4421 (_MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4422 #define MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \
4423 (_MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
4424 #define MX6Q_PAD_EIM_EB0__GPIO_2_28 \
4425 (_MX6Q_PAD_EIM_EB0__GPIO_2_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4426 #define MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \
4427 (_MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4428 #define MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \
4429 (_MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4431 #define MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \
4432 (_MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4433 #define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \
4434 (_MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4435 #define MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \
4436 (_MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4437 #define MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \
4438 (_MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4439 #define MX6Q_PAD_EIM_EB1__GPIO_2_29 \
4440 (_MX6Q_PAD_EIM_EB1__GPIO_2_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4441 #define MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \
4442 (_MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4443 #define MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \
4444 (_MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4446 #define MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \
4447 (_MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4448 #define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \
4449 (_MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4450 #define MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \
4451 (_MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4452 #define MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \
4453 (_MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4454 #define MX6Q_PAD_EIM_DA0__GPIO_3_0 \
4455 (_MX6Q_PAD_EIM_DA0__GPIO_3_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4456 #define MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \
4457 (_MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4458 #define MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \
4459 (_MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4461 #define MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \
4462 (_MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4463 #define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \
4464 (_MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4465 #define MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \
4466 (_MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4467 #define MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \
4468 (_MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4469 #define MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \
4470 (_MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
4471 #define MX6Q_PAD_EIM_DA1__GPIO_3_1 \
4472 (_MX6Q_PAD_EIM_DA1__GPIO_3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4473 #define MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \
4474 (_MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4475 #define MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \
4476 (_MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4478 #define MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \
4479 (_MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4480 #define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \
4481 (_MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4482 #define MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \
4483 (_MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4484 #define MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \
4485 (_MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4486 #define MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \
4487 (_MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
4488 #define MX6Q_PAD_EIM_DA2__GPIO_3_2 \
4489 (_MX6Q_PAD_EIM_DA2__GPIO_3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4490 #define MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \
4491 (_MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4492 #define MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \
4493 (_MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4495 #define MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \
4496 (_MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4497 #define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \
4498 (_MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4499 #define MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \
4500 (_MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4501 #define MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \
4502 (_MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4503 #define MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \
4504 (_MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ | MUX_PAD_CTRL(NO_PAD_CTRL))
4505 #define MX6Q_PAD_EIM_DA3__GPIO_3_3 \
4506 (_MX6Q_PAD_EIM_DA3__GPIO_3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4507 #define MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \
4508 (_MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4509 #define MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \
4510 (_MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4512 #define MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \
4513 (_MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4514 #define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \
4515 (_MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4516 #define MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \
4517 (_MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4518 #define MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \
4519 (_MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4520 #define MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \
4521 (_MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
4522 #define MX6Q_PAD_EIM_DA4__GPIO_3_4 \
4523 (_MX6Q_PAD_EIM_DA4__GPIO_3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4524 #define MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \
4525 (_MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4526 #define MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \
4527 (_MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4529 #define MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \
4530 (_MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4531 #define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \
4532 (_MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4533 #define MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \
4534 (_MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4535 #define MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \
4536 (_MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4537 #define MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \
4538 (_MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
4539 #define MX6Q_PAD_EIM_DA5__GPIO_3_5 \
4540 (_MX6Q_PAD_EIM_DA5__GPIO_3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4541 #define MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \
4542 (_MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4543 #define MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \
4544 (_MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4546 #define MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \
4547 (_MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4548 #define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \
4549 (_MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4550 #define MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \
4551 (_MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4552 #define MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \
4553 (_MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4554 #define MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \
4555 (_MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN | MUX_PAD_CTRL(NO_PAD_CTRL))
4556 #define MX6Q_PAD_EIM_DA6__GPIO_3_6 \
4557 (_MX6Q_PAD_EIM_DA6__GPIO_3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4558 #define MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \
4559 (_MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4560 #define MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \
4561 (_MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4563 #define MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \
4564 (_MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4565 #define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \
4566 (_MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4567 #define MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \
4568 (_MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4569 #define MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \
4570 (_MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4571 #define MX6Q_PAD_EIM_DA7__GPIO_3_7 \
4572 (_MX6Q_PAD_EIM_DA7__GPIO_3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4573 #define MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \
4574 (_MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4575 #define MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \
4576 (_MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4578 #define MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \
4579 (_MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4580 #define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \
4581 (_MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4582 #define MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \
4583 (_MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4584 #define MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \
4585 (_MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4586 #define MX6Q_PAD_EIM_DA8__GPIO_3_8 \
4587 (_MX6Q_PAD_EIM_DA8__GPIO_3_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4588 #define MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \
4589 (_MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4590 #define MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \
4591 (_MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4593 #define MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \
4594 (_MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4595 #define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \
4596 (_MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4597 #define MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \
4598 (_MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4599 #define MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \
4600 (_MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4601 #define MX6Q_PAD_EIM_DA9__GPIO_3_9 \
4602 (_MX6Q_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4603 #define MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \
4604 (_MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4605 #define MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \
4606 (_MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4608 #define MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \
4609 (_MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4610 #define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \
4611 (_MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4612 #define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \
4613 (_MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
4614 #define MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \
4615 (_MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4616 #define MX6Q_PAD_EIM_DA10__GPIO_3_10 \
4617 (_MX6Q_PAD_EIM_DA10__GPIO_3_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4618 #define MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \
4619 (_MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4620 #define MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \
4621 (_MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4623 #define MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \
4624 (_MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4625 #define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \
4626 (_MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4627 #define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \
4628 (_MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
4629 #define MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \
4630 (_MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4631 #define MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \
4632 (_MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4633 #define MX6Q_PAD_EIM_DA11__GPIO_3_11 \
4634 (_MX6Q_PAD_EIM_DA11__GPIO_3_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4635 #define MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \
4636 (_MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4637 #define MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \
4638 (_MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4640 #define MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \
4641 (_MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4642 #define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \
4643 (_MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4644 #define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \
4645 (_MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
4646 #define MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \
4647 (_MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4648 #define MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \
4649 (_MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4650 #define MX6Q_PAD_EIM_DA12__GPIO_3_12 \
4651 (_MX6Q_PAD_EIM_DA12__GPIO_3_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4652 #define MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \
4653 (_MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4654 #define MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \
4655 (_MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4657 #define MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \
4658 (_MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4659 #define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \
4660 (_MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
4661 #define MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \
4662 (_MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4663 #define MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \
4664 (_MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4665 #define MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \
4666 (_MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4667 #define MX6Q_PAD_EIM_DA13__GPIO_3_13 \
4668 (_MX6Q_PAD_EIM_DA13__GPIO_3_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4669 #define MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \
4670 (_MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4671 #define MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \
4672 (_MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4674 #define MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \
4675 (_MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4676 #define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \
4677 (_MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
4678 #define MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \
4679 (_MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4680 #define MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \
4681 (_MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4682 #define MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \
4683 (_MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4684 #define MX6Q_PAD_EIM_DA14__GPIO_3_14 \
4685 (_MX6Q_PAD_EIM_DA14__GPIO_3_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4686 #define MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \
4687 (_MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4688 #define MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \
4689 (_MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4691 #define MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \
4692 (_MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4693 #define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \
4694 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4695 #define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \
4696 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4697 #define MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \
4698 (_MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4699 #define MX6Q_PAD_EIM_DA15__GPIO_3_15 \
4700 (_MX6Q_PAD_EIM_DA15__GPIO_3_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4701 #define MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \
4702 (_MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4703 #define MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \
4704 (_MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4706 #define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \
4707 (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
4708 #define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \
4709 (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL))
4710 #define MX6Q_PAD_EIM_WAIT__GPIO_5_0 \
4711 (_MX6Q_PAD_EIM_WAIT__GPIO_5_0 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
4712 #define MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \
4713 (_MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
4714 #define MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \
4715 (_MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4717 #define MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \
4718 (_MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4719 #define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \
4720 (_MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4721 #define MX6Q_PAD_EIM_BCLK__GPIO_6_31 \
4722 (_MX6Q_PAD_EIM_BCLK__GPIO_6_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4723 #define MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \
4724 (_MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4726 #define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \
4727 (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4728 #define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \
4729 (_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4730 #define MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \
4731 (_MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4732 #define MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \
4733 (_MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4734 #define MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \
4735 (_MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4736 #define MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \
4737 (_MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4739 #define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \
4740 (_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4741 #define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \
4742 (_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4743 #define MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \
4744 (_MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
4745 #define MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \
4746 (_MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4747 #define MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \
4748 (_MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4749 #define MX6Q_PAD_DI0_PIN15__GPIO_4_17 \
4750 (_MX6Q_PAD_DI0_PIN15__GPIO_4_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4751 #define MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \
4752 (_MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4754 #define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \
4755 (_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4756 #define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \
4757 (_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4758 #define MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \
4759 (_MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
4760 #define MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \
4761 (_MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
4762 #define MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \
4763 (_MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4764 #define MX6Q_PAD_DI0_PIN2__GPIO_4_18 \
4765 (_MX6Q_PAD_DI0_PIN2__GPIO_4_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4766 #define MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \
4767 (_MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4768 #define MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \
4769 (_MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4771 #define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \
4772 (_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4773 #define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \
4774 (_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4775 #define MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \
4776 (_MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
4777 #define MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \
4778 (_MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4779 #define MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \
4780 (_MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4781 #define MX6Q_PAD_DI0_PIN3__GPIO_4_19 \
4782 (_MX6Q_PAD_DI0_PIN3__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4783 #define MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \
4784 (_MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4785 #define MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \
4786 (_MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4788 #define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \
4789 (_MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4790 #define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \
4791 (_MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4792 #define MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \
4793 (_MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
4794 #define MX6Q_PAD_DI0_PIN4__USDHC1_WP \
4795 (_MX6Q_PAD_DI0_PIN4__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4796 #define MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \
4797 (_MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL))
4798 #define MX6Q_PAD_DI0_PIN4__GPIO_4_20 \
4799 (_MX6Q_PAD_DI0_PIN4__GPIO_4_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4800 #define MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \
4801 (_MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4802 #define MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \
4803 (_MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4805 #define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \
4806 (_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4807 #define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \
4808 (_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4809 #define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \
4810 (_MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4811 #define MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \
4812 (_MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4813 #define MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \
4814 (_MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL))
4815 #define MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \
4816 (_MX6Q_PAD_DISP0_DAT0__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4817 #define MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \
4818 (_MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4820 #define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \
4821 (_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4822 #define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \
4823 (_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4824 #define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \
4825 (_MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
4826 #define MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \
4827 (_MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4828 #define MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
4829 (_MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
4830 #define MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \
4831 (_MX6Q_PAD_DISP0_DAT1__GPIO_4_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4832 #define MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \
4833 (_MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4834 #define MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \
4835 (_MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4837 #define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \
4838 (_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4839 #define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \
4840 (_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4841 #define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \
4842 (_MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
4843 #define MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \
4844 (_MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4845 #define MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \
4846 (_MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
4847 #define MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \
4848 (_MX6Q_PAD_DISP0_DAT2__GPIO_4_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4849 #define MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \
4850 (_MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4851 #define MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \
4852 (_MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4854 #define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \
4855 (_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4856 #define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \
4857 (_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4858 #define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \
4859 (_MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4860 #define MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \
4861 (_MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4862 #define MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \
4863 (_MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
4864 #define MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \
4865 (_MX6Q_PAD_DISP0_DAT3__GPIO_4_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4866 #define MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \
4867 (_MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4868 #define MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \
4869 (_MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4871 #define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \
4872 (_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4873 #define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \
4874 (_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4875 #define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \
4876 (_MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4877 #define MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \
4878 (_MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4879 #define MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \
4880 (_MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL))
4881 #define MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \
4882 (_MX6Q_PAD_DISP0_DAT4__GPIO_4_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4883 #define MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \
4884 (_MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4885 #define MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \
4886 (_MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4888 #define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \
4889 (_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4890 #define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \
4891 (_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4892 #define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \
4893 (_MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4894 #define MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \
4895 (_MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
4896 #define MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \
4897 (_MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL))
4898 #define MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \
4899 (_MX6Q_PAD_DISP0_DAT5__GPIO_4_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4900 #define MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \
4901 (_MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4902 #define MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \
4903 (_MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4905 #define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \
4906 (_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4907 #define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \
4908 (_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4909 #define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \
4910 (_MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4911 #define MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \
4912 (_MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
4913 #define MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \
4914 (_MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
4915 #define MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \
4916 (_MX6Q_PAD_DISP0_DAT6__GPIO_4_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4917 #define MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \
4918 (_MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4919 #define MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \
4920 (_MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4922 #define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \
4923 (_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4924 #define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \
4925 (_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4926 #define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \
4927 (_MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
4928 #define MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \
4929 (_MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4930 #define MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \
4931 (_MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4932 #define MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \
4933 (_MX6Q_PAD_DISP0_DAT7__GPIO_4_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4934 #define MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \
4935 (_MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4936 #define MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \
4937 (_MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4939 #define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \
4940 (_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4941 #define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \
4942 (_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4943 #define MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \
4944 (_MX6Q_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
4945 #define MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \
4946 (_MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
4947 #define MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \
4948 (_MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4949 #define MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \
4950 (_MX6Q_PAD_DISP0_DAT8__GPIO_4_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4951 #define MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \
4952 (_MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4953 #define MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \
4954 (_MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4956 #define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \
4957 (_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4958 #define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \
4959 (_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4960 #define MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \
4961 (_MX6Q_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
4962 #define MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \
4963 (_MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
4964 #define MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \
4965 (_MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4966 #define MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \
4967 (_MX6Q_PAD_DISP0_DAT9__GPIO_4_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
4968 #define MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \
4969 (_MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4970 #define MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \
4971 (_MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4973 #define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \
4974 (_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4975 #define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \
4976 (_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4977 #define MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \
4978 (_MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4979 #define MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
4980 (_MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4981 #define MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \
4982 (_MX6Q_PAD_DISP0_DAT10__GPIO_4_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4983 #define MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \
4984 (_MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4985 #define MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \
4986 (_MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4988 #define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \
4989 (_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4990 #define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \
4991 (_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4992 #define MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \
4993 (_MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4994 #define MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
4995 (_MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4996 #define MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \
4997 (_MX6Q_PAD_DISP0_DAT11__GPIO_5_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4998 #define MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \
4999 (_MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
5000 #define MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \
5001 (_MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
5003 #define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \
5004 (_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5005 #define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \
5006 (_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5007 #define MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED \
5008 (_MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5009 #define MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
5010 (_MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5011 #define MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \
5012 (_MX6Q_PAD_DISP0_DAT12__GPIO_5_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5013 #define MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \
5014 (_MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
5015 #define MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \
5016 (_MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
5018 #define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \
5019 (_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5020 #define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \
5021 (_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5022 #define MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \
5023 (_MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
5024 #define MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
5025 (_MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5026 #define MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \
5027 (_MX6Q_PAD_DISP0_DAT13__GPIO_5_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5028 #define MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \
5029 (_MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
5030 #define MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \
5031 (_MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
5033 #define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \
5034 (_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5035 #define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \
5036 (_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5037 #define MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \
5038 (_MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
5039 #define MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
5040 (_MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5041 #define MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \
5042 (_MX6Q_PAD_DISP0_DAT14__GPIO_5_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5043 #define MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \
5044 (_MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
5046 #define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \
5047 (_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5048 #define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \
5049 (_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5050 #define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \
5051 (_MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5052 #define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \
5053 (_MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5054 #define MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
5055 (_MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5056 #define MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \
5057 (_MX6Q_PAD_DISP0_DAT15__GPIO_5_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
5058 #define MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \
5059 (_MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
5060 #define MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \
5061 (_MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
5063 #define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \
5064 (_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5065 #define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \
5066 (_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5067 #define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \
5068 (_MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
5069 #define MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \
5070 (_MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
5071 #define MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \
5072 (_MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5073 #define MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \
5074 (_MX6Q_PAD_DISP0_DAT16__GPIO_5_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
5075 #define MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \
5076 (_MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
5077 #define MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \
5078 (_MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
5080 #define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \
5081 (_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5082 #define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \
5083 (_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5084 #define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \
5085 (_MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
5086 #define MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \
5087 (_MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5088 #define MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \
5089 (_MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5090 #define MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \
5091 (_MX6Q_PAD_DISP0_DAT17__GPIO_5_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
5092 #define MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \
5093 (_MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
5094 #define MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \
5095 (_MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
5097 #define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \
5098 (_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5099 #define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \
5100 (_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5101 #define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \
5102 (_MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5103 #define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \
5104 (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
5105 #define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \
5106 (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
5107 #define MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \
5108 (_MX6Q_PAD_DISP0_DAT18__GPIO_5_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
5109 #define MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \
5110 (_MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
5111 #define MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \
5112 (_MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5114 #define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \
5115 (_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5116 #define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \
5117 (_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5118 #define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \
5119 (_MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5120 #define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \
5121 (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5122 #define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \
5123 (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
5124 #define MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \
5125 (_MX6Q_PAD_DISP0_DAT19__GPIO_5_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
5126 #define MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \
5127 (_MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
5128 #define MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \
5129 (_MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5131 #define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \
5132 (_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5133 #define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \
5134 (_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5135 #define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \
5136 (_MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5137 #define MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \
5138 (_MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
5139 #define MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
5140 (_MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5141 #define MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \
5142 (_MX6Q_PAD_DISP0_DAT20__GPIO_5_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
5143 #define MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \
5144 (_MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
5145 #define MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \
5146 (_MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
5148 #define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \
5149 (_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5150 #define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \
5151 (_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5152 #define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \
5153 (_MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
5154 #define MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \
5155 (_MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5156 #define MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \
5157 (_MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5158 #define MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \
5159 (_MX6Q_PAD_DISP0_DAT21__GPIO_5_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
5160 #define MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \
5161 (_MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
5162 #define MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \
5163 (_MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
5165 #define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \
5166 (_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5167 #define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \
5168 (_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5169 #define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \
5170 (_MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
5171 #define MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \
5172 (_MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
5173 #define MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \
5174 (_MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5175 #define MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \
5176 (_MX6Q_PAD_DISP0_DAT22__GPIO_5_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
5177 #define MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \
5178 (_MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
5179 #define MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \
5180 (_MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
5182 #define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \
5183 (_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5184 #define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \
5185 (_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5186 #define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \
5187 (_MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5188 #define MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \
5189 (_MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5190 #define MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \
5191 (_MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5192 #define MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \
5193 (_MX6Q_PAD_DISP0_DAT23__GPIO_5_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
5194 #define MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \
5195 (_MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
5196 #define MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \
5197 (_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
5199 #define MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED \
5200 (_MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5201 #define MX6Q_PAD_ENET_MDIO__ENET_MDIO \
5202 (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | \
5203 MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
5204 #define MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \
5205 (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5206 #define MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \
5207 (_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5208 #define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \
5209 (_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5210 #define MX6Q_PAD_ENET_MDIO__GPIO_1_22 \
5211 (_MX6Q_PAD_ENET_MDIO__GPIO_1_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
5212 #define MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \
5213 (_MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
5215 #define MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED \
5216 (_MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5217 #define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \
5218 (_MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
5219 #define MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \
5220 (_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5221 #define MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \
5222 (_MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5223 #define MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \
5224 (_MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
5225 #define MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \
5226 (_MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5227 #define MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \
5228 (_MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))
5230 #define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \
5231 (_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
5232 #define MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \
5233 (_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5234 #define MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \
5235 (_MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5236 #define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \
5237 (_MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5238 #define MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \
5239 (_MX6Q_PAD_ENET_RX_ER__GPIO_1_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
5240 #define MX6Q_PAD_ENET_RX_ER__PHY_TDI \
5241 (_MX6Q_PAD_ENET_RX_ER__PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
5242 #define MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \
5243 (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5245 #define MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED \
5246 (_MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5247 #define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \
5248 (_MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
5249 #define MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \
5250 (_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5251 #define MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \
5252 (_MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5253 #define MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \
5254 (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
5255 #define MX6Q_PAD_ENET_CRS_DV__PHY_TDO \
5256 (_MX6Q_PAD_ENET_CRS_DV__PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
5257 #define MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \
5258 (_MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5260 #define MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \
5261 (_MX6Q_PAD_ENET_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
5262 #define MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \
5263 (_MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5264 #define MX6Q_PAD_ENET_RXD1__ESAI1_FST \
5265 (_MX6Q_PAD_ENET_RXD1__ESAI1_FST | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5266 #define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \
5267 (_MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5268 #define MX6Q_PAD_ENET_RXD1__GPIO_1_26 \
5269 (_MX6Q_PAD_ENET_RXD1__GPIO_1_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
5270 #define MX6Q_PAD_ENET_RXD1__PHY_TCK \
5271 (_MX6Q_PAD_ENET_RXD1__PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
5272 #define MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \
5273 (_MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))
5275 #define MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \
5276 (_MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5277 #define MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \
5278 (_MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5279 #define MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \
5280 (_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5281 #define MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \
5282 (_MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5283 #define MX6Q_PAD_ENET_RXD0__GPIO_1_27 \
5284 (_MX6Q_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
5285 #define MX6Q_PAD_ENET_RXD0__PHY_TMS \
5286 (_MX6Q_PAD_ENET_RXD0__PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
5287 #define MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \
5288 (_MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))
5290 #define MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED \
5291 (_MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5292 #define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \
5293 (_MX6Q_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
5294 #define MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \
5295 (_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5296 #define MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \
5297 (_MX6Q_PAD_ENET_TX_EN__GPIO_1_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
5298 #define MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \
5299 (_MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
5300 #define MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \
5301 (_MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))
5303 #define MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \
5304 (_MX6Q_PAD_ENET_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5305 #define MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \
5306 (_MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5307 #define MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \
5308 (_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5309 #define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \
5310 (_MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
5311 #define MX6Q_PAD_ENET_TXD1__GPIO_1_29 \
5312 (_MX6Q_PAD_ENET_TXD1__GPIO_1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
5313 #define MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \
5314 (_MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
5315 #define MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \
5316 (_MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5318 #define MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED \
5319 (_MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5320 #define MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \
5321 (_MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5322 #define MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \
5323 (_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5324 #define MX6Q_PAD_ENET_TXD0__GPIO_1_30 \
5325 (_MX6Q_PAD_ENET_TXD0__GPIO_1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
5326 #define MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \
5327 (_MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
5328 #define MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \
5329 (_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5331 #define MX6Q_PAD_ENET_MDC__MLB_MLBDAT \
5332 (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
5333 #define MX6Q_PAD_ENET_MDC__ENET_MDC \
5334 (_MX6Q_PAD_ENET_MDC__ENET_MDC | \
5335 MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
5336 #define MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \
5337 (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5338 #define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \
5339 (_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
5340 #define MX6Q_PAD_ENET_MDC__GPIO_1_31 \
5341 (_MX6Q_PAD_ENET_MDC__GPIO_1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
5342 #define MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \
5343 (_MX6Q_PAD_ENET_MDC__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
5344 #define MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \
5345 (_MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))
5347 #define MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \
5348 (_MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
5350 #define MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \
5351 (_MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
5353 #define MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \
5354 (_MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
5356 #define MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \
5357 (_MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
5359 #define MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \
5360 (_MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
5362 #define MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \
5363 (_MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
5365 #define MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \
5366 (_MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
5368 #define MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \
5369 (_MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
5371 #define MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \
5372 (_MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5374 #define MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \
5375 (_MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5377 #define MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \
5378 (_MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
5380 #define MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \
5381 (_MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
5383 #define MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \
5384 (_MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
5386 #define MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \
5387 (_MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
5389 #define MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \
5390 (_MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
5392 #define MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \
5393 (_MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
5395 #define MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \
5396 (_MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
5398 #define MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \
5399 (_MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
5401 #define MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \
5402 (_MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5404 #define MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \
5405 (_MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5407 #define MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \
5408 (_MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
5410 #define MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \
5411 (_MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
5413 #define MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \
5414 (_MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
5416 #define MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \
5417 (_MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
5419 #define MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \
5420 (_MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
5422 #define MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \
5423 (_MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
5425 #define MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \
5426 (_MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5428 #define MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \
5429 (_MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
5431 #define MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \
5432 (_MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
5434 #define MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \
5435 (_MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5437 #define MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \
5438 (_MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
5440 #define MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \
5441 (_MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
5443 #define MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \
5444 (_MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
5446 #define MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \
5447 (_MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
5449 #define MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \
5450 (_MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
5452 #define MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \
5453 (_MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
5455 #define MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \
5456 (_MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
5458 #define MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \
5459 (_MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5461 #define MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \
5462 (_MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
5464 #define MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \
5465 (_MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5467 #define MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \
5468 (_MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5470 #define MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \
5471 (_MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5473 #define MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \
5474 (_MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5476 #define MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \
5477 (_MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5479 #define MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \
5480 (_MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5482 #define MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \
5483 (_MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5485 #define MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \
5486 (_MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5488 #define MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \
5489 (_MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5491 #define MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \
5492 (_MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5494 #define MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \
5495 (_MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
5497 #define MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \
5498 (_MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
5500 #define MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \
5501 (_MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
5503 #define MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \
5504 (_MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
5506 #define MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \
5507 (_MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
5509 #define MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \
5510 (_MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
5512 #define MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \
5513 (_MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
5515 #define MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \
5516 (_MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS | MUX_PAD_CTRL(NO_PAD_CTRL))
5518 #define MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \
5519 (_MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5521 #define MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \
5522 (_MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5524 #define MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \
5525 (_MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS | MUX_PAD_CTRL(NO_PAD_CTRL))
5527 #define MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \
5528 (_MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET | MUX_PAD_CTRL(NO_PAD_CTRL))
5530 #define MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \
5531 (_MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5533 #define MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \
5534 (_MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5536 #define MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \
5537 (_MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5539 #define MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \
5540 (_MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5542 #define MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \
5543 (_MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5545 #define MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \
5546 (_MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5548 #define MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \
5549 (_MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5551 #define MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \
5552 (_MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5554 #define MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \
5555 (_MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5557 #define MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \
5558 (_MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE | MUX_PAD_CTRL(NO_PAD_CTRL))
5560 #define MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \
5561 (_MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5563 #define MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \
5564 (_MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5566 #define MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \
5567 (_MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5569 #define MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \
5570 (_MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5572 #define MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \
5573 (_MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5575 #define MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \
5576 (_MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5578 #define MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \
5579 (_MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5581 #define MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \
5582 (_MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5584 #define MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \
5585 (_MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5587 #define MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \
5588 (_MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5590 #define MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \
5591 (_MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5593 #define MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \
5594 (_MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
5596 #define MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \
5597 (_MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
5599 #define MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \
5600 (_MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
5602 #define MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \
5603 (_MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
5605 #define MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \
5606 (_MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
5608 #define MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \
5609 (_MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
5611 #define MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \
5612 (_MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5614 #define MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \
5615 (_MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
5617 #define MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \
5618 (_MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5620 #define MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \
5621 (_MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
5623 #define MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \
5624 (_MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
5626 #define MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \
5627 (_MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
5629 #define MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \
5630 (_MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 | MUX_PAD_CTRL(NO_PAD_CTRL))
5632 #define MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \
5633 (_MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 | MUX_PAD_CTRL(NO_PAD_CTRL))
5635 #define MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \
5636 (_MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 | MUX_PAD_CTRL(NO_PAD_CTRL))
5638 #define MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \
5639 (_MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 | MUX_PAD_CTRL(NO_PAD_CTRL))
5641 #define MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \
5642 (_MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 | MUX_PAD_CTRL(NO_PAD_CTRL))
5644 #define MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \
5645 (_MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5647 #define MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \
5648 (_MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5650 #define MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \
5651 (_MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 | MUX_PAD_CTRL(NO_PAD_CTRL))
5653 #define MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \
5654 (_MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5656 #define MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \
5657 (_MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 | MUX_PAD_CTRL(NO_PAD_CTRL))
5659 #define MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \
5660 (_MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 | MUX_PAD_CTRL(NO_PAD_CTRL))
5662 #define MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \
5663 (_MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 | MUX_PAD_CTRL(NO_PAD_CTRL))
5665 #define MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \
5666 (_MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 | MUX_PAD_CTRL(NO_PAD_CTRL))
5668 #define MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \
5669 (_MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5671 #define MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \
5672 (_MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 | MUX_PAD_CTRL(NO_PAD_CTRL))
5674 #define MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \
5675 (_MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 | MUX_PAD_CTRL(NO_PAD_CTRL))
5677 #define MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \
5678 (_MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 | MUX_PAD_CTRL(NO_PAD_CTRL))
5680 #define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \
5681 (_MX6Q_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5682 #define MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \
5683 (_MX6Q_PAD_KEY_COL0__ENET_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5684 #define MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \
5685 (_MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
5686 #define MX6Q_PAD_KEY_COL0__KPP_COL_0 \
5687 (_MX6Q_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5688 #define MX6Q_PAD_KEY_COL0__UART4_TXD \
5689 (_MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5690 #define MX6Q_PAD_KEY_COL0__UART4_RXD \
5691 (_MX6Q_PAD_KEY_COL0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5692 #define MX6Q_PAD_KEY_COL0__GPIO_4_6 \
5693 (_MX6Q_PAD_KEY_COL0__GPIO_4_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5694 #define MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \
5695 (_MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5696 #define MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \
5697 (_MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
5699 #define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \
5700 (_MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
5701 #define MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \
5702 (_MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5703 #define MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \
5704 (_MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5705 #define MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \
5706 (_MX6Q_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5707 #define MX6Q_PAD_KEY_ROW0__UART4_TXD \
5708 (_MX6Q_PAD_KEY_ROW0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5709 #define MX6Q_PAD_KEY_ROW0__UART4_RXD \
5710 (_MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5711 #define MX6Q_PAD_KEY_ROW0__GPIO_4_7 \
5712 (_MX6Q_PAD_KEY_ROW0__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5713 #define MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \
5714 (_MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5715 #define MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \
5716 (_MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5718 #define MX6Q_PAD_KEY_COL1__ECSPI1_MISO \
5719 (_MX6Q_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
5720 #define MX6Q_PAD_KEY_COL1__ENET_MDIO \
5721 (_MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
5722 #define MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \
5723 (_MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
5724 #define MX6Q_PAD_KEY_COL1__KPP_COL_1 \
5725 (_MX6Q_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5726 #define MX6Q_PAD_KEY_COL1__UART5_TXD \
5727 (_MX6Q_PAD_KEY_COL1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5728 #define MX6Q_PAD_KEY_COL1__UART5_RXD \
5729 (_MX6Q_PAD_KEY_COL1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5730 #define MX6Q_PAD_KEY_COL1__GPIO_4_8 \
5731 (_MX6Q_PAD_KEY_COL1__GPIO_4_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5732 #define MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \
5733 (_MX6Q_PAD_KEY_COL1__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5734 #define MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \
5735 (_MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5737 #define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \
5738 (_MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5739 #define MX6Q_PAD_KEY_ROW1__ENET_COL \
5740 (_MX6Q_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
5741 #define MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \
5742 (_MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5743 #define MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \
5744 (_MX6Q_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5745 #define MX6Q_PAD_KEY_ROW1__UART5_TXD \
5746 (_MX6Q_PAD_KEY_ROW1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5747 #define MX6Q_PAD_KEY_ROW1__UART5_RXD \
5748 (_MX6Q_PAD_KEY_ROW1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5749 #define MX6Q_PAD_KEY_ROW1__GPIO_4_9 \
5750 (_MX6Q_PAD_KEY_ROW1__GPIO_4_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
5751 #define MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \
5752 (_MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5753 #define MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \
5754 (_MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5756 #define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \
5757 (_MX6Q_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5758 #define MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \
5759 (_MX6Q_PAD_KEY_COL2__ENET_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5760 #define MX6Q_PAD_KEY_COL2__CAN1_TXCAN \
5761 (_MX6Q_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5762 #define MX6Q_PAD_KEY_COL2__KPP_COL_2 \
5763 (_MX6Q_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5764 #define MX6Q_PAD_KEY_COL2__ENET_MDC \
5765 (_MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
5766 #define MX6Q_PAD_KEY_COL2__GPIO_4_10 \
5767 (_MX6Q_PAD_KEY_COL2__GPIO_4_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
5768 #define MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \
5769 (_MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))
5770 #define MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \
5771 (_MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5773 #define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \
5774 (_MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5775 #define MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \
5776 (_MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5777 #define MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \
5778 (_MX6Q_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5779 #define MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \
5780 (_MX6Q_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5781 #define MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \
5782 (_MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5783 #define MX6Q_PAD_KEY_ROW2__GPIO_4_11 \
5784 (_MX6Q_PAD_KEY_ROW2__GPIO_4_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
5785 #define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \
5786 (_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
5787 #define MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \
5788 (_MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5790 #define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \
5791 (_MX6Q_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5792 #define MX6Q_PAD_KEY_COL3__ENET_CRS \
5793 (_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
5794 #define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \
5795 (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
5796 #define MX6Q_PAD_KEY_COL3__KPP_COL_3 \
5797 (_MX6Q_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5798 #define MX6Q_PAD_KEY_COL3__I2C2_SCL \
5799 (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
5800 #define MX6Q_PAD_KEY_COL3__GPIO_4_12 \
5801 (_MX6Q_PAD_KEY_COL3__GPIO_4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
5802 #define MX6Q_PAD_KEY_COL3__SPDIF_IN1 \
5803 (_MX6Q_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5804 #define MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \
5805 (_MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5807 #define MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \
5808 (_MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5809 #define MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \
5810 (_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5811 #define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \
5812 (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
5813 #define MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \
5814 (_MX6Q_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5815 #define MX6Q_PAD_KEY_ROW3__I2C2_SDA \
5816 (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
5817 #define MX6Q_PAD_KEY_ROW3__GPIO_4_13 \
5818 (_MX6Q_PAD_KEY_ROW3__GPIO_4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
5819 #define MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \
5820 (_MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5821 #define MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \
5822 (_MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5824 #define MX6Q_PAD_KEY_COL4__CAN2_TXCAN \
5825 (_MX6Q_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5826 #define MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \
5827 (_MX6Q_PAD_KEY_COL4__IPU1_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5828 #define MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \
5829 (_MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
5830 #define MX6Q_PAD_KEY_COL4__KPP_COL_4 \
5831 (_MX6Q_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5832 #define MX6Q_PAD_KEY_COL4__UART5_CTS \
5833 (_MX6Q_PAD_KEY_COL4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5834 #define MX6Q_PAD_KEY_COL4__UART5_RTS \
5835 (_MX6Q_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5836 #define MX6Q_PAD_KEY_COL4__GPIO_4_14 \
5837 (_MX6Q_PAD_KEY_COL4__GPIO_4_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
5838 #define MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \
5839 (_MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
5840 #define MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \
5841 (_MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5843 #define MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \
5844 (_MX6Q_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5845 #define MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \
5846 (_MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5847 #define MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \
5848 (_MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
5849 #define MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \
5850 (_MX6Q_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5851 #define MX6Q_PAD_KEY_ROW4__UART5_CTS \
5852 (_MX6Q_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5853 #define MX6Q_PAD_KEY_ROW4__GPIO_4_15 \
5854 (_MX6Q_PAD_KEY_ROW4__GPIO_4_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
5855 #define MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \
5856 (_MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
5857 #define MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \
5858 (_MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5860 #define MX6Q_PAD_GPIO_0__CCM_CLKO \
5861 (_MX6Q_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(MX6Q_CCM_CLK0_PAD_CTRL))
5862 #define MX6Q_PAD_GPIO_0__KPP_COL_5 \
5863 (_MX6Q_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5864 #define MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \
5865 (_MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5866 #define MX6Q_PAD_GPIO_0__EPIT1_EPITO \
5867 (_MX6Q_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
5868 #define MX6Q_PAD_GPIO_0__GPIO_1_0 \
5869 (_MX6Q_PAD_GPIO_0__GPIO_1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5870 #define MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \
5871 (_MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
5872 #define MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \
5873 (_MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5875 #define MX6Q_PAD_GPIO_1__ESAI1_SCKR \
5876 (_MX6Q_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
5877 #define MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \
5878 (_MX6Q_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
5879 #define MX6Q_PAD_GPIO_1__KPP_ROW_5 \
5880 (_MX6Q_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5881 #define MX6Q_PAD_GPIO_1__PWM2_PWMO \
5882 (_MX6Q_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
5883 #define MX6Q_PAD_GPIO_1__GPIO_1_1 \
5884 (_MX6Q_PAD_GPIO_1__GPIO_1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5885 #define MX6Q_PAD_GPIO_1__USDHC1_CD \
5886 (_MX6Q_PAD_GPIO_1__USDHC1_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5887 #define MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \
5888 (_MX6Q_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL))
5890 #define MX6Q_PAD_GPIO_9__ESAI1_FSR \
5891 (_MX6Q_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5892 #define MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \
5893 (_MX6Q_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
5894 #define MX6Q_PAD_GPIO_9__KPP_COL_6 \
5895 (_MX6Q_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5896 #define MX6Q_PAD_GPIO_9__CCM_REF_EN_B \
5897 (_MX6Q_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
5898 #define MX6Q_PAD_GPIO_9__PWM1_PWMO \
5899 (_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
5900 #define MX6Q_PAD_GPIO_9__GPIO_1_9 \
5901 (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
5902 #define MX6Q_PAD_GPIO_9__USDHC1_WP \
5903 (_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5904 #define MX6Q_PAD_GPIO_9__SRC_EARLY_RST \
5905 (_MX6Q_PAD_GPIO_9__SRC_EARLY_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
5907 #define MX6Q_PAD_GPIO_3__ESAI1_HCKR \
5908 (_MX6Q_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
5909 #define MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \
5910 (_MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5911 #define MX6Q_PAD_GPIO_3__I2C3_SCL \
5912 (_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
5913 #define MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \
5914 (_MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5915 #define MX6Q_PAD_GPIO_3__CCM_CLKO2 \
5916 (_MX6Q_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5917 #define MX6Q_PAD_GPIO_3__GPIO_1_3 \
5918 (_MX6Q_PAD_GPIO_3__GPIO_1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5919 #define MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \
5920 (_MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
5921 #define MX6Q_PAD_GPIO_3__MLB_MLBCLK \
5922 (_MX6Q_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(MX6Q_MLB150_PAD_CTRL))
5924 #define MX6Q_PAD_GPIO_6__ESAI1_SCKT \
5925 (_MX6Q_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
5926 #define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
5927 (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5928 #define MX6Q_PAD_GPIO_6__I2C3_SDA \
5929 (_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
5930 #define MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \
5931 (_MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5932 #define MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \
5933 (_MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
5934 #define MX6Q_PAD_GPIO_6__GPIO_1_6 \
5935 (_MX6Q_PAD_GPIO_6__GPIO_1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5936 #define MX6Q_PAD_GPIO_6__USDHC2_LCTL \
5937 (_MX6Q_PAD_GPIO_6__USDHC2_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5938 #define MX6Q_PAD_GPIO_6__MLB_MLBSIG \
5939 (_MX6Q_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(MX6Q_MLB150_PAD_CTRL))
5941 #define MX6Q_PAD_GPIO_2__ESAI1_FST \
5942 (_MX6Q_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
5943 #define MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \
5944 (_MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5945 #define MX6Q_PAD_GPIO_2__KPP_ROW_6 \
5946 (_MX6Q_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5947 #define MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \
5948 (_MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5949 #define MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \
5950 (_MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5951 #define MX6Q_PAD_GPIO_2__GPIO_1_2 \
5952 (_MX6Q_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5953 #define MX6Q_PAD_GPIO_2__USDHC2_WP \
5954 (_MX6Q_PAD_GPIO_2__USDHC2_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5955 #define MX6Q_PAD_GPIO_2__MLB_MLBDAT \
5956 (_MX6Q_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(MX6Q_MLB150_PAD_CTRL))
5958 #define MX6Q_PAD_GPIO_4__ESAI1_HCKT \
5959 (_MX6Q_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
5960 #define MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \
5961 (_MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5962 #define MX6Q_PAD_GPIO_4__KPP_COL_7 \
5963 (_MX6Q_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5964 #define MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \
5965 (_MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5966 #define MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \
5967 (_MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5968 #define MX6Q_PAD_GPIO_4__GPIO_1_4 \
5969 (_MX6Q_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5970 #define MX6Q_PAD_GPIO_4__USDHC2_CD \
5971 (_MX6Q_PAD_GPIO_4__USDHC2_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5972 #define MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \
5973 (_MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED | MUX_PAD_CTRL(NO_PAD_CTRL))
5975 #define MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \
5976 (_MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5977 #define MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \
5978 (_MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5979 #define MX6Q_PAD_GPIO_5__KPP_ROW_7 \
5980 (_MX6Q_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5981 #define MX6Q_PAD_GPIO_5__CCM_CLKO \
5982 (_MX6Q_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
5983 #define MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \
5984 (_MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5985 #define MX6Q_PAD_GPIO_5__GPIO_1_5 \
5986 (_MX6Q_PAD_GPIO_5__GPIO_1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5987 #define MX6Q_PAD_GPIO_5__I2C3_SCL \
5988 (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
5989 #define MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \
5990 (_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI | MUX_PAD_CTRL(NO_PAD_CTRL))
5992 #define MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \
5993 (_MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5994 #define MX6Q_PAD_GPIO_7__ECSPI5_RDY \
5995 (_MX6Q_PAD_GPIO_7__ECSPI5_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
5996 #define MX6Q_PAD_GPIO_7__EPIT1_EPITO \
5997 (_MX6Q_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
5998 #define MX6Q_PAD_GPIO_7__CAN1_TXCAN \
5999 (_MX6Q_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
6000 #define MX6Q_PAD_GPIO_7__UART2_TXD \
6001 (_MX6Q_PAD_GPIO_7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6002 #define MX6Q_PAD_GPIO_7__UART2_RXD \
6003 (_MX6Q_PAD_GPIO_7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6004 #define MX6Q_PAD_GPIO_7__GPIO_1_7 \
6005 (_MX6Q_PAD_GPIO_7__GPIO_1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6006 #define MX6Q_PAD_GPIO_7__SPDIF_PLOCK \
6007 (_MX6Q_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
6008 #define MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \
6009 (_MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
6011 #define MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \
6012 (_MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6013 #define MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \
6014 (_MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
6015 #define MX6Q_PAD_GPIO_8__EPIT2_EPITO \
6016 (_MX6Q_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
6017 #define MX6Q_PAD_GPIO_8__CAN1_RXCAN \
6018 (_MX6Q_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
6019 #define MX6Q_PAD_GPIO_8__UART2_TXD \
6020 (_MX6Q_PAD_GPIO_8__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6021 #define MX6Q_PAD_GPIO_8__UART2_RXD \
6022 (_MX6Q_PAD_GPIO_8__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6023 #define MX6Q_PAD_GPIO_8__GPIO_1_8 \
6024 (_MX6Q_PAD_GPIO_8__GPIO_1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6025 #define MX6Q_PAD_GPIO_8__SPDIF_SRCLK \
6026 (_MX6Q_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6027 #define MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \
6028 (_MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))
6030 #define MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \
6031 (_MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6032 #define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \
6033 (_MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
6034 #define MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
6035 (_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
6036 #define MX6Q_PAD_GPIO_16__USDHC1_LCTL \
6037 (_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6038 #define MX6Q_PAD_GPIO_16__SPDIF_IN1 \
6039 (_MX6Q_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6040 #define MX6Q_PAD_GPIO_16__GPIO_7_11 \
6041 (_MX6Q_PAD_GPIO_16__GPIO_7_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6042 #define MX6Q_PAD_GPIO_16__I2C3_SDA \
6043 (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
6044 #define MX6Q_PAD_GPIO_16__SJC_DE_B \
6045 (_MX6Q_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
6047 #define MX6Q_PAD_GPIO_17__ESAI1_TX0 \
6048 (_MX6Q_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
6049 #define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \
6050 (_MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
6051 #define MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \
6052 (_MX6Q_PAD_GPIO_17__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
6053 #define MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \
6054 (_MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6055 #define MX6Q_PAD_GPIO_17__SPDIF_OUT1 \
6056 (_MX6Q_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(MX6Q_SPDIF_OUT_PAD_CTRL))
6057 #define MX6Q_PAD_GPIO_17__GPIO_7_12 \
6058 (_MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6059 #define MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \
6060 (_MX6Q_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL))
6062 #define MX6Q_PAD_GPIO_18__ESAI1_TX1 \
6063 (_MX6Q_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6064 #define MX6Q_PAD_GPIO_18__ENET_RX_CLK \
6065 (_MX6Q_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6066 #define MX6Q_PAD_GPIO_18__USDHC3_VSELECT \
6067 (_MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6068 #define MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \
6069 (_MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6070 #define MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \
6071 (_MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6072 #define MX6Q_PAD_GPIO_18__GPIO_7_13 \
6073 (_MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6074 #define MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \
6075 (_MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL | MUX_PAD_CTRL(NO_PAD_CTRL))
6076 #define MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \
6077 (_MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
6079 #define MX6Q_PAD_GPIO_19__KPP_COL_5 \
6080 (_MX6Q_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6081 #define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \
6082 (_MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
6083 #define MX6Q_PAD_GPIO_19__SPDIF_OUT1 \
6084 (_MX6Q_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6085 #define MX6Q_PAD_GPIO_19__CCM_CLKO \
6086 (_MX6Q_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
6087 #define MX6Q_PAD_GPIO_19__ECSPI1_RDY \
6088 (_MX6Q_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
6089 #define MX6Q_PAD_GPIO_19__GPIO_4_5 \
6090 (_MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6091 #define MX6Q_PAD_GPIO_19__ENET_TX_ER \
6092 (_MX6Q_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
6093 #define MX6Q_PAD_GPIO_19__SRC_INT_BOOT \
6094 (_MX6Q_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL))
6096 #define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \
6097 (_MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6098 #define MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \
6099 (_MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6100 #define MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \
6101 (_MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6102 #define MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \
6103 (_MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6104 #define MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \
6105 (_MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
6106 #define MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \
6107 (_MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO | MUX_PAD_CTRL(NO_PAD_CTRL))
6109 #define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \
6110 (_MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
6111 #define MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \
6112 (_MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6113 #define MX6Q_PAD_CSI0_MCLK__CCM_CLKO \
6114 (_MX6Q_PAD_CSI0_MCLK__CCM_CLKO | MUX_PAD_CTRL(MX6Q_CCM_CLK0_PAD_CTRL))
6115 #define MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \
6116 (_MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6117 #define MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \
6118 (_MX6Q_PAD_CSI0_MCLK__GPIO_5_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6119 #define MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \
6120 (_MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
6121 #define MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \
6122 (_MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
6124 #define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \
6125 (_MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
6126 #define MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \
6127 (_MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6128 #define MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \
6129 (_MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6130 #define MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \
6131 (_MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6132 #define MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \
6133 (_MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
6134 #define MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \
6135 (_MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
6136 #define MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \
6137 (_MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6139 #define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \
6140 (_MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
6141 #define MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \
6142 (_MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6143 #define MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \
6144 (_MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6145 #define MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \
6146 (_MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6147 #define MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \
6148 (_MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
6149 #define MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \
6150 (_MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
6151 #define MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \
6152 (_MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6154 #define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \
6155 (_MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6156 #define MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \
6157 (_MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6158 #define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \
6159 (_MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6160 #define MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \
6161 (_MX6Q_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6162 #define MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \
6163 (_MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
6164 #define MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \
6165 (_MX6Q_PAD_CSI0_DAT4__GPIO_5_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
6166 #define MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \
6167 (_MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
6168 #define MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \
6169 (_MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6171 #define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \
6172 (_MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6173 #define MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \
6174 (_MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6175 #define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \
6176 (_MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
6177 #define MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \
6178 (_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6179 #define MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \
6180 (_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
6181 #define MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \
6182 (_MX6Q_PAD_CSI0_DAT5__GPIO_5_23 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
6183 #define MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \
6184 (_MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
6185 #define MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \
6186 (_MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6188 #define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \
6189 (_MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6190 #define MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \
6191 (_MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6192 #define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \
6193 (_MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
6194 #define MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \
6195 (_MX6Q_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6196 #define MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \
6197 (_MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
6198 #define MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \
6199 (_MX6Q_PAD_CSI0_DAT6__GPIO_5_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
6200 #define MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \
6201 (_MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
6202 #define MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \
6203 (_MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6205 #define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \
6206 (_MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6207 #define MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \
6208 (_MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6209 #define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \
6210 (_MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6211 #define MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \
6212 (_MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6213 #define MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \
6214 (_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
6215 #define MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \
6216 (_MX6Q_PAD_CSI0_DAT7__GPIO_5_25 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
6217 #define MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \
6218 (_MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
6219 #define MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \
6220 (_MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6222 #define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \
6223 (_MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6224 #define MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \
6225 (_MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6226 #define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \
6227 (_MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6228 #define MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \
6229 (_MX6Q_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6230 #define MX6Q_PAD_CSI0_DAT8__I2C1_SDA \
6231 (_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
6232 #define MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \
6233 (_MX6Q_PAD_CSI0_DAT8__GPIO_5_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
6234 #define MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \
6235 (_MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
6236 #define MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \
6237 (_MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6239 #define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \
6240 (_MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6241 #define MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \
6242 (_MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6243 #define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \
6244 (_MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
6245 #define MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \
6246 (_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6247 #define MX6Q_PAD_CSI0_DAT9__I2C1_SCL \
6248 (_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
6249 #define MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \
6250 (_MX6Q_PAD_CSI0_DAT9__GPIO_5_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
6251 #define MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \
6252 (_MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
6253 #define MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \
6254 (_MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6256 #define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \
6257 (_MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6258 #define MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \
6259 (_MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
6260 #define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \
6261 (_MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
6262 #define MX6Q_PAD_CSI0_DAT10__UART1_TXD \
6263 (_MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6264 #define MX6Q_PAD_CSI0_DAT10__UART1_RXD \
6265 (_MX6Q_PAD_CSI0_DAT10__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6266 #define MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \
6267 (_MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6268 #define MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \
6269 (_MX6Q_PAD_CSI0_DAT10__GPIO_5_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
6270 #define MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \
6271 (_MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
6272 #define MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \
6273 (_MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6275 #define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \
6276 (_MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6277 #define MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \
6278 (_MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
6279 #define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \
6280 (_MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6281 #define MX6Q_PAD_CSI0_DAT11__UART1_TXD \
6282 (_MX6Q_PAD_CSI0_DAT11__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6283 #define MX6Q_PAD_CSI0_DAT11__UART1_RXD \
6284 (_MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6285 #define MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \
6286 (_MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6287 #define MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \
6288 (_MX6Q_PAD_CSI0_DAT11__GPIO_5_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
6289 #define MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \
6290 (_MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
6291 #define MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \
6292 (_MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6294 #define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \
6295 (_MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6296 #define MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \
6297 (_MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6298 #define MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \
6299 (_MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6300 #define MX6Q_PAD_CSI0_DAT12__UART4_TXD \
6301 (_MX6Q_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6302 #define MX6Q_PAD_CSI0_DAT12__UART4_RXD \
6303 (_MX6Q_PAD_CSI0_DAT12__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6304 #define MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \
6305 (_MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6306 #define MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \
6307 (_MX6Q_PAD_CSI0_DAT12__GPIO_5_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
6308 #define MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \
6309 (_MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
6310 #define MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \
6311 (_MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6313 #define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \
6314 (_MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6315 #define MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \
6316 (_MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6317 #define MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \
6318 (_MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6319 #define MX6Q_PAD_CSI0_DAT13__UART4_TXD \
6320 (_MX6Q_PAD_CSI0_DAT13__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6321 #define MX6Q_PAD_CSI0_DAT13__UART4_RXD \
6322 (_MX6Q_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6323 #define MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \
6324 (_MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6325 #define MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \
6326 (_MX6Q_PAD_CSI0_DAT13__GPIO_5_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
6327 #define MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \
6328 (_MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
6329 #define MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \
6330 (_MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6332 #define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \
6333 (_MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6334 #define MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \
6335 (_MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6336 #define MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \
6337 (_MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6338 #define MX6Q_PAD_CSI0_DAT14__UART5_TXD \
6339 (_MX6Q_PAD_CSI0_DAT14__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6340 #define MX6Q_PAD_CSI0_DAT14__UART5_RXD \
6341 (_MX6Q_PAD_CSI0_DAT14__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6342 #define MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \
6343 (_MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6344 #define MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \
6345 (_MX6Q_PAD_CSI0_DAT14__GPIO_6_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6346 #define MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \
6347 (_MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
6348 #define MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \
6349 (_MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6351 #define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \
6352 (_MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6353 #define MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \
6354 (_MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6355 #define MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \
6356 (_MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6357 #define MX6Q_PAD_CSI0_DAT15__UART5_TXD \
6358 (_MX6Q_PAD_CSI0_DAT15__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6359 #define MX6Q_PAD_CSI0_DAT15__UART5_RXD \
6360 (_MX6Q_PAD_CSI0_DAT15__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6361 #define MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \
6362 (_MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6363 #define MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \
6364 (_MX6Q_PAD_CSI0_DAT15__GPIO_6_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6365 #define MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \
6366 (_MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
6367 #define MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \
6368 (_MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6370 #define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \
6371 (_MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6372 #define MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \
6373 (_MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6374 #define MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \
6375 (_MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
6376 #define MX6Q_PAD_CSI0_DAT16__UART4_CTS \
6377 (_MX6Q_PAD_CSI0_DAT16__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6378 #define MX6Q_PAD_CSI0_DAT16__UART4_RTS \
6379 (_MX6Q_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6380 #define MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \
6381 (_MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6382 #define MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \
6383 (_MX6Q_PAD_CSI0_DAT16__GPIO_6_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6384 #define MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \
6385 (_MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
6386 #define MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \
6387 (_MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6389 #define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \
6390 (_MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6391 #define MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \
6392 (_MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6393 #define MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \
6394 (_MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
6395 #define MX6Q_PAD_CSI0_DAT17__UART4_CTS \
6396 (_MX6Q_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6397 #define MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \
6398 (_MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6399 #define MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \
6400 (_MX6Q_PAD_CSI0_DAT17__GPIO_6_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6401 #define MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \
6402 (_MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
6403 #define MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \
6404 (_MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6406 #define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \
6407 (_MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6408 #define MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \
6409 (_MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6410 #define MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \
6411 (_MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
6412 #define MX6Q_PAD_CSI0_DAT18__UART5_CTS \
6413 (_MX6Q_PAD_CSI0_DAT18__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6414 #define MX6Q_PAD_CSI0_DAT18__UART5_RTS \
6415 (_MX6Q_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6416 #define MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \
6417 (_MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6418 #define MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \
6419 (_MX6Q_PAD_CSI0_DAT18__GPIO_6_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6420 #define MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \
6421 (_MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
6422 #define MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \
6423 (_MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6425 #define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \
6426 (_MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6427 #define MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \
6428 (_MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6429 #define MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \
6430 (_MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
6431 #define MX6Q_PAD_CSI0_DAT19__UART5_CTS \
6432 (_MX6Q_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6433 #define MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \
6434 (_MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6435 #define MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \
6436 (_MX6Q_PAD_CSI0_DAT19__GPIO_6_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6437 #define MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \
6438 (_MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
6439 #define MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \
6440 (_MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6442 #define MX6Q_PAD_JTAG_TMS__SJC_TMS \
6443 (_MX6Q_PAD_JTAG_TMS__SJC_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
6445 #define MX6Q_PAD_JTAG_MOD__SJC_MOD \
6446 (_MX6Q_PAD_JTAG_MOD__SJC_MOD | MUX_PAD_CTRL(NO_PAD_CTRL))
6448 #define MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \
6449 (_MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB | MUX_PAD_CTRL(NO_PAD_CTRL))
6451 #define MX6Q_PAD_JTAG_TDI__SJC_TDI \
6452 (_MX6Q_PAD_JTAG_TDI__SJC_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
6454 #define MX6Q_PAD_JTAG_TCK__SJC_TCK \
6455 (_MX6Q_PAD_JTAG_TCK__SJC_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
6457 #define MX6Q_PAD_JTAG_TDO__SJC_TDO \
6458 (_MX6Q_PAD_JTAG_TDO__SJC_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
6460 #define MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \
6461 (_MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6463 #define MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \
6464 (_MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6466 #define MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \
6467 (_MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6469 #define MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \
6470 (_MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6472 #define MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \
6473 (_MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6475 #define MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \
6476 (_MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6478 #define MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \
6479 (_MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6481 #define MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \
6482 (_MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6484 #define MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \
6485 (_MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6487 #define MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \
6488 (_MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6490 #define MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \
6491 (_MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6493 #define MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \
6494 (_MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM | MUX_PAD_CTRL(NO_PAD_CTRL))
6496 #define MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \
6497 (_MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ | MUX_PAD_CTRL(NO_PAD_CTRL))
6499 #define MX6Q_PAD_POR_B__SRC_POR_B \
6500 (_MX6Q_PAD_POR_B__SRC_POR_B | MUX_PAD_CTRL(NO_PAD_CTRL))
6502 #define MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \
6503 (_MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6505 #define MX6Q_PAD_RESET_IN_B__SRC_RESET_B \
6506 (_MX6Q_PAD_RESET_IN_B__SRC_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
6508 #define MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \
6509 (_MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6511 #define MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \
6512 (_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
6514 #define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ \
6515 (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6516 #define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_100MHZ \
6517 (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6518 #define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_200MHZ \
6519 (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6520 #define MX6Q_PAD_SD3_DAT7__UART1_TXD \
6521 (_MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6522 #define MX6Q_PAD_SD3_DAT7__UART1_RXD \
6523 (_MX6Q_PAD_SD3_DAT7__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6524 #define MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \
6525 (_MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
6526 #define MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \
6527 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6528 #define MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \
6529 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6530 #define MX6Q_PAD_SD3_DAT7__GPIO_6_17 \
6531 (_MX6Q_PAD_SD3_DAT7__GPIO_6_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6532 #define MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \
6533 (_MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6534 #define MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \
6535 (_MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))
6537 #define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ \
6538 (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6539 #define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_100MHZ \
6540 (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6541 #define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_200MHZ \
6542 (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6543 #define MX6Q_PAD_SD3_DAT6__UART1_TXD \
6544 (_MX6Q_PAD_SD3_DAT6__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6545 #define MX6Q_PAD_SD3_DAT6__UART1_RXD \
6546 (_MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6547 #define MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \
6548 (_MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
6549 #define MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \
6550 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6551 #define MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \
6552 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6553 #define MX6Q_PAD_SD3_DAT6__GPIO_6_18 \
6554 (_MX6Q_PAD_SD3_DAT6__GPIO_6_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6555 #define MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \
6556 (_MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6557 #define MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \
6558 (_MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6560 #define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ \
6561 (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6562 #define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_100MHZ \
6563 (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6564 #define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_200MHZ \
6565 (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6566 #define MX6Q_PAD_SD3_DAT5__UART2_TXD \
6567 (_MX6Q_PAD_SD3_DAT5__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6568 #define MX6Q_PAD_SD3_DAT5__UART2_RXD \
6569 (_MX6Q_PAD_SD3_DAT5__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6570 #define MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \
6571 (_MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
6572 #define MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \
6573 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6574 #define MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \
6575 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6576 #define MX6Q_PAD_SD3_DAT5__GPIO_7_0 \
6577 (_MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6578 #define MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \
6579 (_MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6580 #define MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \
6581 (_MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6583 #define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ \
6584 (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6585 #define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_100MHZ \
6586 (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6587 #define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_200MHZ \
6588 (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6589 #define MX6Q_PAD_SD3_DAT4__UART2_TXD \
6590 (_MX6Q_PAD_SD3_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6591 #define MX6Q_PAD_SD3_DAT4__UART2_RXD \
6592 (_MX6Q_PAD_SD3_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6593 #define MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \
6594 (_MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
6595 #define MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \
6596 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6597 #define MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \
6598 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6599 #define MX6Q_PAD_SD3_DAT4__GPIO_7_1 \
6600 (_MX6Q_PAD_SD3_DAT4__GPIO_7_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6601 #define MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \
6602 (_MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6603 #define MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \
6604 (_MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6606 #define MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ \
6607 (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6608 #define MX6Q_PAD_SD3_CMD__USDHC3_CMD_100MHZ \
6609 (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6610 #define MX6Q_PAD_SD3_CMD__USDHC3_CMD_200MHZ \
6611 (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6612 #define MX6Q_PAD_SD3_CMD__UART2_CTS \
6613 (_MX6Q_PAD_SD3_CMD__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6614 #define MX6Q_PAD_SD3_CMD__CAN1_TXCAN \
6615 (_MX6Q_PAD_SD3_CMD__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
6616 #define MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \
6617 (_MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6618 #define MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \
6619 (_MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6620 #define MX6Q_PAD_SD3_CMD__GPIO_7_2 \
6621 (_MX6Q_PAD_SD3_CMD__GPIO_7_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6622 #define MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \
6623 (_MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6624 #define MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \
6625 (_MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6627 #define MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ \
6628 (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6629 #define MX6Q_PAD_SD3_CLK__USDHC3_CLK_100MHZ \
6630 (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6631 #define MX6Q_PAD_SD3_CLK__USDHC3_CLK_200MHZ \
6632 (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6633 #define MX6Q_PAD_SD3_CLK__UART2_CTS \
6634 (_MX6Q_PAD_SD3_CLK__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6635 #define MX6Q_PAD_SD3_CLK__UART2_RTS \
6636 (_MX6Q_PAD_SD3_CLK__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6637 #define MX6Q_PAD_SD3_CLK__CAN1_RXCAN \
6638 (_MX6Q_PAD_SD3_CLK__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
6639 #define MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \
6640 (_MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6641 #define MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \
6642 (_MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6643 #define MX6Q_PAD_SD3_CLK__GPIO_7_3 \
6644 (_MX6Q_PAD_SD3_CLK__GPIO_7_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6645 #define MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \
6646 (_MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6647 #define MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \
6648 (_MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6650 #define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ \
6651 (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6652 #define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_100MHZ \
6653 (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6654 #define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_200MHZ \
6655 (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6656 #define MX6Q_PAD_SD3_DAT0__UART1_CTS \
6657 (_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6658 #define MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \
6659 (_MX6Q_PAD_SD3_DAT0__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
6660 #define MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
6661 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6662 #define MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \
6663 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6664 #define MX6Q_PAD_SD3_DAT0__GPIO_7_4 \
6665 (_MX6Q_PAD_SD3_DAT0__GPIO_7_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6666 #define MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \
6667 (_MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6668 #define MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \
6669 (_MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6671 #define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ \
6672 (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6673 #define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_100MHZ \
6674 (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6675 #define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_200MHZ \
6676 (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6677 #define MX6Q_PAD_SD3_DAT1__UART1_CTS \
6678 (_MX6Q_PAD_SD3_DAT1__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6679 #define MX6Q_PAD_SD3_DAT1__UART1_RTS \
6680 (_MX6Q_PAD_SD3_DAT1__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6681 #define MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \
6682 (_MX6Q_PAD_SD3_DAT1__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
6683 #define MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \
6684 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6685 #define MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \
6686 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6687 #define MX6Q_PAD_SD3_DAT1__GPIO_7_5 \
6688 (_MX6Q_PAD_SD3_DAT1__GPIO_7_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6689 #define MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \
6690 (_MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6691 #define MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \
6692 (_MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6694 #define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ \
6695 (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6696 #define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_100MHZ \
6697 (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6698 #define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_200MHZ \
6699 (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6700 #define MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \
6701 (_MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
6702 #define MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \
6703 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6704 #define MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \
6705 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6706 #define MX6Q_PAD_SD3_DAT2__GPIO_7_6 \
6707 (_MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6708 #define MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \
6709 (_MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
6710 #define MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \
6711 (_MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6713 #define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ \
6714 (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6715 #define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_100MHZ \
6716 (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6717 #define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_200MHZ \
6718 (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6719 #define MX6Q_PAD_SD3_DAT3__UART3_CTS \
6720 (_MX6Q_PAD_SD3_DAT3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6721 #define MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \
6722 (_MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
6723 #define MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \
6724 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6725 #define MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \
6726 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6727 #define MX6Q_PAD_SD3_DAT3__GPIO_7_7 \
6728 (_MX6Q_PAD_SD3_DAT3__GPIO_7_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6729 #define MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \
6730 (_MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
6731 #define MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \
6732 (_MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6734 #define MX6Q_PAD_SD3_RST__USDHC3_RST \
6735 (_MX6Q_PAD_SD3_RST__USDHC3_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6736 #define MX6Q_PAD_SD3_RST__UART3_CTS \
6737 (_MX6Q_PAD_SD3_RST__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6738 #define MX6Q_PAD_SD3_RST__UART3_RTS \
6739 (_MX6Q_PAD_SD3_RST__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6740 #define MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \
6741 (_MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
6742 #define MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \
6743 (_MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6744 #define MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \
6745 (_MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6746 #define MX6Q_PAD_SD3_RST__GPIO_7_8 \
6747 (_MX6Q_PAD_SD3_RST__GPIO_7_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6748 #define MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \
6749 (_MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
6750 #define MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \
6751 (_MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6753 #define MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \
6754 (_MX6Q_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6755 #define MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \
6756 (_MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6757 #define MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \
6758 (_MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
6759 #define MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \
6760 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6761 #define MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \
6762 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6763 #define MX6Q_PAD_NANDF_CLE__GPIO_6_7 \
6764 (_MX6Q_PAD_NANDF_CLE__GPIO_6_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6765 #define MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \
6766 (_MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
6767 #define MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \
6768 (_MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6770 #define MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \
6771 (_MX6Q_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6772 #define MX6Q_PAD_NANDF_ALE__USDHC4_RST \
6773 (_MX6Q_PAD_NANDF_ALE__USDHC4_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6774 #define MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \
6775 (_MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6776 #define MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \
6777 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6778 #define MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \
6779 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6780 #define MX6Q_PAD_NANDF_ALE__GPIO_6_8 \
6781 (_MX6Q_PAD_NANDF_ALE__GPIO_6_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6782 #define MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \
6783 (_MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
6784 #define MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \
6785 (_MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6787 #define MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \
6788 (_MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6789 #define MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \
6790 (_MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6791 #define MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \
6792 (_MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6793 #define MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \
6794 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6795 #define MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \
6796 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6797 #define MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \
6798 (_MX6Q_PAD_NANDF_WP_B__GPIO_6_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6799 #define MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \
6800 (_MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
6801 #define MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \
6802 (_MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6804 #define MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \
6805 (_MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL0))
6806 #define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \
6807 (_MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6808 #define MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \
6809 (_MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6810 #define MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \
6811 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6812 #define MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \
6813 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6814 #define MX6Q_PAD_NANDF_RB0__GPIO_6_10 \
6815 (_MX6Q_PAD_NANDF_RB0__GPIO_6_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6816 #define MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \
6817 (_MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
6818 #define MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \
6819 (_MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6821 #define MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \
6822 (_MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6823 #define MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \
6824 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6825 #define MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \
6826 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6827 #define MX6Q_PAD_NANDF_CS0__GPIO_6_11 \
6828 (_MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6829 #define MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \
6830 (_MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6832 #define MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \
6833 (_MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6834 #define MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \
6835 (_MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6836 #define MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \
6837 (_MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6838 #define MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \
6839 (_MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6840 #define MX6Q_PAD_NANDF_CS1__GPIO_6_14 \
6841 (_MX6Q_PAD_NANDF_CS1__GPIO_6_14 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6842 #define MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \
6843 (_MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT | MUX_PAD_CTRL(NO_PAD_CTRL))
6845 #define MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \
6846 (_MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6847 #define MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \
6848 (_MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6849 #define MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \
6850 (_MX6Q_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
6851 #define MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \
6852 (_MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
6853 #define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \
6854 (_MX6Q_PAD_NANDF_CS2__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6855 #define MX6Q_PAD_NANDF_CS2__GPIO_6_15 \
6856 (_MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6857 #define MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \
6858 (_MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6860 #define MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \
6861 (_MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6862 #define MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \
6863 (_MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6864 #define MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \
6865 (_MX6Q_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
6866 #define MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \
6867 (_MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
6868 #define MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \
6869 (_MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6870 #define MX6Q_PAD_NANDF_CS3__GPIO_6_16 \
6871 (_MX6Q_PAD_NANDF_CS3__GPIO_6_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6872 #define MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \
6873 (_MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6874 #define MX6Q_PAD_NANDF_CS3__TPSMP_CLK \
6875 (_MX6Q_PAD_NANDF_CS3__TPSMP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6877 #define MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ \
6878 (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6879 #define MX6Q_PAD_SD4_CMD__USDHC4_CMD_100MHZ \
6880 (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6881 #define MX6Q_PAD_SD4_CMD__USDHC4_CMD_200MHZ \
6882 (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6883 #define MX6Q_PAD_SD4_CMD__RAWNAND_RDN \
6884 (_MX6Q_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6885 #define MX6Q_PAD_SD4_CMD__UART3_TXD \
6886 (_MX6Q_PAD_SD4_CMD__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6887 #define MX6Q_PAD_SD4_CMD__UART3_RXD \
6888 (_MX6Q_PAD_SD4_CMD__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6889 #define MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \
6890 (_MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6891 #define MX6Q_PAD_SD4_CMD__GPIO_7_9 \
6892 (_MX6Q_PAD_SD4_CMD__GPIO_7_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6893 #define MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \
6894 (_MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
6896 #define MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ \
6897 (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6898 #define MX6Q_PAD_SD4_CLK__USDHC4_CLK_100MHZ \
6899 (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6900 #define MX6Q_PAD_SD4_CLK__USDHC4_CLK_200MHZ \
6901 (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6902 #define MX6Q_PAD_SD4_CLK__RAWNAND_WRN \
6903 (_MX6Q_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6904 #define MX6Q_PAD_SD4_CLK__UART3_TXD \
6905 (_MX6Q_PAD_SD4_CLK__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6906 #define MX6Q_PAD_SD4_CLK__UART3_RXD \
6907 (_MX6Q_PAD_SD4_CLK__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6908 #define MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \
6909 (_MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6910 #define MX6Q_PAD_SD4_CLK__GPIO_7_10 \
6911 (_MX6Q_PAD_SD4_CLK__GPIO_7_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6913 #define MX6Q_PAD_NANDF_D0__RAWNAND_D0 \
6914 (_MX6Q_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6915 #define MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \
6916 (_MX6Q_PAD_NANDF_D0__USDHC1_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6917 #define MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \
6918 (_MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6919 #define MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \
6920 (_MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6921 #define MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \
6922 (_MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6923 #define MX6Q_PAD_NANDF_D0__GPIO_2_0 \
6924 (_MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6925 #define MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \
6926 (_MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6927 #define MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \
6928 (_MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6930 #define MX6Q_PAD_NANDF_D1__RAWNAND_D1 \
6931 (_MX6Q_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6932 #define MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \
6933 (_MX6Q_PAD_NANDF_D1__USDHC1_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6934 #define MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \
6935 (_MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6936 #define MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \
6937 (_MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6938 #define MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \
6939 (_MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6940 #define MX6Q_PAD_NANDF_D1__GPIO_2_1 \
6941 (_MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6942 #define MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \
6943 (_MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6944 #define MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \
6945 (_MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6947 #define MX6Q_PAD_NANDF_D2__RAWNAND_D2 \
6948 (_MX6Q_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6949 #define MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \
6950 (_MX6Q_PAD_NANDF_D2__USDHC1_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6951 #define MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \
6952 (_MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6953 #define MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \
6954 (_MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6955 #define MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \
6956 (_MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6957 #define MX6Q_PAD_NANDF_D2__GPIO_2_2 \
6958 (_MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6959 #define MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \
6960 (_MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6961 #define MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \
6962 (_MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6964 #define MX6Q_PAD_NANDF_D3__RAWNAND_D3 \
6965 (_MX6Q_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6966 #define MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \
6967 (_MX6Q_PAD_NANDF_D3__USDHC1_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6968 #define MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \
6969 (_MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6970 #define MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \
6971 (_MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6972 #define MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \
6973 (_MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6974 #define MX6Q_PAD_NANDF_D3__GPIO_2_3 \
6975 (_MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6976 #define MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \
6977 (_MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6978 #define MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \
6979 (_MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6981 #define MX6Q_PAD_NANDF_D4__RAWNAND_D4 \
6982 (_MX6Q_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6983 #define MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \
6984 (_MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6985 #define MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \
6986 (_MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6987 #define MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \
6988 (_MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
6989 #define MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \
6990 (_MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
6991 #define MX6Q_PAD_NANDF_D4__GPIO_2_4 \
6992 (_MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6993 #define MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \
6994 (_MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6995 #define MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \
6996 (_MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6998 #define MX6Q_PAD_NANDF_D5__RAWNAND_D5 \
6999 (_MX6Q_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
7000 #define MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \
7001 (_MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7002 #define MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \
7003 (_MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
7004 #define MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \
7005 (_MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
7006 #define MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \
7007 (_MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
7008 #define MX6Q_PAD_NANDF_D5__GPIO_2_5 \
7009 (_MX6Q_PAD_NANDF_D5__GPIO_2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
7010 #define MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \
7011 (_MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
7012 #define MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \
7013 (_MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
7015 #define MX6Q_PAD_NANDF_D6__RAWNAND_D6 \
7016 (_MX6Q_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
7017 #define MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \
7018 (_MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7019 #define MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \
7020 (_MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
7021 #define MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \
7022 (_MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
7023 #define MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \
7024 (_MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
7025 #define MX6Q_PAD_NANDF_D6__GPIO_2_6 \
7026 (_MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
7027 #define MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \
7028 (_MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
7029 #define MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \
7030 (_MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
7032 #define MX6Q_PAD_NANDF_D7__RAWNAND_D7 \
7033 (_MX6Q_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
7034 #define MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \
7035 (_MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7036 #define MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \
7037 (_MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
7038 #define MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \
7039 (_MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
7040 #define MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \
7041 (_MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
7042 #define MX6Q_PAD_NANDF_D7__GPIO_2_7 \
7043 (_MX6Q_PAD_NANDF_D7__GPIO_2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
7044 #define MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \
7045 (_MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
7046 #define MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \
7047 (_MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
7049 #define MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \
7050 (_MX6Q_PAD_SD4_DAT0__RAWNAND_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
7051 #define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ \
7052 (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7053 #define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_100MHZ \
7054 (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7055 #define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_200MHZ \
7056 (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7057 #define MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \
7058 (_MX6Q_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL1))
7059 #define MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \
7060 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
7061 #define MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \
7062 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
7063 #define MX6Q_PAD_SD4_DAT0__GPIO_2_8 \
7064 (_MX6Q_PAD_SD4_DAT0__GPIO_2_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
7065 #define MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \
7066 (_MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
7067 #define MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \
7068 (_MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
7070 #define MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \
7071 (_MX6Q_PAD_SD4_DAT1__RAWNAND_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
7072 #define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ \
7073 (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7074 #define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_100MHZ \
7075 (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7076 #define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_200MHZ \
7077 (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7078 #define MX6Q_PAD_SD4_DAT1__PWM3_PWMO \
7079 (_MX6Q_PAD_SD4_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7080 #define MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \
7081 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
7082 #define MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \
7083 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
7084 #define MX6Q_PAD_SD4_DAT1__GPIO_2_9 \
7085 (_MX6Q_PAD_SD4_DAT1__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
7086 #define MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \
7087 (_MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
7088 #define MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \
7089 (_MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
7091 #define MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \
7092 (_MX6Q_PAD_SD4_DAT2__RAWNAND_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7093 #define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ \
7094 (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7095 #define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_100MHZ \
7096 (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7097 #define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_200MHZ \
7098 (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7099 #define MX6Q_PAD_SD4_DAT2__PWM4_PWMO \
7100 (_MX6Q_PAD_SD4_DAT2__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7101 #define MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \
7102 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
7103 #define MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \
7104 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
7105 #define MX6Q_PAD_SD4_DAT2__GPIO_2_10 \
7106 (_MX6Q_PAD_SD4_DAT2__GPIO_2_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7107 #define MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \
7108 (_MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7109 #define MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \
7110 (_MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7112 #define MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \
7113 (_MX6Q_PAD_SD4_DAT3__RAWNAND_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7114 #define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ \
7115 (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7116 #define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_100MHZ \
7117 (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7118 #define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_200MHZ \
7119 (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7120 #define MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \
7121 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
7122 #define MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \
7123 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
7124 #define MX6Q_PAD_SD4_DAT3__GPIO_2_11 \
7125 (_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7126 #define MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \
7127 (_MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7128 #define MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \
7129 (_MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7131 #define MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \
7132 (_MX6Q_PAD_SD4_DAT4__RAWNAND_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
7133 #define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ \
7134 (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7135 #define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_100MHZ \
7136 (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7137 #define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_200MHZ \
7138 (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7139 #define MX6Q_PAD_SD4_DAT4__UART2_TXD \
7140 (_MX6Q_PAD_SD4_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7141 #define MX6Q_PAD_SD4_DAT4__UART2_RXD \
7142 (_MX6Q_PAD_SD4_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7143 #define MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \
7144 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
7145 #define MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \
7146 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
7147 #define MX6Q_PAD_SD4_DAT4__GPIO_2_12 \
7148 (_MX6Q_PAD_SD4_DAT4__GPIO_2_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
7149 #define MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \
7150 (_MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
7151 #define MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \
7152 (_MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
7154 #define MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \
7155 (_MX6Q_PAD_SD4_DAT5__RAWNAND_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
7156 #define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ \
7157 (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7158 #define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_100MHZ \
7159 (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7160 #define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_200MHZ \
7161 (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7162 #define MX6Q_PAD_SD4_DAT5__UART2_CTS \
7163 (_MX6Q_PAD_SD4_DAT5__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7164 #define MX6Q_PAD_SD4_DAT5__UART2_RTS \
7165 (_MX6Q_PAD_SD4_DAT5__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7166 #define MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \
7167 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
7168 #define MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \
7169 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
7170 #define MX6Q_PAD_SD4_DAT5__GPIO_2_13 \
7171 (_MX6Q_PAD_SD4_DAT5__GPIO_2_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
7172 #define MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \
7173 (_MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
7174 #define MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \
7175 (_MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
7177 #define MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \
7178 (_MX6Q_PAD_SD4_DAT6__RAWNAND_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
7179 #define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ \
7180 (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7181 #define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_100MHZ \
7182 (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7183 #define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_200MHZ \
7184 (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7185 #define MX6Q_PAD_SD4_DAT6__UART2_CTS \
7186 (_MX6Q_PAD_SD4_DAT6__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7187 #define MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \
7188 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
7189 #define MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \
7190 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
7191 #define MX6Q_PAD_SD4_DAT6__GPIO_2_14 \
7192 (_MX6Q_PAD_SD4_DAT6__GPIO_2_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
7193 #define MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \
7194 (_MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
7195 #define MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \
7196 (_MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
7198 #define MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \
7199 (_MX6Q_PAD_SD4_DAT7__RAWNAND_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
7200 #define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ \
7201 (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7202 #define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_100MHZ \
7203 (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7204 #define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_200MHZ \
7205 (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7206 #define MX6Q_PAD_SD4_DAT7__UART2_TXD \
7207 (_MX6Q_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7208 #define MX6Q_PAD_SD4_DAT7__UART2_RXD \
7209 (_MX6Q_PAD_SD4_DAT7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7210 #define MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \
7211 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
7212 #define MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \
7213 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
7214 #define MX6Q_PAD_SD4_DAT7__GPIO_2_15 \
7215 (_MX6Q_PAD_SD4_DAT7__GPIO_2_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
7216 #define MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \
7217 (_MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
7218 #define MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \
7219 (_MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
7221 #define MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \
7222 (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7223 #define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \
7224 (_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
7225 #define MX6Q_PAD_SD1_DAT1__PWM3_PWMO \
7226 (_MX6Q_PAD_SD1_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7227 #define MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \
7228 (_MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
7229 #define MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \
7230 (_MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
7231 #define MX6Q_PAD_SD1_DAT1__GPIO_1_17 \
7232 (_MX6Q_PAD_SD1_DAT1__GPIO_1_17 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
7233 #define MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \
7234 (_MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
7235 #define MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \
7236 (_MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
7238 #define MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \
7239 (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7240 #define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \
7241 (_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
7242 #define MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \
7243 (_MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS | MUX_PAD_CTRL(NO_PAD_CTRL))
7244 #define MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \
7245 (_MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7246 #define MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \
7247 (_MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
7248 #define MX6Q_PAD_SD1_DAT0__GPIO_1_16 \
7249 (_MX6Q_PAD_SD1_DAT0__GPIO_1_16 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
7250 #define MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \
7251 (_MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7252 #define MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \
7253 (_MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
7255 #define MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \
7256 (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7257 #define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \
7258 (_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
7259 #define MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \
7260 (_MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
7261 #define MX6Q_PAD_SD1_DAT3__PWM1_PWMO \
7262 (_MX6Q_PAD_SD1_DAT3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7263 #define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \
7264 (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
7265 #define MX6Q_PAD_SD1_DAT3__GPIO_1_21 \
7266 (_MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
7267 #define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \
7268 (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
7269 #define MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \
7270 (_MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
7272 #define MX6Q_PAD_SD1_CMD__USDHC1_CMD \
7273 (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7274 #define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \
7275 (_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
7276 #define MX6Q_PAD_SD1_CMD__PWM4_PWMO \
7277 (_MX6Q_PAD_SD1_CMD__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7278 #define MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \
7279 (_MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7280 #define MX6Q_PAD_SD1_CMD__GPIO_1_18 \
7281 (_MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
7282 #define MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \
7283 (_MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
7285 #define MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \
7286 (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7287 #define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \
7288 (_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7289 #define MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \
7290 (_MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
7291 #define MX6Q_PAD_SD1_DAT2__PWM2_PWMO \
7292 (_MX6Q_PAD_SD1_DAT2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7293 #define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \
7294 (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
7295 #define MX6Q_PAD_SD1_DAT2__GPIO_1_19 \
7296 (_MX6Q_PAD_SD1_DAT2__GPIO_1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
7297 #define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \
7298 (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
7299 #define MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \
7300 (_MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
7302 #define MX6Q_PAD_SD1_CLK__USDHC1_CLK \
7303 (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7304 #define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \
7305 (_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
7306 #define MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \
7307 (_MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
7308 #define MX6Q_PAD_SD1_CLK__GPT_CLKIN \
7309 (_MX6Q_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL))
7310 #define MX6Q_PAD_SD1_CLK__GPIO_1_20 \
7311 (_MX6Q_PAD_SD1_CLK__GPIO_1_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
7312 #define MX6Q_PAD_SD1_CLK__PHY_DTB_0 \
7313 (_MX6Q_PAD_SD1_CLK__PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
7314 #define MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \
7315 (_MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
7317 #define MX6Q_PAD_SD2_CLK__USDHC2_CLK \
7318 (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7319 #define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \
7320 (_MX6Q_PAD_SD2_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
7321 #define MX6Q_PAD_SD2_CLK__KPP_COL_5 \
7322 (_MX6Q_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
7323 #define MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \
7324 (_MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
7325 #define MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \
7326 (_MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
7327 #define MX6Q_PAD_SD2_CLK__GPIO_1_10 \
7328 (_MX6Q_PAD_SD2_CLK__GPIO_1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7329 #define MX6Q_PAD_SD2_CLK__PHY_DTB_1 \
7330 (_MX6Q_PAD_SD2_CLK__PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7331 #define MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \
7332 (_MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7334 #define MX6Q_PAD_SD2_CMD__USDHC2_CMD \
7335 (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7336 #define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \
7337 (_MX6Q_PAD_SD2_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
7338 #define MX6Q_PAD_SD2_CMD__KPP_ROW_5 \
7339 (_MX6Q_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
7340 #define MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \
7341 (_MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
7342 #define MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \
7343 (_MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7344 #define MX6Q_PAD_SD2_CMD__GPIO_1_11 \
7345 (_MX6Q_PAD_SD2_CMD__GPIO_1_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7347 #define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \
7348 (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7349 #define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \
7350 (_MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
7351 #define MX6Q_PAD_SD2_DAT3__KPP_COL_6 \
7352 (_MX6Q_PAD_SD2_DAT3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
7353 #define MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \
7354 (_MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
7355 #define MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \
7356 (_MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7357 #define MX6Q_PAD_SD2_DAT3__GPIO_1_12 \
7358 (_MX6Q_PAD_SD2_DAT3__GPIO_1_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
7359 #define MX6Q_PAD_SD2_DAT3__SJC_DONE \
7360 (_MX6Q_PAD_SD2_DAT3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL))
7361 #define MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \
7362 (_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
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