2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 * Auto Generate file, please don't edit it
22 #ifndef __MACH_IOMUX_MX6Q_H__
23 #define __MACH_IOMUX_MX6Q_H__
25 #include <mach/iomux-v3.h>
28 * various IOMUX alternate output functions (1-7)
30 typedef enum iomux_config {
39 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
42 #define NON_MUX_I 0x3FF
43 #define NON_PAD_I 0x7FF
44 #define MX6Q_CCM_CLK0_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
45 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
46 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
48 #define MX6Q_HIGH_DRV (PAD_CTL_DSE_120ohm)
49 #define MX6Q_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
50 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
51 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
53 #define MX6Q_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
54 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
55 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
57 #define MX6Q_USDHC_PAD_CTRL_100MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \
58 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \
59 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
61 #define MX6Q_USDHC_PAD_CTRL_200MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \
62 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
63 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
65 #define MX6Q_ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
66 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
67 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
69 #define MX6Q_DISP_PAD_CLT MX6Q_HIGH_DRV
70 #define MX6Q_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
71 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_40ohm | \
72 PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_SPEED_MED)
74 #define MX6Q_ESAI_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
75 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
77 #define MX6Q_GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
78 #define MX6Q_GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
79 #define MX6Q_GPMI_PAD_CTRL2 (MX6Q_GPMI_PAD_CTRL0 | MX6Q_GPMI_PAD_CTRL1)
81 #define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
82 IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
83 #define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
84 IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0)
85 #define _MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \
86 IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0)
87 #define _MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \
88 IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0)
89 #define _MX6Q_PAD_SD2_DAT1__KPP_COL_7 \
90 IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0)
91 #define _MX6Q_PAD_SD2_DAT1__GPIO_1_14 \
92 IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0)
93 #define _MX6Q_PAD_SD2_DAT1__CCM_WAIT \
94 IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0)
95 #define _MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \
96 IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0)
98 #define _MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \
99 IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0)
100 #define _MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \
101 IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0)
102 #define _MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \
103 IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0)
104 #define _MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \
105 IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0)
106 #define _MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \
107 IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0)
108 #define _MX6Q_PAD_SD2_DAT2__GPIO_1_13 \
109 IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0)
110 #define _MX6Q_PAD_SD2_DAT2__CCM_STOP \
111 IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0)
112 #define _MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \
113 IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0)
115 #define _MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \
116 IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0)
117 #define _MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \
118 IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0)
119 #define _MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
120 IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0)
121 #define _MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \
122 IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0)
123 #define _MX6Q_PAD_SD2_DAT0__GPIO_1_15 \
124 IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0)
125 #define _MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \
126 IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0)
127 #define _MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \
128 IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0)
130 #define _MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \
131 IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0)
132 #define _MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \
133 IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0)
134 #define _MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \
135 IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0)
136 #define _MX6Q_PAD_RGMII_TXC__GPIO_6_19 \
137 IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0)
138 #define _MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \
139 IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0)
140 #define _MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \
141 IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0)
143 #define _MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \
144 IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0)
145 #define _MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \
146 IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0)
147 #define _MX6Q_PAD_RGMII_TD0__GPIO_6_20 \
148 IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0)
149 #define _MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \
150 IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0)
152 #define _MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \
153 IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0)
154 #define _MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \
155 IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0)
156 #define _MX6Q_PAD_RGMII_TD1__GPIO_6_21 \
157 IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0)
158 #define _MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \
159 IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0)
160 #define _MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \
161 IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0)
163 #define _MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \
164 IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0)
165 #define _MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \
166 IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0)
167 #define _MX6Q_PAD_RGMII_TD2__GPIO_6_22 \
168 IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0)
169 #define _MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \
170 IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0)
171 #define _MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \
172 IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0)
174 #define _MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \
175 IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0)
176 #define _MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \
177 IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0)
178 #define _MX6Q_PAD_RGMII_TD3__GPIO_6_23 \
179 IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0)
180 #define _MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \
181 IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0)
183 #define _MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \
184 IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0)
185 #define _MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \
186 IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0)
187 #define _MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \
188 IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0)
189 #define _MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \
190 IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0)
192 #define _MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \
193 IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0)
194 #define _MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \
195 IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0)
196 #define _MX6Q_PAD_RGMII_RD0__GPIO_6_25 \
197 IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0)
198 #define _MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \
199 IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0)
201 #define _MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \
202 IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0)
203 #define _MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \
204 IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0)
205 #define _MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \
206 IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0)
207 #define _MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \
208 IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0)
209 #define _MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \
210 IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0)
212 #define _MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \
213 IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0)
214 #define _MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \
215 IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0)
216 #define _MX6Q_PAD_RGMII_RD1__GPIO_6_27 \
217 IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0)
218 #define _MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \
219 IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0)
220 #define _MX6Q_PAD_RGMII_RD1__SJC_FAIL \
221 IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0)
223 #define _MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \
224 IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0)
225 #define _MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \
226 IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0)
227 #define _MX6Q_PAD_RGMII_RD2__GPIO_6_28 \
228 IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0)
229 #define _MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \
230 IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0)
232 #define _MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \
233 IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0)
234 #define _MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \
235 IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0)
236 #define _MX6Q_PAD_RGMII_RD3__GPIO_6_29 \
237 IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0)
238 #define _MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \
239 IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0)
241 #define _MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \
242 IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0)
243 #define _MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \
244 IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0)
245 #define _MX6Q_PAD_RGMII_RXC__GPIO_6_30 \
246 IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0)
247 #define _MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \
248 IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0)
250 #define _MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \
251 IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0)
252 #define _MX6Q_PAD_EIM_A25__ECSPI4_SS1 \
253 IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0)
254 #define _MX6Q_PAD_EIM_A25__ECSPI2_RDY \
255 IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0)
256 #define _MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \
257 IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0)
258 #define _MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \
259 IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0)
260 #define _MX6Q_PAD_EIM_A25__GPIO_5_2 \
261 IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0)
262 #define _MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \
263 IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0)
264 #define _MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \
265 IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0)
267 #define _MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \
268 IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0)
269 #define _MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \
270 IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0)
271 #define _MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \
272 IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0)
273 #define _MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \
274 IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0)
275 #define _MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \
276 IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0)
277 #define _MX6Q_PAD_EIM_EB2__GPIO_2_30 \
278 IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0)
279 #define _MX6Q_PAD_EIM_EB2__I2C2_SCL \
280 IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0)
281 #define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \
282 IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0)
284 #define _MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \
285 IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0)
286 #define _MX6Q_PAD_EIM_D16__ECSPI1_SCLK \
287 IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0)
288 #define _MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \
289 IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0)
290 #define _MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \
291 IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0)
292 #define _MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \
293 IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0)
294 #define _MX6Q_PAD_EIM_D16__GPIO_3_16 \
295 IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0)
296 #define _MX6Q_PAD_EIM_D16__I2C2_SDA \
297 IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0)
299 #define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \
300 IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0)
301 #define _MX6Q_PAD_EIM_D17__ECSPI1_MISO \
302 IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0)
303 #define _MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \
304 IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0)
305 #define _MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \
306 IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0)
307 #define _MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \
308 IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0)
309 #define _MX6Q_PAD_EIM_D17__GPIO_3_17 \
310 IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0)
311 #define _MX6Q_PAD_EIM_D17__I2C3_SCL \
312 IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0)
313 #define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \
314 IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0)
316 #define _MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \
317 IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0)
318 #define _MX6Q_PAD_EIM_D18__ECSPI1_MOSI \
319 IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0)
320 #define _MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \
321 IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0)
322 #define _MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \
323 IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0)
324 #define _MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \
325 IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0)
326 #define _MX6Q_PAD_EIM_D18__GPIO_3_18 \
327 IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0)
328 #define _MX6Q_PAD_EIM_D18__I2C3_SDA \
329 IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0)
330 #define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \
331 IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0)
333 #define _MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \
334 IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0)
335 #define _MX6Q_PAD_EIM_D19__ECSPI1_SS1 \
336 IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0)
337 #define _MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \
338 IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0)
339 #define _MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \
340 IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0)
341 #define _MX6Q_PAD_EIM_D19__UART1_CTS \
342 IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0)
343 #define _MX6Q_PAD_EIM_D19__GPIO_3_19 \
344 IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0)
345 #define _MX6Q_PAD_EIM_D19__EPIT1_EPITO \
346 IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0)
347 #define _MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \
348 IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0)
350 #define _MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \
351 IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0)
352 #define _MX6Q_PAD_EIM_D20__ECSPI4_SS0 \
353 IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0)
354 #define _MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \
355 IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0)
356 #define _MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \
357 IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0)
358 #define _MX6Q_PAD_EIM_D20__UART1_CTS \
359 IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0)
360 #define _MX6Q_PAD_EIM_D20__UART1_RTS \
361 IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0)
362 #define _MX6Q_PAD_EIM_D20__GPIO_3_20 \
363 IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0)
364 #define _MX6Q_PAD_EIM_D20__EPIT2_EPITO \
365 IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0)
367 #define _MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \
368 IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0)
369 #define _MX6Q_PAD_EIM_D21__ECSPI4_SCLK \
370 IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0)
371 #define _MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \
372 IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0)
373 #define _MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \
374 IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0)
375 #define _MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \
376 IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0)
377 #define _MX6Q_PAD_EIM_D21__GPIO_3_21 \
378 IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0)
379 #define _MX6Q_PAD_EIM_D21__I2C1_SCL \
380 IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0)
381 #define _MX6Q_PAD_EIM_D21__SPDIF_IN1 \
382 IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0)
384 #define _MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \
385 IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0)
386 #define _MX6Q_PAD_EIM_D22__ECSPI4_MISO \
387 IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0)
388 #define _MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \
389 IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0)
390 #define _MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \
391 IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0)
392 #define _MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \
393 IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0)
394 #define _MX6Q_PAD_EIM_D22__GPIO_3_22 \
395 IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0)
396 #define _MX6Q_PAD_EIM_D22__SPDIF_OUT1 \
397 IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0)
398 #define _MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \
399 IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0)
401 #define _MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \
402 IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0)
403 #define _MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \
404 IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0)
405 #define _MX6Q_PAD_EIM_D23__UART3_CTS \
406 IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0)
407 #define _MX6Q_PAD_EIM_D23__UART1_DCD \
408 IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0)
409 #define _MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \
410 IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0)
411 #define _MX6Q_PAD_EIM_D23__GPIO_3_23 \
412 IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0)
413 #define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \
414 IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0)
415 #define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \
416 IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0)
418 #define _MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \
419 IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0)
420 #define _MX6Q_PAD_EIM_EB3__ECSPI4_RDY \
421 IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0)
422 #define _MX6Q_PAD_EIM_EB3__UART3_CTS \
423 IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0)
424 #define _MX6Q_PAD_EIM_EB3__UART3_RTS \
425 IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0)
426 #define _MX6Q_PAD_EIM_EB3__UART1_RI \
427 IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0)
428 #define _MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \
429 IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0)
430 #define _MX6Q_PAD_EIM_EB3__GPIO_2_31 \
431 IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0)
432 #define _MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \
433 IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0)
434 #define _MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \
435 IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0)
437 #define _MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \
438 IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0)
439 #define _MX6Q_PAD_EIM_D24__ECSPI4_SS2 \
440 IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0)
441 #define _MX6Q_PAD_EIM_D24__UART3_TXD \
442 IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0)
443 #define _MX6Q_PAD_EIM_D24__UART3_RXD \
444 IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0)
445 #define _MX6Q_PAD_EIM_D24__ECSPI1_SS2 \
446 IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0)
447 #define _MX6Q_PAD_EIM_D24__ECSPI2_SS2 \
448 IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0)
449 #define _MX6Q_PAD_EIM_D24__GPIO_3_24 \
450 IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0)
451 #define _MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \
452 IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0)
453 #define _MX6Q_PAD_EIM_D24__UART1_DTR \
454 IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0)
456 #define _MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \
457 IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0)
458 #define _MX6Q_PAD_EIM_D25__ECSPI4_SS3 \
459 IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0)
460 #define _MX6Q_PAD_EIM_D25__UART3_TXD \
461 IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0)
462 #define _MX6Q_PAD_EIM_D25__UART3_RXD \
463 IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0)
464 #define _MX6Q_PAD_EIM_D25__ECSPI1_SS3 \
465 IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0)
466 #define _MX6Q_PAD_EIM_D25__ECSPI2_SS3 \
467 IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0)
468 #define _MX6Q_PAD_EIM_D25__GPIO_3_25 \
469 IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0)
470 #define _MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \
471 IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0)
472 #define _MX6Q_PAD_EIM_D25__UART1_DSR \
473 IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0)
475 #define _MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \
476 IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0)
477 #define _MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \
478 IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0)
479 #define _MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \
480 IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0)
481 #define _MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \
482 IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0)
483 #define _MX6Q_PAD_EIM_D26__UART2_TXD \
484 IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0)
485 #define _MX6Q_PAD_EIM_D26__UART2_RXD \
486 IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0)
487 #define _MX6Q_PAD_EIM_D26__GPIO_3_26 \
488 IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0)
489 #define _MX6Q_PAD_EIM_D26__IPU1_SISG_2 \
490 IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0)
491 #define _MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \
492 IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0)
494 #define _MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \
495 IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0)
496 #define _MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \
497 IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0)
498 #define _MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \
499 IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0)
500 #define _MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \
501 IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0)
502 #define _MX6Q_PAD_EIM_D27__UART2_TXD \
503 IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0)
504 #define _MX6Q_PAD_EIM_D27__UART2_RXD \
505 IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0)
506 #define _MX6Q_PAD_EIM_D27__GPIO_3_27 \
507 IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0)
508 #define _MX6Q_PAD_EIM_D27__IPU1_SISG_3 \
509 IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0)
510 #define _MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \
511 IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0)
513 #define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \
514 IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0)
515 #define _MX6Q_PAD_EIM_D28__I2C1_SDA \
516 IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0)
517 #define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI \
518 IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0)
519 #define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \
520 IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0)
521 #define _MX6Q_PAD_EIM_D28__UART2_CTS \
522 IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0)
523 #define _MX6Q_PAD_EIM_D28__GPIO_3_28 \
524 IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0)
525 #define _MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \
526 IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0)
527 #define _MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \
528 IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0)
530 #define _MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \
531 IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0)
532 #define _MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \
533 IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0)
534 #define _MX6Q_PAD_EIM_D29__ECSPI4_SS0 \
535 IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0)
536 #define _MX6Q_PAD_EIM_D29__UART2_CTS \
537 IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0)
538 #define _MX6Q_PAD_EIM_D29__UART2_RTS \
539 IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0)
540 #define _MX6Q_PAD_EIM_D29__GPIO_3_29 \
541 IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0)
542 #define _MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \
543 IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0)
544 #define _MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \
545 IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0)
547 #define _MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \
548 IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0)
549 #define _MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
550 IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0)
551 #define _MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \
552 IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0)
553 #define _MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \
554 IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0)
555 #define _MX6Q_PAD_EIM_D30__UART3_CTS \
556 IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0)
557 #define _MX6Q_PAD_EIM_D30__GPIO_3_30 \
558 IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0)
559 #define _MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \
560 IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0)
561 #define _MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \
562 IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0)
564 #define _MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \
565 IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0)
566 #define _MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
567 IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0)
568 #define _MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \
569 IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0)
570 #define _MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \
571 IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0)
572 #define _MX6Q_PAD_EIM_D31__UART3_CTS \
573 IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0)
574 #define _MX6Q_PAD_EIM_D31__UART3_RTS \
575 IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0)
576 #define _MX6Q_PAD_EIM_D31__GPIO_3_31 \
577 IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0)
578 #define _MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \
579 IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0)
580 #define _MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \
581 IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0)
583 #define _MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \
584 IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0)
585 #define _MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \
586 IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0)
587 #define _MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \
588 IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0)
589 #define _MX6Q_PAD_EIM_A24__IPU2_SISG_2 \
590 IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0)
591 #define _MX6Q_PAD_EIM_A24__IPU1_SISG_2 \
592 IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0)
593 #define _MX6Q_PAD_EIM_A24__GPIO_5_4 \
594 IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0)
595 #define _MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \
596 IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0)
597 #define _MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \
598 IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0)
600 #define _MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \
601 IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0)
602 #define _MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \
603 IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0)
604 #define _MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \
605 IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0)
606 #define _MX6Q_PAD_EIM_A23__IPU2_SISG_3 \
607 IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0)
608 #define _MX6Q_PAD_EIM_A23__IPU1_SISG_3 \
609 IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0)
610 #define _MX6Q_PAD_EIM_A23__GPIO_6_6 \
611 IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0)
612 #define _MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \
613 IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0)
614 #define _MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \
615 IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0)
617 #define _MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \
618 IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0)
619 #define _MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \
620 IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0)
621 #define _MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \
622 IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0)
623 #define _MX6Q_PAD_EIM_A22__GPIO_2_16 \
624 IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0)
625 #define _MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \
626 IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0)
627 #define _MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \
628 IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0)
630 #define _MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \
631 IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0)
632 #define _MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \
633 IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0)
634 #define _MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \
635 IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0)
636 #define _MX6Q_PAD_EIM_A21__RESERVED_RESERVED \
637 IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0)
638 #define _MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \
639 IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0)
640 #define _MX6Q_PAD_EIM_A21__GPIO_2_17 \
641 IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0)
642 #define _MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \
643 IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0)
644 #define _MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \
645 IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0)
647 #define _MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \
648 IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0)
649 #define _MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \
650 IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0)
651 #define _MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \
652 IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0)
653 #define _MX6Q_PAD_EIM_A20__RESERVED_RESERVED \
654 IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0)
655 #define _MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \
656 IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0)
657 #define _MX6Q_PAD_EIM_A20__GPIO_2_18 \
658 IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0)
659 #define _MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \
660 IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0)
661 #define _MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \
662 IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0)
664 #define _MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \
665 IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0)
666 #define _MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \
667 IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0)
668 #define _MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \
669 IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0)
670 #define _MX6Q_PAD_EIM_A19__RESERVED_RESERVED \
671 IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0)
672 #define _MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \
673 IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0)
674 #define _MX6Q_PAD_EIM_A19__GPIO_2_19 \
675 IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0)
676 #define _MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \
677 IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0)
678 #define _MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \
679 IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0)
681 #define _MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \
682 IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0)
683 #define _MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \
684 IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0)
685 #define _MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \
686 IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0)
687 #define _MX6Q_PAD_EIM_A18__RESERVED_RESERVED \
688 IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0)
689 #define _MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \
690 IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0)
691 #define _MX6Q_PAD_EIM_A18__GPIO_2_20 \
692 IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0)
693 #define _MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \
694 IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0)
695 #define _MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \
696 IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0)
698 #define _MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \
699 IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0)
700 #define _MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \
701 IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0)
702 #define _MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \
703 IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0)
704 #define _MX6Q_PAD_EIM_A17__RESERVED_RESERVED \
705 IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0)
706 #define _MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \
707 IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0)
708 #define _MX6Q_PAD_EIM_A17__GPIO_2_21 \
709 IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0)
710 #define _MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \
711 IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0)
712 #define _MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \
713 IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0)
715 #define _MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \
716 IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0)
717 #define _MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \
718 IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0)
719 #define _MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \
720 IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0)
721 #define _MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \
722 IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0)
723 #define _MX6Q_PAD_EIM_A16__GPIO_2_22 \
724 IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0)
725 #define _MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \
726 IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0)
727 #define _MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \
728 IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0)
730 #define _MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \
731 IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0)
732 #define _MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \
733 IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0)
734 #define _MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \
735 IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0)
736 #define _MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \
737 IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0)
738 #define _MX6Q_PAD_EIM_CS0__GPIO_2_23 \
739 IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0)
740 #define _MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \
741 IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0)
743 #define _MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \
744 IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0)
745 #define _MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \
746 IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0)
747 #define _MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \
748 IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0)
749 #define _MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \
750 IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0)
751 #define _MX6Q_PAD_EIM_CS1__GPIO_2_24 \
752 IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0)
753 #define _MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \
754 IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0)
756 #define _MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \
757 IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0)
758 #define _MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \
759 IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0)
760 #define _MX6Q_PAD_EIM_OE__ECSPI2_MISO \
761 IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0)
762 #define _MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \
763 IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0)
764 #define _MX6Q_PAD_EIM_OE__GPIO_2_25 \
765 IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0)
766 #define _MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \
767 IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0)
769 #define _MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \
770 IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0)
771 #define _MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \
772 IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0)
773 #define _MX6Q_PAD_EIM_RW__ECSPI2_SS0 \
774 IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0)
775 #define _MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \
776 IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0)
777 #define _MX6Q_PAD_EIM_RW__GPIO_2_26 \
778 IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0)
779 #define _MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \
780 IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0)
781 #define _MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \
782 IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0)
784 #define _MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \
785 IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0)
786 #define _MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \
787 IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0)
788 #define _MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \
789 IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0)
790 #define _MX6Q_PAD_EIM_LBA__GPIO_2_27 \
791 IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0)
792 #define _MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \
793 IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0)
794 #define _MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \
795 IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0)
797 #define _MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \
798 IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0)
799 #define _MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \
800 IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0)
801 #define _MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \
802 IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0)
803 #define _MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \
804 IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0)
805 #define _MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \
806 IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0)
807 #define _MX6Q_PAD_EIM_EB0__GPIO_2_28 \
808 IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0)
809 #define _MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \
810 IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0)
811 #define _MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \
812 IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0)
814 #define _MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \
815 IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0)
816 #define _MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \
817 IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0)
818 #define _MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \
819 IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0)
820 #define _MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \
821 IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0)
822 #define _MX6Q_PAD_EIM_EB1__GPIO_2_29 \
823 IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0)
824 #define _MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \
825 IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0)
826 #define _MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \
827 IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0)
829 #define _MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \
830 IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0)
831 #define _MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \
832 IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0)
833 #define _MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \
834 IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0)
835 #define _MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \
836 IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0)
837 #define _MX6Q_PAD_EIM_DA0__GPIO_3_0 \
838 IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0)
839 #define _MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \
840 IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0)
841 #define _MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \
842 IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0)
844 #define _MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \
845 IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0)
846 #define _MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \
847 IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0)
848 #define _MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \
849 IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0)
850 #define _MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \
851 IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0)
852 #define _MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \
853 IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0)
854 #define _MX6Q_PAD_EIM_DA1__GPIO_3_1 \
855 IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0)
856 #define _MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \
857 IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0)
858 #define _MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \
859 IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0)
861 #define _MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \
862 IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0)
863 #define _MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \
864 IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0)
865 #define _MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \
866 IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0)
867 #define _MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \
868 IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0)
869 #define _MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \
870 IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0)
871 #define _MX6Q_PAD_EIM_DA2__GPIO_3_2 \
872 IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0)
873 #define _MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \
874 IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0)
875 #define _MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \
876 IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0)
878 #define _MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \
879 IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0)
880 #define _MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \
881 IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0)
882 #define _MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \
883 IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0)
884 #define _MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \
885 IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0)
886 #define _MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \
887 IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0)
888 #define _MX6Q_PAD_EIM_DA3__GPIO_3_3 \
889 IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0)
890 #define _MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \
891 IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0)
892 #define _MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \
893 IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0)
895 #define _MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \
896 IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0)
897 #define _MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \
898 IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0)
899 #define _MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \
900 IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0)
901 #define _MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \
902 IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0)
903 #define _MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \
904 IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0)
905 #define _MX6Q_PAD_EIM_DA4__GPIO_3_4 \
906 IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0)
907 #define _MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \
908 IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0)
909 #define _MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \
910 IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0)
912 #define _MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \
913 IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0)
914 #define _MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \
915 IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0)
916 #define _MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \
917 IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0)
918 #define _MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \
919 IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0)
920 #define _MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \
921 IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0)
922 #define _MX6Q_PAD_EIM_DA5__GPIO_3_5 \
923 IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0)
924 #define _MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \
925 IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0)
926 #define _MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \
927 IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0)
929 #define _MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \
930 IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0)
931 #define _MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \
932 IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0)
933 #define _MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \
934 IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0)
935 #define _MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \
936 IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0)
937 #define _MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \
938 IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0)
939 #define _MX6Q_PAD_EIM_DA6__GPIO_3_6 \
940 IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0)
941 #define _MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \
942 IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0)
943 #define _MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \
944 IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0)
946 #define _MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \
947 IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0)
948 #define _MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \
949 IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0)
950 #define _MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \
951 IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0)
952 #define _MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \
953 IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0)
954 #define _MX6Q_PAD_EIM_DA7__GPIO_3_7 \
955 IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0)
956 #define _MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \
957 IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0)
958 #define _MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \
959 IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0)
961 #define _MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \
962 IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0)
963 #define _MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \
964 IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0)
965 #define _MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \
966 IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0)
967 #define _MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \
968 IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0)
969 #define _MX6Q_PAD_EIM_DA8__GPIO_3_8 \
970 IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0)
971 #define _MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \
972 IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0)
973 #define _MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \
974 IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0)
976 #define _MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \
977 IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0)
978 #define _MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \
979 IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0)
980 #define _MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \
981 IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0)
982 #define _MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \
983 IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0)
984 #define _MX6Q_PAD_EIM_DA9__GPIO_3_9 \
985 IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0)
986 #define _MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \
987 IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0)
988 #define _MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \
989 IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0)
991 #define _MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \
992 IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0)
993 #define _MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \
994 IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0)
995 #define _MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \
996 IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0)
997 #define _MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \
998 IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0)
999 #define _MX6Q_PAD_EIM_DA10__GPIO_3_10 \
1000 IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0)
1001 #define _MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \
1002 IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0)
1003 #define _MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \
1004 IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0)
1006 #define _MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \
1007 IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0)
1008 #define _MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \
1009 IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0)
1010 #define _MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \
1011 IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0)
1012 #define _MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \
1013 IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0)
1014 #define _MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \
1015 IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0)
1016 #define _MX6Q_PAD_EIM_DA11__GPIO_3_11 \
1017 IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0)
1018 #define _MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \
1019 IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0)
1020 #define _MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \
1021 IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0)
1023 #define _MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \
1024 IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0)
1025 #define _MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \
1026 IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0)
1027 #define _MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \
1028 IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0)
1029 #define _MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \
1030 IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0)
1031 #define _MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \
1032 IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0)
1033 #define _MX6Q_PAD_EIM_DA12__GPIO_3_12 \
1034 IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0)
1035 #define _MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \
1036 IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0)
1037 #define _MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \
1038 IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0)
1040 #define _MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \
1041 IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0)
1042 #define _MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \
1043 IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0)
1044 #define _MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \
1045 IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0)
1046 #define _MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \
1047 IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0)
1048 #define _MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \
1049 IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0)
1050 #define _MX6Q_PAD_EIM_DA13__GPIO_3_13 \
1051 IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0)
1052 #define _MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \
1053 IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0)
1054 #define _MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \
1055 IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0)
1057 #define _MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \
1058 IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0)
1059 #define _MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \
1060 IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0)
1061 #define _MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \
1062 IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0)
1063 #define _MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \
1064 IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0)
1065 #define _MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \
1066 IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0)
1067 #define _MX6Q_PAD_EIM_DA14__GPIO_3_14 \
1068 IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0)
1069 #define _MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \
1070 IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0)
1071 #define _MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \
1072 IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0)
1074 #define _MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \
1075 IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0)
1076 #define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \
1077 IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0)
1078 #define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \
1079 IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0)
1080 #define _MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \
1081 IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0)
1082 #define _MX6Q_PAD_EIM_DA15__GPIO_3_15 \
1083 IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0)
1084 #define _MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \
1085 IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0)
1086 #define _MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \
1087 IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0)
1089 #define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \
1090 IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0)
1091 #define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \
1092 IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0)
1093 #define _MX6Q_PAD_EIM_WAIT__GPIO_5_0 \
1094 IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0)
1095 #define _MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \
1096 IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0)
1097 #define _MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \
1098 IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0)
1100 #define _MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \
1101 IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0)
1102 #define _MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \
1103 IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0)
1104 #define _MX6Q_PAD_EIM_BCLK__GPIO_6_31 \
1105 IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0)
1106 #define _MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \
1107 IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0)
1109 #define _MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \
1110 IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0)
1111 #define _MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \
1112 IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0)
1113 #define _MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \
1114 IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0)
1115 #define _MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \
1116 IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0)
1117 #define _MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \
1118 IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0)
1119 #define _MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \
1120 IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0)
1122 #define _MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \
1123 IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0)
1124 #define _MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \
1125 IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0)
1126 #define _MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \
1127 IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0)
1128 #define _MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \
1129 IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0)
1130 #define _MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \
1131 IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0)
1132 #define _MX6Q_PAD_DI0_PIN15__GPIO_4_17 \
1133 IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0)
1134 #define _MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \
1135 IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0)
1137 #define _MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \
1138 IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0)
1139 #define _MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \
1140 IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0)
1141 #define _MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \
1142 IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0)
1143 #define _MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \
1144 IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0)
1145 #define _MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \
1146 IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0)
1147 #define _MX6Q_PAD_DI0_PIN2__GPIO_4_18 \
1148 IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0)
1149 #define _MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \
1150 IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0)
1151 #define _MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \
1152 IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0)
1154 #define _MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \
1155 IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0)
1156 #define _MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \
1157 IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0)
1158 #define _MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \
1159 IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0)
1160 #define _MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \
1161 IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0)
1162 #define _MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \
1163 IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0)
1164 #define _MX6Q_PAD_DI0_PIN3__GPIO_4_19 \
1165 IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0)
1166 #define _MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \
1167 IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0)
1168 #define _MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \
1169 IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0)
1171 #define _MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \
1172 IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0)
1173 #define _MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \
1174 IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0)
1175 #define _MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \
1176 IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0)
1177 #define _MX6Q_PAD_DI0_PIN4__USDHC1_WP \
1178 IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0)
1179 #define _MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \
1180 IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0)
1181 #define _MX6Q_PAD_DI0_PIN4__GPIO_4_20 \
1182 IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0)
1183 #define _MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \
1184 IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0)
1185 #define _MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \
1186 IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0)
1188 #define _MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \
1189 IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0)
1190 #define _MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \
1191 IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0)
1192 #define _MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \
1193 IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0)
1194 #define _MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \
1195 IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0)
1196 #define _MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \
1197 IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0)
1198 #define _MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \
1199 IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0)
1200 #define _MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \
1201 IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0)
1203 #define _MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \
1204 IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0)
1205 #define _MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \
1206 IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0)
1207 #define _MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \
1208 IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0)
1209 #define _MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \
1210 IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0)
1211 #define _MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
1212 IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0)
1213 #define _MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \
1214 IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0)
1215 #define _MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \
1216 IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0)
1217 #define _MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \
1218 IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0)
1220 #define _MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \
1221 IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0)
1222 #define _MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \
1223 IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0)
1224 #define _MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \
1225 IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0)
1226 #define _MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \
1227 IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0)
1228 #define _MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \
1229 IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0)
1230 #define _MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \
1231 IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0)
1232 #define _MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \
1233 IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0)
1234 #define _MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \
1235 IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0)
1237 #define _MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \
1238 IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0)
1239 #define _MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \
1240 IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0)
1241 #define _MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \
1242 IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0)
1243 #define _MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \
1244 IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0)
1245 #define _MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \
1246 IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0)
1247 #define _MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \
1248 IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0)
1249 #define _MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \
1250 IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0)
1251 #define _MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \
1252 IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0)
1254 #define _MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \
1255 IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0)
1256 #define _MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \
1257 IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0)
1258 #define _MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \
1259 IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0)
1260 #define _MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \
1261 IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0)
1262 #define _MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \
1263 IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0)
1264 #define _MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \
1265 IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0)
1266 #define _MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \
1267 IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0)
1268 #define _MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \
1269 IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0)
1271 #define _MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \
1272 IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0)
1273 #define _MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \
1274 IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0)
1275 #define _MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \
1276 IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0)
1277 #define _MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \
1278 IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0)
1279 #define _MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \
1280 IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0)
1281 #define _MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \
1282 IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0)
1283 #define _MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \
1284 IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0)
1285 #define _MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \
1286 IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0)
1288 #define _MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \
1289 IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0)
1290 #define _MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \
1291 IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0)
1292 #define _MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \
1293 IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0)
1294 #define _MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \
1295 IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0)
1296 #define _MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \
1297 IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0)
1298 #define _MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \
1299 IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0)
1300 #define _MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \
1301 IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0)
1302 #define _MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \
1303 IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0)
1305 #define _MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \
1306 IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0)
1307 #define _MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \
1308 IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0)
1309 #define _MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \
1310 IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0)
1311 #define _MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \
1312 IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0)
1313 #define _MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \
1314 IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0)
1315 #define _MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \
1316 IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0)
1317 #define _MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \
1318 IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0)
1319 #define _MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \
1320 IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0)
1322 #define _MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \
1323 IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0)
1324 #define _MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \
1325 IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0)
1326 #define _MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \
1327 IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0)
1328 #define _MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \
1329 IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0)
1330 #define _MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \
1331 IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0)
1332 #define _MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \
1333 IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0)
1334 #define _MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \
1335 IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0)
1336 #define _MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \
1337 IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0)
1339 #define _MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \
1340 IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0)
1341 #define _MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \
1342 IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0)
1343 #define _MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \
1344 IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0)
1345 #define _MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \
1346 IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0)
1347 #define _MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \
1348 IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0)
1349 #define _MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \
1350 IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0)
1351 #define _MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \
1352 IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0)
1353 #define _MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \
1354 IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0)
1356 #define _MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \
1357 IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0)
1358 #define _MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \
1359 IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0)
1360 #define _MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \
1361 IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0)
1362 #define _MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
1363 IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0)
1364 #define _MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \
1365 IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0)
1366 #define _MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \
1367 IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0)
1368 #define _MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \
1369 IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0)
1371 #define _MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \
1372 IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0)
1373 #define _MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \
1374 IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0)
1375 #define _MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \
1376 IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0)
1377 #define _MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
1378 IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0)
1379 #define _MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \
1380 IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0)
1381 #define _MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \
1382 IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0)
1383 #define _MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \
1384 IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0)
1386 #define _MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \
1387 IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0)
1388 #define _MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \
1389 IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0)
1390 #define _MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED \
1391 IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0)
1392 #define _MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
1393 IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0)
1394 #define _MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \
1395 IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0)
1396 #define _MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \
1397 IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0)
1398 #define _MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \
1399 IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0)
1401 #define _MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \
1402 IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0)
1403 #define _MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \
1404 IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0)
1405 #define _MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \
1406 IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0)
1407 #define _MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
1408 IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0)
1409 #define _MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \
1410 IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0)
1411 #define _MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \
1412 IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0)
1413 #define _MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \
1414 IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0)
1416 #define _MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \
1417 IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0)
1418 #define _MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \
1419 IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0)
1420 #define _MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \
1421 IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0)
1422 #define _MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
1423 IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0)
1424 #define _MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \
1425 IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0)
1426 #define _MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \
1427 IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0)
1429 #define _MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \
1430 IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0)
1431 #define _MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \
1432 IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0)
1433 #define _MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \
1434 IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0)
1435 #define _MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \
1436 IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0)
1437 #define _MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
1438 IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0)
1439 #define _MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \
1440 IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0)
1441 #define _MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \
1442 IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0)
1443 #define _MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \
1444 IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0)
1446 #define _MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \
1447 IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0)
1448 #define _MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \
1449 IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0)
1450 #define _MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \
1451 IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0)
1452 #define _MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \
1453 IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0)
1454 #define _MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \
1455 IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0)
1456 #define _MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \
1457 IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0)
1458 #define _MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \
1459 IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0)
1460 #define _MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \
1461 IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0)
1463 #define _MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \
1464 IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0)
1465 #define _MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \
1466 IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0)
1467 #define _MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \
1468 IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0)
1469 #define _MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \
1470 IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0)
1471 #define _MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \
1472 IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0)
1473 #define _MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \
1474 IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0)
1475 #define _MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \
1476 IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0)
1477 #define _MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \
1478 IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0)
1480 #define _MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \
1481 IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0)
1482 #define _MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \
1483 IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0)
1484 #define _MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \
1485 IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0)
1486 #define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \
1487 IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0)
1488 #define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \
1489 IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0)
1490 #define _MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \
1491 IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0)
1492 #define _MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \
1493 IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0)
1494 #define _MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \
1495 IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0)
1497 #define _MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \
1498 IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0)
1499 #define _MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \
1500 IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0)
1501 #define _MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \
1502 IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0)
1503 #define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \
1504 IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0)
1505 #define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \
1506 IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0)
1507 #define _MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \
1508 IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0)
1509 #define _MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \
1510 IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0)
1511 #define _MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \
1512 IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0)
1514 #define _MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \
1515 IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0)
1516 #define _MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \
1517 IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0)
1518 #define _MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \
1519 IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0)
1520 #define _MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \
1521 IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0)
1522 #define _MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
1523 IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0)
1524 #define _MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \
1525 IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0)
1526 #define _MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \
1527 IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0)
1528 #define _MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \
1529 IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0)
1531 #define _MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \
1532 IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0)
1533 #define _MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \
1534 IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0)
1535 #define _MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \
1536 IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0)
1537 #define _MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \
1538 IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0)
1539 #define _MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \
1540 IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0)
1541 #define _MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \
1542 IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0)
1543 #define _MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \
1544 IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0)
1545 #define _MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \
1546 IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0)
1548 #define _MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \
1549 IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0)
1550 #define _MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \
1551 IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0)
1552 #define _MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \
1553 IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0)
1554 #define _MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \
1555 IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0)
1556 #define _MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \
1557 IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0)
1558 #define _MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \
1559 IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0)
1560 #define _MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \
1561 IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0)
1562 #define _MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \
1563 IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0)
1565 #define _MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \
1566 IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0)
1567 #define _MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \
1568 IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0)
1569 #define _MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \
1570 IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0)
1571 #define _MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \
1572 IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0)
1573 #define _MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \
1574 IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0)
1575 #define _MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \
1576 IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0)
1577 #define _MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \
1578 IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0)
1579 #define _MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \
1580 IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0)
1582 #define _MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED \
1583 IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0)
1584 #define _MX6Q_PAD_ENET_MDIO__ENET_MDIO \
1585 IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0)
1586 #define _MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \
1587 IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0)
1588 #define _MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \
1589 IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0)
1590 #define _MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \
1591 IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0)
1592 #define _MX6Q_PAD_ENET_MDIO__GPIO_1_22 \
1593 IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0)
1594 #define _MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \
1595 IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0)
1597 #define _MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED \
1598 IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0)
1599 #define _MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \
1600 IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0)
1601 #define _MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \
1602 IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0)
1603 #define _MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \
1604 IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0)
1605 #define _MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \
1606 IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0)
1607 #define _MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \
1608 IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0)
1609 #define _MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \
1610 IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0)
1612 #define _MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \
1613 IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0)
1614 #define _MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \
1615 IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0)
1616 #define _MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \
1617 IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0)
1618 #define _MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \
1619 IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0)
1620 #define _MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \
1621 IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0)
1622 #define _MX6Q_PAD_ENET_RX_ER__PHY_TDI \
1623 IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0)
1624 #define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \
1625 IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0)
1627 #define _MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED \
1628 IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0)
1629 #define _MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \
1630 IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0)
1631 #define _MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \
1632 IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0)
1633 #define _MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \
1634 IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0)
1635 #define _MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \
1636 IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0)
1637 #define _MX6Q_PAD_ENET_CRS_DV__PHY_TDO \
1638 IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0)
1639 #define _MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \
1640 IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0)
1642 #define _MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \
1643 IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0)
1644 #define _MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \
1645 IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0)
1646 #define _MX6Q_PAD_ENET_RXD1__ESAI1_FST \
1647 IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0)
1648 #define _MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \
1649 IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0)
1650 #define _MX6Q_PAD_ENET_RXD1__GPIO_1_26 \
1651 IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0)
1652 #define _MX6Q_PAD_ENET_RXD1__PHY_TCK \
1653 IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0)
1654 #define _MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \
1655 IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0)
1657 #define _MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \
1658 IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0)
1659 #define _MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \
1660 IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0)
1661 #define _MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \
1662 IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0)
1663 #define _MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \
1664 IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0)
1665 #define _MX6Q_PAD_ENET_RXD0__GPIO_1_27 \
1666 IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0)
1667 #define _MX6Q_PAD_ENET_RXD0__PHY_TMS \
1668 IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0)
1669 #define _MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \
1670 IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0)
1672 #define _MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED \
1673 IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0)
1674 #define _MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \
1675 IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0)
1676 #define _MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \
1677 IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0)
1678 #define _MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \
1679 IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0)
1680 #define _MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \
1681 IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0)
1682 #define _MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \
1683 IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0)
1685 #define _MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \
1686 IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0)
1687 #define _MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \
1688 IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0)
1689 #define _MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \
1690 IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0)
1691 #define _MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \
1692 IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0)
1693 #define _MX6Q_PAD_ENET_TXD1__GPIO_1_29 \
1694 IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0)
1695 #define _MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \
1696 IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0)
1697 #define _MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \
1698 IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0)
1700 #define _MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED \
1701 IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0)
1702 #define _MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \
1703 IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0)
1704 #define _MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \
1705 IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0)
1706 #define _MX6Q_PAD_ENET_TXD0__GPIO_1_30 \
1707 IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0)
1708 #define _MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \
1709 IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0)
1710 #define _MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \
1711 IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0)
1713 #define _MX6Q_PAD_ENET_MDC__MLB_MLBDAT \
1714 IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0)
1715 #define _MX6Q_PAD_ENET_MDC__ENET_MDC \
1716 IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0)
1717 #define _MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \
1718 IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0)
1719 #define _MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \
1720 IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0)
1721 #define _MX6Q_PAD_ENET_MDC__GPIO_1_31 \
1722 IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0)
1723 #define _MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \
1724 IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0)
1725 #define _MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \
1726 IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0)
1728 #define _MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \
1729 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1731 #define _MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \
1732 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1734 #define _MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \
1735 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1737 #define _MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \
1738 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1740 #define _MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \
1741 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1743 #define _MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \
1744 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1746 #define _MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \
1747 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1749 #define _MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \
1750 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1752 #define _MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \
1753 IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0)
1755 #define _MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \
1756 IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0)
1758 #define _MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \
1759 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1761 #define _MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \
1762 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1764 #define _MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \
1765 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1767 #define _MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \
1768 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1770 #define _MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \
1771 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1773 #define _MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \
1774 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1776 #define _MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \
1777 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1779 #define _MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \
1780 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1782 #define _MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \
1783 IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0)
1785 #define _MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \
1786 IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0)
1788 #define _MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \
1789 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1791 #define _MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \
1792 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1794 #define _MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \
1795 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1797 #define _MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \
1798 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1800 #define _MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \
1801 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1803 #define _MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \
1804 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1806 #define _MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \
1807 IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0)
1809 #define _MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \
1810 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1812 #define _MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \
1813 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1815 #define _MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \
1816 IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0)
1818 #define _MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \
1819 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1821 #define _MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \
1822 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1824 #define _MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \
1825 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1827 #define _MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \
1828 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1830 #define _MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \
1831 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1833 #define _MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \
1834 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1836 #define _MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \
1837 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1839 #define _MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \
1840 IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0)
1842 #define _MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \
1843 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1845 #define _MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \
1846 IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0)
1848 #define _MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \
1849 IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0)
1851 #define _MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \
1852 IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0)
1854 #define _MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \
1855 IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0)
1857 #define _MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \
1858 IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0)
1860 #define _MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \
1861 IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0)
1863 #define _MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \
1864 IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0)
1866 #define _MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \
1867 IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0)
1869 #define _MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \
1870 IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0)
1872 #define _MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \
1873 IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0)
1875 #define _MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \
1876 IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0)
1878 #define _MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \
1879 IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0)
1881 #define _MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \
1882 IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0)
1884 #define _MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \
1885 IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0)
1887 #define _MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \
1888 IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0)
1890 #define _MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \
1891 IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0)
1893 #define _MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \
1894 IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0)
1896 #define _MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \
1897 IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0)
1899 #define _MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \
1900 IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0)
1902 #define _MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \
1903 IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0)
1905 #define _MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \
1906 IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0)
1908 #define _MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \
1909 IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0)
1911 #define _MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \
1912 IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0)
1914 #define _MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \
1915 IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0)
1917 #define _MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \
1918 IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0)
1920 #define _MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \
1921 IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0)
1923 #define _MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \
1924 IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0)
1926 #define _MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \
1927 IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0)
1929 #define _MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \
1930 IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0)
1932 #define _MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \
1933 IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0)
1935 #define _MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \
1936 IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0)
1938 #define _MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \
1939 IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0)
1941 #define _MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \
1942 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1944 #define _MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \
1945 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1947 #define _MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \
1948 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1950 #define _MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \
1951 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1953 #define _MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \
1954 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1956 #define _MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \
1957 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1959 #define _MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \
1960 IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0)
1962 #define _MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \
1963 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1965 #define _MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \
1966 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1968 #define _MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \
1969 IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0)
1971 #define _MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \
1972 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1974 #define _MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \
1975 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1977 #define _MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \
1978 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1980 #define _MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \
1981 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1983 #define _MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \
1984 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1986 #define _MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \
1987 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1989 #define _MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \
1990 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1992 #define _MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \
1993 IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0)
1995 #define _MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \
1996 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1998 #define _MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \
1999 IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0)
2001 #define _MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \
2002 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2004 #define _MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \
2005 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2007 #define _MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \
2008 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2010 #define _MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \
2011 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2013 #define _MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \
2014 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2016 #define _MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \
2017 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2019 #define _MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \
2020 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2022 #define _MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \
2023 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2025 #define _MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \
2026 IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0)
2028 #define _MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \
2029 IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0)
2031 #define _MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \
2032 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2034 #define _MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \
2035 IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0)
2037 #define _MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \
2038 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2040 #define _MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \
2041 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2043 #define _MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \
2044 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2046 #define _MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \
2047 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2049 #define _MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \
2050 IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0)
2052 #define _MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \
2053 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2055 #define _MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \
2056 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2058 #define _MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \
2059 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2061 #define _MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \
2062 IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0)
2063 #define _MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \
2064 IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0)
2065 #define _MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \
2066 IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0)
2067 #define _MX6Q_PAD_KEY_COL0__KPP_COL_0 \
2068 IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0)
2069 #define _MX6Q_PAD_KEY_COL0__UART4_TXD \
2070 IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0)
2071 #define _MX6Q_PAD_KEY_COL0__UART4_RXD \
2072 IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0)
2073 #define _MX6Q_PAD_KEY_COL0__GPIO_4_6 \
2074 IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0)
2075 #define _MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \
2076 IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0)
2077 #define _MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \
2078 IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0)
2080 #define _MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \
2081 IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0)
2082 #define _MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \
2083 IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0)
2084 #define _MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \
2085 IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0)
2086 #define _MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \
2087 IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0)
2088 #define _MX6Q_PAD_KEY_ROW0__UART4_TXD \
2089 IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0)
2090 #define _MX6Q_PAD_KEY_ROW0__UART4_RXD \
2091 IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0)
2092 #define _MX6Q_PAD_KEY_ROW0__GPIO_4_7 \
2093 IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0)
2094 #define _MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \
2095 IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0)
2096 #define _MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \
2097 IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0)
2099 #define _MX6Q_PAD_KEY_COL1__ECSPI1_MISO \
2100 IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0)
2101 #define _MX6Q_PAD_KEY_COL1__ENET_MDIO \
2102 IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0)
2103 #define _MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \
2104 IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0)
2105 #define _MX6Q_PAD_KEY_COL1__KPP_COL_1 \
2106 IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0)
2107 #define _MX6Q_PAD_KEY_COL1__UART5_TXD \
2108 IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0)
2109 #define _MX6Q_PAD_KEY_COL1__UART5_RXD \
2110 IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0)
2111 #define _MX6Q_PAD_KEY_COL1__GPIO_4_8 \
2112 IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0)
2113 #define _MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \
2114 IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0)
2115 #define _MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \
2116 IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0)
2118 #define _MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \
2119 IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0)
2120 #define _MX6Q_PAD_KEY_ROW1__ENET_COL \
2121 IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0)
2122 #define _MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \
2123 IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0)
2124 #define _MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \
2125 IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0)
2126 #define _MX6Q_PAD_KEY_ROW1__UART5_TXD \
2127 IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0)
2128 #define _MX6Q_PAD_KEY_ROW1__UART5_RXD \
2129 IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0)
2130 #define _MX6Q_PAD_KEY_ROW1__GPIO_4_9 \
2131 IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0)
2132 #define _MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \
2133 IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0)
2134 #define _MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \
2135 IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0)
2137 #define _MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \
2138 IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0)
2139 #define _MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \
2140 IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0)
2141 #define _MX6Q_PAD_KEY_COL2__CAN1_TXCAN \
2142 IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0)
2143 #define _MX6Q_PAD_KEY_COL2__KPP_COL_2 \
2144 IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0)
2145 #define _MX6Q_PAD_KEY_COL2__ENET_MDC \
2146 IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0)
2147 #define _MX6Q_PAD_KEY_COL2__GPIO_4_10 \
2148 IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0)
2149 #define _MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \
2150 IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0)
2151 #define _MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \
2152 IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0)
2154 #define _MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \
2155 IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0)
2156 #define _MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \
2157 IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0)
2158 #define _MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \
2159 IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0)
2160 #define _MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \
2161 IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0)
2162 #define _MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \
2163 IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0)
2164 #define _MX6Q_PAD_KEY_ROW2__GPIO_4_11 \
2165 IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0)
2166 #define _MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \
2167 IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0)
2168 #define _MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \
2169 IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0)
2171 #define _MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \
2172 IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0)
2173 #define _MX6Q_PAD_KEY_COL3__ENET_CRS \
2174 IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0)
2175 #define _MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \
2176 IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0)
2177 #define _MX6Q_PAD_KEY_COL3__KPP_COL_3 \
2178 IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0)
2179 #define _MX6Q_PAD_KEY_COL3__I2C2_SCL \
2180 IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0)
2181 #define _MX6Q_PAD_KEY_COL3__GPIO_4_12 \
2182 IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0)
2183 #define _MX6Q_PAD_KEY_COL3__SPDIF_IN1 \
2184 IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0)
2185 #define _MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \
2186 IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0)
2188 #define _MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \
2189 IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0)
2190 #define _MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \
2191 IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0)
2192 #define _MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \
2193 IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0)
2194 #define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \
2195 IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0)
2196 #define _MX6Q_PAD_KEY_ROW3__I2C2_SDA \
2197 IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0)
2198 #define _MX6Q_PAD_KEY_ROW3__GPIO_4_13 \
2199 IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0)
2200 #define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \
2201 IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0)
2202 #define _MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \
2203 IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0)
2205 #define _MX6Q_PAD_KEY_COL4__CAN2_TXCAN \
2206 IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0)
2207 #define _MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \
2208 IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0)
2209 #define _MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \
2210 IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0)
2211 #define _MX6Q_PAD_KEY_COL4__KPP_COL_4 \
2212 IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0)
2213 #define _MX6Q_PAD_KEY_COL4__UART5_CTS \
2214 IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0)
2215 #define _MX6Q_PAD_KEY_COL4__UART5_RTS \
2216 IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0)
2217 #define _MX6Q_PAD_KEY_COL4__GPIO_4_14 \
2218 IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0)
2219 #define _MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \
2220 IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0)
2221 #define _MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \
2222 IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0)
2224 #define _MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \
2225 IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0)
2226 #define _MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \
2227 IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0)
2228 #define _MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \
2229 IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0)
2230 #define _MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \
2231 IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0)
2232 #define _MX6Q_PAD_KEY_ROW4__UART5_CTS \
2233 IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0)
2234 #define _MX6Q_PAD_KEY_ROW4__GPIO_4_15 \
2235 IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0)
2236 #define _MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \
2237 IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0)
2238 #define _MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \
2239 IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0)
2241 #define _MX6Q_PAD_GPIO_0__CCM_CLKO \
2242 IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0)
2243 #define _MX6Q_PAD_GPIO_0__KPP_COL_5 \
2244 IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0)
2245 #define _MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \
2246 IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0)
2247 #define _MX6Q_PAD_GPIO_0__EPIT1_EPITO \
2248 IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0)
2249 #define _MX6Q_PAD_GPIO_0__GPIO_1_0 \
2250 IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0)
2251 #define _MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \
2252 IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0)
2253 #define _MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \
2254 IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0)
2256 #define _MX6Q_PAD_GPIO_1__ESAI1_SCKR \
2257 IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0)
2258 #define _MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \
2259 IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0)
2260 #define _MX6Q_PAD_GPIO_1__KPP_ROW_5 \
2261 IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0)
2262 #define MX6Q_PAD_GPIO_1__USBOTG_ID \
2263 IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, MX6Q_USDHC_PAD_CTRL)
2264 #define _MX6Q_PAD_GPIO_1__PWM2_PWMO \
2265 IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0)
2266 #define _MX6Q_PAD_GPIO_1__GPIO_1_1 \
2267 IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0)
2268 #define _MX6Q_PAD_GPIO_1__USDHC1_CD \
2269 IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0)
2270 #define _MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \
2271 IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0)
2273 #define _MX6Q_PAD_GPIO_9__ESAI1_FSR \
2274 IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0)
2275 #define _MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \
2276 IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0)
2277 #define _MX6Q_PAD_GPIO_9__KPP_COL_6 \
2278 IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0)
2279 #define _MX6Q_PAD_GPIO_9__CCM_REF_EN_B \
2280 IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0)
2281 #define _MX6Q_PAD_GPIO_9__PWM1_PWMO \
2282 IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0)
2283 #define _MX6Q_PAD_GPIO_9__GPIO_1_9 \
2284 IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0)
2285 #define _MX6Q_PAD_GPIO_9__USDHC1_WP \
2286 IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0)
2287 #define _MX6Q_PAD_GPIO_9__SRC_EARLY_RST \
2288 IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0)
2290 #define _MX6Q_PAD_GPIO_3__ESAI1_HCKR \
2291 IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0)
2292 #define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \
2293 IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0)
2294 #define _MX6Q_PAD_GPIO_3__I2C3_SCL \
2295 IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0)
2296 #define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \
2297 IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0)
2298 #define _MX6Q_PAD_GPIO_3__CCM_CLKO2 \
2299 IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0)
2300 #define _MX6Q_PAD_GPIO_3__GPIO_1_3 \
2301 IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0)
2302 #define _MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \
2303 IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0)
2304 #define _MX6Q_PAD_GPIO_3__MLB_MLBCLK \
2305 IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0)
2307 #define _MX6Q_PAD_GPIO_6__ESAI1_SCKT \
2308 IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0)
2309 #define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
2310 IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0)
2311 #define _MX6Q_PAD_GPIO_6__I2C3_SDA \
2312 IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0)
2313 #define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \
2314 IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0)
2315 #define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \
2316 IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0)
2317 #define _MX6Q_PAD_GPIO_6__GPIO_1_6 \
2318 IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0)
2319 #define _MX6Q_PAD_GPIO_6__USDHC2_LCTL \
2320 IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0)
2321 #define _MX6Q_PAD_GPIO_6__MLB_MLBSIG \
2322 IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0)
2324 #define _MX6Q_PAD_GPIO_2__ESAI1_FST \
2325 IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0)
2326 #define _MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \
2327 IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0)
2328 #define _MX6Q_PAD_GPIO_2__KPP_ROW_6 \
2329 IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0)
2330 #define _MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \
2331 IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0)
2332 #define _MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \
2333 IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0)
2334 #define _MX6Q_PAD_GPIO_2__GPIO_1_2 \
2335 IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0)
2336 #define _MX6Q_PAD_GPIO_2__USDHC2_WP \
2337 IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0)
2338 #define _MX6Q_PAD_GPIO_2__MLB_MLBDAT \
2339 IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0)
2341 #define _MX6Q_PAD_GPIO_4__ESAI1_HCKT \
2342 IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0)
2343 #define _MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \
2344 IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0)
2345 #define _MX6Q_PAD_GPIO_4__KPP_COL_7 \
2346 IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0)
2347 #define _MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \
2348 IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0)
2349 #define _MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \
2350 IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0)
2351 #define _MX6Q_PAD_GPIO_4__GPIO_1_4 \
2352 IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0)
2353 #define _MX6Q_PAD_GPIO_4__USDHC2_CD \
2354 IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0)
2355 #define _MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \
2356 IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0)
2358 #define _MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \
2359 IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0)
2360 #define _MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \
2361 IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0)
2362 #define _MX6Q_PAD_GPIO_5__KPP_ROW_7 \
2363 IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0)
2364 #define _MX6Q_PAD_GPIO_5__CCM_CLKO \
2365 IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0)
2366 #define _MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \
2367 IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0)
2368 #define _MX6Q_PAD_GPIO_5__GPIO_1_5 \
2369 IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0)
2370 #define _MX6Q_PAD_GPIO_5__I2C3_SCL \
2371 IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0)
2372 #define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \
2373 IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0)
2375 #define _MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \
2376 IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0)
2377 #define _MX6Q_PAD_GPIO_7__ECSPI5_RDY \
2378 IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0)
2379 #define _MX6Q_PAD_GPIO_7__EPIT1_EPITO \
2380 IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0)
2381 #define _MX6Q_PAD_GPIO_7__CAN1_TXCAN \
2382 IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0)
2383 #define _MX6Q_PAD_GPIO_7__UART2_TXD \
2384 IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0)
2385 #define _MX6Q_PAD_GPIO_7__UART2_RXD \
2386 IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0)
2387 #define _MX6Q_PAD_GPIO_7__GPIO_1_7 \
2388 IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0)
2389 #define _MX6Q_PAD_GPIO_7__SPDIF_PLOCK \
2390 IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0)
2391 #define _MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \
2392 IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0)
2394 #define _MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \
2395 IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0)
2396 #define _MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \
2397 IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0)
2398 #define _MX6Q_PAD_GPIO_8__EPIT2_EPITO \
2399 IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0)
2400 #define _MX6Q_PAD_GPIO_8__CAN1_RXCAN \
2401 IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0)
2402 #define _MX6Q_PAD_GPIO_8__UART2_TXD \
2403 IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0)
2404 #define _MX6Q_PAD_GPIO_8__UART2_RXD \
2405 IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0)
2406 #define _MX6Q_PAD_GPIO_8__GPIO_1_8 \
2407 IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0)
2408 #define _MX6Q_PAD_GPIO_8__SPDIF_SRCLK \
2409 IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0)
2410 #define _MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \
2411 IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0)
2413 #define _MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \
2414 IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0)
2415 #define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \
2416 IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0)
2417 #define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
2418 IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0)
2419 #define _MX6Q_PAD_GPIO_16__USDHC1_LCTL \
2420 IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0)
2421 #define _MX6Q_PAD_GPIO_16__SPDIF_IN1 \
2422 IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0)
2423 #define _MX6Q_PAD_GPIO_16__GPIO_7_11 \
2424 IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0)
2425 #define _MX6Q_PAD_GPIO_16__I2C3_SDA \
2426 IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0)
2427 #define _MX6Q_PAD_GPIO_16__SJC_DE_B \
2428 IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0)
2430 #define _MX6Q_PAD_GPIO_17__ESAI1_TX0 \
2431 IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0)
2432 #define _MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \
2433 IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0)
2434 #define _MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \
2435 IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0)
2436 #define _MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \
2437 IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0)
2438 #define _MX6Q_PAD_GPIO_17__SPDIF_OUT1 \
2439 IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0)
2440 #define _MX6Q_PAD_GPIO_17__GPIO_7_12 \
2441 IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0)
2442 #define _MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \
2443 IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0)
2445 #define _MX6Q_PAD_GPIO_18__ESAI1_TX1 \
2446 IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0)
2447 #define _MX6Q_PAD_GPIO_18__ENET_RX_CLK \
2448 IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0)
2449 #define _MX6Q_PAD_GPIO_18__USDHC3_VSELECT \
2450 IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0)
2451 #define _MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \
2452 IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0)
2453 #define _MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \
2454 IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0)
2455 #define _MX6Q_PAD_GPIO_18__GPIO_7_13 \
2456 IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0)
2457 #define _MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \
2458 IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0)
2459 #define _MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \
2460 IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0)
2462 #define _MX6Q_PAD_GPIO_19__KPP_COL_5 \
2463 IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0)
2464 #define _MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \
2465 IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0)
2466 #define _MX6Q_PAD_GPIO_19__SPDIF_OUT1 \
2467 IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0)
2468 #define _MX6Q_PAD_GPIO_19__CCM_CLKO \
2469 IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0)
2470 #define _MX6Q_PAD_GPIO_19__ECSPI1_RDY \
2471 IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0)
2472 #define _MX6Q_PAD_GPIO_19__GPIO_4_5 \
2473 IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0)
2474 #define _MX6Q_PAD_GPIO_19__ENET_TX_ER \
2475 IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0)
2476 #define _MX6Q_PAD_GPIO_19__SRC_INT_BOOT \
2477 IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0)
2479 #define _MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \
2480 IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0)
2481 #define _MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \
2482 IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0)
2483 #define _MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \
2484 IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0)
2485 #define _MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \
2486 IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0)
2487 #define _MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \
2488 IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0)
2489 #define _MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \
2490 IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0)
2492 #define _MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \
2493 IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0)
2494 #define _MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \
2495 IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0)
2496 #define _MX6Q_PAD_CSI0_MCLK__CCM_CLKO \
2497 IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0)
2498 #define _MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \
2499 IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0)
2500 #define _MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \
2501 IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0)
2502 #define _MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \
2503 IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0)
2504 #define _MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \
2505 IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0)
2507 #define _MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \
2508 IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0)
2509 #define _MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \
2510 IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0)
2511 #define _MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \
2512 IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0)
2513 #define _MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \
2514 IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0)
2515 #define _MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \
2516 IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0)
2517 #define _MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \
2518 IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0)
2519 #define _MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \
2520 IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0)
2522 #define _MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \
2523 IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0)
2524 #define _MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \
2525 IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0)
2526 #define _MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \
2527 IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0)
2528 #define _MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \
2529 IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0)
2530 #define _MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \
2531 IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0)
2532 #define _MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \
2533 IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0)
2534 #define _MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \
2535 IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0)
2537 #define _MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \
2538 IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0)
2539 #define _MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \
2540 IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0)
2541 #define _MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \
2542 IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0)
2543 #define _MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \
2544 IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0)
2545 #define _MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \
2546 IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0)
2547 #define _MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \
2548 IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0)
2549 #define _MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \
2550 IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0)
2551 #define _MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \
2552 IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0)
2554 #define _MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \
2555 IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0)
2556 #define _MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \
2557 IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0)
2558 #define _MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \
2559 IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0)
2560 #define _MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \
2561 IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0)
2562 #define _MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \
2563 IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0)
2564 #define _MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \
2565 IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0)
2566 #define _MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \
2567 IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0)
2568 #define _MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \
2569 IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0)
2571 #define _MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \
2572 IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0)
2573 #define _MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \
2574 IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0)
2575 #define _MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \
2576 IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0)
2577 #define _MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \
2578 IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0)
2579 #define _MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \
2580 IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0)
2581 #define _MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \
2582 IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0)
2583 #define _MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \
2584 IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0)
2585 #define _MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \
2586 IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0)
2588 #define _MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \
2589 IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0)
2590 #define _MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \
2591 IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0)
2592 #define _MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \
2593 IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0)
2594 #define _MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \
2595 IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0)
2596 #define _MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \
2597 IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0)
2598 #define _MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \
2599 IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0)
2600 #define _MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \
2601 IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0)
2602 #define _MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \
2603 IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0)
2605 #define _MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \
2606 IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0)
2607 #define _MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \
2608 IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0)
2609 #define _MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \
2610 IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0)
2611 #define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \
2612 IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0)
2613 #define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA \
2614 IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0)
2615 #define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \
2616 IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0)
2617 #define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \
2618 IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0)
2619 #define _MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \
2620 IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0)
2622 #define _MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \
2623 IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0)
2624 #define _MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \
2625 IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0)
2626 #define _MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \
2627 IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0)
2628 #define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \
2629 IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0)
2630 #define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL \
2631 IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0)
2632 #define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \
2633 IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0)
2634 #define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \
2635 IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0)
2636 #define _MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \
2637 IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0)
2639 #define _MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \
2640 IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0)
2641 #define _MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \
2642 IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0)
2643 #define _MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \
2644 IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0)
2645 #define _MX6Q_PAD_CSI0_DAT10__UART1_TXD \
2646 IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0)
2647 #define _MX6Q_PAD_CSI0_DAT10__UART1_RXD \
2648 IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0)
2649 #define _MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \
2650 IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0)
2651 #define _MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \
2652 IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0)
2653 #define _MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \
2654 IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0)
2655 #define _MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \
2656 IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0)
2658 #define _MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \
2659 IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0)
2660 #define _MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \
2661 IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0)
2662 #define _MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \
2663 IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0)
2664 #define _MX6Q_PAD_CSI0_DAT11__UART1_TXD \
2665 IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0)
2666 #define _MX6Q_PAD_CSI0_DAT11__UART1_RXD \
2667 IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0)
2668 #define _MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \
2669 IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0)
2670 #define _MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \
2671 IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0)
2672 #define _MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \
2673 IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0)
2674 #define _MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \
2675 IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0)
2677 #define _MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \
2678 IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0)
2679 #define _MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \
2680 IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0)
2681 #define _MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \
2682 IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0)
2683 #define _MX6Q_PAD_CSI0_DAT12__UART4_TXD \
2684 IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0)
2685 #define _MX6Q_PAD_CSI0_DAT12__UART4_RXD \
2686 IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0)
2687 #define _MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \
2688 IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0)
2689 #define _MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \
2690 IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0)
2691 #define _MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \
2692 IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0)
2693 #define _MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \
2694 IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0)
2696 #define _MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \
2697 IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0)
2698 #define _MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \
2699 IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0)
2700 #define _MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \
2701 IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0)
2702 #define _MX6Q_PAD_CSI0_DAT13__UART4_TXD \
2703 IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0)
2704 #define _MX6Q_PAD_CSI0_DAT13__UART4_RXD \
2705 IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0)
2706 #define _MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \
2707 IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0)
2708 #define _MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \
2709 IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0)
2710 #define _MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \
2711 IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0)
2712 #define _MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \
2713 IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0)
2715 #define _MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \
2716 IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0)
2717 #define _MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \
2718 IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0)
2719 #define _MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \
2720 IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0)
2721 #define _MX6Q_PAD_CSI0_DAT14__UART5_TXD \
2722 IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0)
2723 #define _MX6Q_PAD_CSI0_DAT14__UART5_RXD \
2724 IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0)
2725 #define _MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \
2726 IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0)
2727 #define _MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \
2728 IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0)
2729 #define _MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \
2730 IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0)
2731 #define _MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \
2732 IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0)
2734 #define _MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \
2735 IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0)
2736 #define _MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \
2737 IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0)
2738 #define _MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \
2739 IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0)
2740 #define _MX6Q_PAD_CSI0_DAT15__UART5_TXD \
2741 IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0)
2742 #define _MX6Q_PAD_CSI0_DAT15__UART5_RXD \
2743 IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0)
2744 #define _MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \
2745 IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0)
2746 #define _MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \
2747 IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0)
2748 #define _MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \
2749 IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0)
2750 #define _MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \
2751 IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0)
2753 #define _MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \
2754 IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0)
2755 #define _MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \
2756 IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0)
2757 #define _MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \
2758 IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0)
2759 #define _MX6Q_PAD_CSI0_DAT16__UART4_CTS \
2760 IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0)
2761 #define _MX6Q_PAD_CSI0_DAT16__UART4_RTS \
2762 IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0)
2763 #define _MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \
2764 IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0)
2765 #define _MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \
2766 IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0)
2767 #define _MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \
2768 IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0)
2769 #define _MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \
2770 IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0)
2772 #define _MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \
2773 IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0)
2774 #define _MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \
2775 IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0)
2776 #define _MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \
2777 IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0)
2778 #define _MX6Q_PAD_CSI0_DAT17__UART4_CTS \
2779 IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0)
2780 #define _MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \
2781 IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0)
2782 #define _MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \
2783 IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0)
2784 #define _MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \
2785 IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0)
2786 #define _MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \
2787 IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0)
2789 #define _MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \
2790 IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0)
2791 #define _MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \
2792 IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0)
2793 #define _MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \
2794 IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0)
2795 #define _MX6Q_PAD_CSI0_DAT18__UART5_CTS \
2796 IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0)
2797 #define _MX6Q_PAD_CSI0_DAT18__UART5_RTS \
2798 IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0)
2799 #define _MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \
2800 IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0)
2801 #define _MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \
2802 IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0)
2803 #define _MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \
2804 IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0)
2805 #define _MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \
2806 IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0)
2808 #define _MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \
2809 IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0)
2810 #define _MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \
2811 IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0)
2812 #define _MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \
2813 IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0)
2814 #define _MX6Q_PAD_CSI0_DAT19__UART5_CTS \
2815 IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0)
2816 #define _MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \
2817 IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0)
2818 #define _MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \
2819 IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0)
2820 #define _MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \
2821 IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0)
2822 #define _MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \
2823 IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0)
2825 #define _MX6Q_PAD_JTAG_TMS__SJC_TMS \
2826 IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0)
2828 #define _MX6Q_PAD_JTAG_MOD__SJC_MOD \
2829 IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0)
2831 #define _MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \
2832 IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0)
2834 #define _MX6Q_PAD_JTAG_TDI__SJC_TDI \
2835 IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0)
2837 #define _MX6Q_PAD_JTAG_TCK__SJC_TCK \
2838 IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0)
2840 #define _MX6Q_PAD_JTAG_TDO__SJC_TDO \
2841 IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0)
2843 #define _MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \
2844 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2846 #define _MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \
2847 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2849 #define _MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \
2850 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2852 #define _MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \
2853 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2855 #define _MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \
2856 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2858 #define _MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \
2859 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2861 #define _MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \
2862 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2864 #define _MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \
2865 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2867 #define _MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \
2868 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2870 #define _MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \
2871 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2873 #define _MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \
2874 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2876 #define _MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \
2877 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2879 #define _MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \
2880 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2882 #define _MX6Q_PAD_POR_B__SRC_POR_B \
2883 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2885 #define _MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \
2886 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2888 #define _MX6Q_PAD_RESET_IN_B__SRC_RESET_B \
2889 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2891 #define _MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \
2892 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2894 #define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \
2895 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2897 #define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 \
2898 IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0)
2899 #define _MX6Q_PAD_SD3_DAT7__UART1_TXD \
2900 IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0)
2901 #define _MX6Q_PAD_SD3_DAT7__UART1_RXD \
2902 IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0)
2903 #define _MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \
2904 IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0)
2905 #define _MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \
2906 IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0)
2907 #define _MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \
2908 IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0)
2909 #define _MX6Q_PAD_SD3_DAT7__GPIO_6_17 \
2910 IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
2911 #define _MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \
2912 IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0)
2913 #define _MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \
2914 IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0)
2916 #define _MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 \
2917 IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0)
2918 #define _MX6Q_PAD_SD3_DAT6__UART1_TXD \
2919 IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0)
2920 #define _MX6Q_PAD_SD3_DAT6__UART1_RXD \
2921 IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0)
2922 #define _MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \
2923 IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0)
2924 #define _MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \
2925 IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0)
2926 #define _MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \
2927 IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0)
2928 #define _MX6Q_PAD_SD3_DAT6__GPIO_6_18 \
2929 IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0)
2930 #define _MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \
2931 IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0)
2932 #define _MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \
2933 IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0)
2935 #define _MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 \
2936 IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0)
2937 #define _MX6Q_PAD_SD3_DAT5__UART2_TXD \
2938 IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0)
2939 #define _MX6Q_PAD_SD3_DAT5__UART2_RXD \
2940 IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0)
2941 #define _MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \
2942 IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0)
2943 #define _MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \
2944 IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0)
2945 #define _MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \
2946 IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0)
2947 #define _MX6Q_PAD_SD3_DAT5__GPIO_7_0 \
2948 IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0)
2949 #define _MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \
2950 IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0)
2951 #define _MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \
2952 IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0)
2954 #define _MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 \
2955 IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0)
2956 #define _MX6Q_PAD_SD3_DAT4__UART2_TXD \
2957 IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0)
2958 #define _MX6Q_PAD_SD3_DAT4__UART2_RXD \
2959 IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0)
2960 #define _MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \
2961 IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0)
2962 #define _MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \
2963 IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0)
2964 #define _MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \
2965 IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0)
2966 #define _MX6Q_PAD_SD3_DAT4__GPIO_7_1 \
2967 IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0)
2968 #define _MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \
2969 IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0)
2970 #define _MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \
2971 IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0)
2973 #define _MX6Q_PAD_SD3_CMD__USDHC3_CMD \
2974 IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
2975 #define _MX6Q_PAD_SD3_CMD__UART2_CTS \
2976 IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0)
2977 #define _MX6Q_PAD_SD3_CMD__CAN1_TXCAN \
2978 IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0)
2979 #define _MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \
2980 IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0)
2981 #define _MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \
2982 IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0)
2983 #define _MX6Q_PAD_SD3_CMD__GPIO_7_2 \
2984 IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0)
2985 #define _MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \
2986 IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0)
2987 #define _MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \
2988 IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0)
2990 #define _MX6Q_PAD_SD3_CLK__USDHC3_CLK \
2991 IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0)
2992 #define _MX6Q_PAD_SD3_CLK__UART2_CTS \
2993 IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0)
2994 #define _MX6Q_PAD_SD3_CLK__UART2_RTS \
2995 IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0)
2996 #define _MX6Q_PAD_SD3_CLK__CAN1_RXCAN \
2997 IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0)
2998 #define _MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \
2999 IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0)
3000 #define _MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \
3001 IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0)
3002 #define _MX6Q_PAD_SD3_CLK__GPIO_7_3 \
3003 IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0)
3004 #define _MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \
3005 IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0)
3006 #define _MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \
3007 IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0)
3009 #define _MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 \
3010 IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0)
3011 #define _MX6Q_PAD_SD3_DAT0__UART1_CTS \
3012 IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0)
3013 #define _MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \
3014 IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0)
3015 #define _MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
3016 IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0)
3017 #define _MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \
3018 IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0)
3019 #define _MX6Q_PAD_SD3_DAT0__GPIO_7_4 \
3020 IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0)
3021 #define _MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \
3022 IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0)
3023 #define _MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \
3024 IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0)
3026 #define _MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 \
3027 IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0)
3028 #define _MX6Q_PAD_SD3_DAT1__UART1_CTS \
3029 IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0)
3030 #define _MX6Q_PAD_SD3_DAT1__UART1_RTS \
3031 IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0)
3032 #define _MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \
3033 IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0)
3034 #define _MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \
3035 IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0)
3036 #define _MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \
3037 IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0)
3038 #define _MX6Q_PAD_SD3_DAT1__GPIO_7_5 \
3039 IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0)
3040 #define _MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \
3041 IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0)
3042 #define _MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \
3043 IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0)
3045 #define _MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 \
3046 IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0)
3047 #define _MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \
3048 IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0)
3049 #define _MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \
3050 IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0)
3051 #define _MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \
3052 IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0)
3053 #define _MX6Q_PAD_SD3_DAT2__GPIO_7_6 \
3054 IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0)
3055 #define _MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \
3056 IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0)
3057 #define _MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \
3058 IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0)
3060 #define _MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 \
3061 IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0)
3062 #define _MX6Q_PAD_SD3_DAT3__UART3_CTS \
3063 IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0)
3064 #define _MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \
3065 IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0)
3066 #define _MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \
3067 IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0)
3068 #define _MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \
3069 IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0)
3070 #define _MX6Q_PAD_SD3_DAT3__GPIO_7_7 \
3071 IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0)
3072 #define _MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \
3073 IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0)
3074 #define _MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \
3075 IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0)
3077 #define _MX6Q_PAD_SD3_RST__USDHC3_RST \
3078 IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0)
3079 #define _MX6Q_PAD_SD3_RST__UART3_CTS \
3080 IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0)
3081 #define _MX6Q_PAD_SD3_RST__UART3_RTS \
3082 IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0)
3083 #define _MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \
3084 IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0)
3085 #define _MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \
3086 IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0)
3087 #define _MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \
3088 IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0)
3089 #define _MX6Q_PAD_SD3_RST__GPIO_7_8 \
3090 IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0)
3091 #define _MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \
3092 IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0)
3093 #define _MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \
3094 IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0)
3096 #define _MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \
3097 IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0)
3098 #define _MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \
3099 IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0)
3100 #define _MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \
3101 IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0)
3102 #define _MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \
3103 IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0)
3104 #define _MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \
3105 IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0)
3106 #define _MX6Q_PAD_NANDF_CLE__GPIO_6_7 \
3107 IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0)
3108 #define _MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \
3109 IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0)
3110 #define _MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \
3111 IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0)
3113 #define _MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \
3114 IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0)
3115 #define _MX6Q_PAD_NANDF_ALE__USDHC4_RST \
3116 IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0)
3117 #define _MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \
3118 IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0)
3119 #define _MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \
3120 IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0)
3121 #define _MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \
3122 IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0)
3123 #define _MX6Q_PAD_NANDF_ALE__GPIO_6_8 \
3124 IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0)
3125 #define _MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \
3126 IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0)
3127 #define _MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \
3128 IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0)
3130 #define _MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \
3131 IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0)
3132 #define _MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \
3133 IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0)
3134 #define _MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \
3135 IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0)
3136 #define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \
3137 IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0)
3138 #define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \
3139 IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0)
3140 #define _MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \
3141 IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0)
3142 #define _MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \
3143 IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0)
3144 #define _MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \
3145 IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0)
3147 #define _MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \
3148 IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0)
3149 #define _MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \
3150 IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0)
3151 #define _MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \
3152 IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0)
3153 #define _MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \
3154 IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0)
3155 #define _MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \
3156 IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0)
3157 #define _MX6Q_PAD_NANDF_RB0__GPIO_6_10 \
3158 IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0)
3159 #define _MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \
3160 IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0)
3161 #define _MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \
3162 IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0)
3164 #define _MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \
3165 IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0)
3166 #define _MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \
3167 IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0)
3168 #define _MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \
3169 IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0)
3170 #define _MX6Q_PAD_NANDF_CS0__GPIO_6_11 \
3171 IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0)
3172 #define _MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \
3173 IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0)
3175 #define _MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \
3176 IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0)
3177 #define _MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \
3178 IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0)
3179 #define _MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \
3180 IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0)
3181 #define _MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \
3182 IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0)
3183 #define _MX6Q_PAD_NANDF_CS1__GPIO_6_14 \
3184 IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0)
3185 #define _MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \
3186 IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0)
3188 #define _MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \
3189 IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0)
3190 #define _MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \
3191 IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0)
3192 #define _MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \
3193 IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0)
3194 #define _MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \
3195 IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0)
3196 #define _MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \
3197 IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0)
3198 #define _MX6Q_PAD_NANDF_CS2__GPIO_6_15 \
3199 IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0)
3200 #define _MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \
3201 IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0)
3203 #define _MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \
3204 IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0)
3205 #define _MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \
3206 IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0)
3207 #define _MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \
3208 IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0)
3209 #define _MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \
3210 IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0)
3211 #define _MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \
3212 IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0)
3213 #define _MX6Q_PAD_NANDF_CS3__GPIO_6_16 \
3214 IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0)
3215 #define _MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \
3216 IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0)
3217 #define _MX6Q_PAD_NANDF_CS3__TPSMP_CLK \
3218 IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0)
3220 #define _MX6Q_PAD_SD4_CMD__USDHC4_CMD \
3221 IOMUX_PAD(0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
3222 #define _MX6Q_PAD_SD4_CMD__RAWNAND_RDN \
3223 IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0)
3224 #define _MX6Q_PAD_SD4_CMD__UART3_TXD \
3225 IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0)
3226 #define _MX6Q_PAD_SD4_CMD__UART3_RXD \
3227 IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0)
3228 #define _MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \
3229 IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0)
3230 #define _MX6Q_PAD_SD4_CMD__GPIO_7_9 \
3231 IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0)
3232 #define _MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \
3233 IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0)
3235 #define _MX6Q_PAD_SD4_CLK__USDHC4_CLK \
3236 IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0)
3237 #define _MX6Q_PAD_SD4_CLK__RAWNAND_WRN \
3238 IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0)
3239 #define _MX6Q_PAD_SD4_CLK__UART3_TXD \
3240 IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0)
3241 #define _MX6Q_PAD_SD4_CLK__UART3_RXD \
3242 IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0)
3243 #define _MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \
3244 IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0)
3245 #define _MX6Q_PAD_SD4_CLK__GPIO_7_10 \
3246 IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0)
3248 #define _MX6Q_PAD_NANDF_D0__RAWNAND_D0 \
3249 IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0)
3250 #define _MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \
3251 IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0)
3252 #define _MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \
3253 IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0)
3254 #define _MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \
3255 IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0)
3256 #define _MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \
3257 IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0)
3258 #define _MX6Q_PAD_NANDF_D0__GPIO_2_0 \
3259 IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0)
3260 #define _MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \
3261 IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0)
3262 #define _MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \
3263 IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0)
3265 #define _MX6Q_PAD_NANDF_D1__RAWNAND_D1 \
3266 IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0)
3267 #define _MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \
3268 IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0)
3269 #define _MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \
3270 IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0)
3271 #define _MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \
3272 IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0)
3273 #define _MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \
3274 IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0)
3275 #define _MX6Q_PAD_NANDF_D1__GPIO_2_1 \
3276 IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0)
3277 #define _MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \
3278 IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0)
3279 #define _MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \
3280 IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0)
3282 #define _MX6Q_PAD_NANDF_D2__RAWNAND_D2 \
3283 IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0)
3284 #define _MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \
3285 IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0)
3286 #define _MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \
3287 IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0)
3288 #define _MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \
3289 IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0)
3290 #define _MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \
3291 IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0)
3292 #define _MX6Q_PAD_NANDF_D2__GPIO_2_2 \
3293 IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0)
3294 #define _MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \
3295 IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0)
3296 #define _MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \
3297 IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0)
3299 #define _MX6Q_PAD_NANDF_D3__RAWNAND_D3 \
3300 IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0)
3301 #define _MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \
3302 IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0)
3303 #define _MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \
3304 IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0)
3305 #define _MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \
3306 IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0)
3307 #define _MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \
3308 IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0)
3309 #define _MX6Q_PAD_NANDF_D3__GPIO_2_3 \
3310 IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0)
3311 #define _MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \
3312 IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0)
3313 #define _MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \
3314 IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0)
3316 #define _MX6Q_PAD_NANDF_D4__RAWNAND_D4 \
3317 IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0)
3318 #define _MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \
3319 IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0)
3320 #define _MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \
3321 IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0)
3322 #define _MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \
3323 IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0)
3324 #define _MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \
3325 IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0)
3326 #define _MX6Q_PAD_NANDF_D4__GPIO_2_4 \
3327 IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0)
3328 #define _MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \
3329 IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0)
3330 #define _MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \
3331 IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0)
3333 #define _MX6Q_PAD_NANDF_D5__RAWNAND_D5 \
3334 IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0)
3335 #define _MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \
3336 IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0)
3337 #define _MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \
3338 IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0)
3339 #define _MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \
3340 IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0)
3341 #define _MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \
3342 IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0)
3343 #define _MX6Q_PAD_NANDF_D5__GPIO_2_5 \
3344 IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0)
3345 #define _MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \
3346 IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0)
3347 #define _MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \
3348 IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0)
3350 #define _MX6Q_PAD_NANDF_D6__RAWNAND_D6 \
3351 IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0)
3352 #define _MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \
3353 IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0)
3354 #define _MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \
3355 IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0)
3356 #define _MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \
3357 IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0)
3358 #define _MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \
3359 IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0)
3360 #define _MX6Q_PAD_NANDF_D6__GPIO_2_6 \
3361 IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0)
3362 #define _MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \
3363 IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0)
3364 #define _MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \
3365 IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0)
3367 #define _MX6Q_PAD_NANDF_D7__RAWNAND_D7 \
3368 IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0)
3369 #define _MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \
3370 IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0)
3371 #define _MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \
3372 IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0)
3373 #define _MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \
3374 IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0)
3375 #define _MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \
3376 IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0)
3377 #define _MX6Q_PAD_NANDF_D7__GPIO_2_7 \
3378 IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0)
3379 #define _MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \
3380 IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0)
3381 #define _MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \
3382 IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0)
3384 #define _MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \
3385 IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0)
3386 #define _MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 \
3387 IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0)
3388 #define _MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \
3389 IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0)
3390 #define _MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \
3391 IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0)
3392 #define _MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \
3393 IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0)
3394 #define _MX6Q_PAD_SD4_DAT0__GPIO_2_8 \
3395 IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0)
3396 #define _MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \
3397 IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0)
3398 #define _MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \
3399 IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0)
3401 #define _MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \
3402 IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0)
3403 #define _MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 \
3404 IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0)
3405 #define _MX6Q_PAD_SD4_DAT1__PWM3_PWMO \
3406 IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0)
3407 #define _MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \
3408 IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0)
3409 #define _MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \
3410 IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0)
3411 #define _MX6Q_PAD_SD4_DAT1__GPIO_2_9 \
3412 IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0)
3413 #define _MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \
3414 IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0)
3415 #define _MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \
3416 IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0)
3418 #define _MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \
3419 IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0)
3420 #define _MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 \
3421 IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0)
3422 #define _MX6Q_PAD_SD4_DAT2__PWM4_PWMO \
3423 IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0)
3424 #define _MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \
3425 IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0)
3426 #define _MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \
3427 IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0)
3428 #define _MX6Q_PAD_SD4_DAT2__GPIO_2_10 \
3429 IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0)
3430 #define _MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \
3431 IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0)
3432 #define _MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \
3433 IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0)
3435 #define _MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \
3436 IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0)
3437 #define _MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 \
3438 IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0)
3439 #define _MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \
3440 IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0)
3441 #define _MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \
3442 IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0)
3443 #define _MX6Q_PAD_SD4_DAT3__GPIO_2_11 \
3444 IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0)
3445 #define _MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \
3446 IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0)
3447 #define _MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \
3448 IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0)
3450 #define _MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \
3451 IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0)
3452 #define _MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 \
3453 IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0)
3454 #define _MX6Q_PAD_SD4_DAT4__UART2_TXD \
3455 IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0)
3456 #define _MX6Q_PAD_SD4_DAT4__UART2_RXD \
3457 IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0)
3458 #define _MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \
3459 IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0)
3460 #define _MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \
3461 IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0)
3462 #define _MX6Q_PAD_SD4_DAT4__GPIO_2_12 \
3463 IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0)
3464 #define _MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \
3465 IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0)
3466 #define _MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \
3467 IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0)
3469 #define _MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \
3470 IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0)
3471 #define _MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 \
3472 IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0)
3473 #define _MX6Q_PAD_SD4_DAT5__UART2_CTS \
3474 IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0)
3475 #define _MX6Q_PAD_SD4_DAT5__UART2_RTS \
3476 IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0)
3477 #define _MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \
3478 IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0)
3479 #define _MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \
3480 IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0)
3481 #define _MX6Q_PAD_SD4_DAT5__GPIO_2_13 \
3482 IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0)
3483 #define _MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \
3484 IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0)
3485 #define _MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \
3486 IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0)
3488 #define _MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \
3489 IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0)
3490 #define _MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 \
3491 IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0)
3492 #define _MX6Q_PAD_SD4_DAT6__UART2_CTS \
3493 IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0)
3494 #define _MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \
3495 IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0)
3496 #define _MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \
3497 IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0)
3498 #define _MX6Q_PAD_SD4_DAT6__GPIO_2_14 \
3499 IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0)
3500 #define _MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \
3501 IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0)
3502 #define _MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \
3503 IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0)
3505 #define _MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \
3506 IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0)
3507 #define _MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 \
3508 IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0)
3509 #define _MX6Q_PAD_SD4_DAT7__UART2_TXD \
3510 IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0)
3511 #define _MX6Q_PAD_SD4_DAT7__UART2_RXD \
3512 IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0)
3513 #define _MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \
3514 IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0)
3515 #define _MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \
3516 IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0)
3517 #define _MX6Q_PAD_SD4_DAT7__GPIO_2_15 \
3518 IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0)
3519 #define _MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \
3520 IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0)
3521 #define _MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \
3522 IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0)
3524 #define _MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \
3525 IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0)
3526 #define _MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \
3527 IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0)
3528 #define _MX6Q_PAD_SD1_DAT1__PWM3_PWMO \
3529 IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0)
3530 #define _MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \
3531 IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0)
3532 #define _MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \
3533 IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0)
3534 #define _MX6Q_PAD_SD1_DAT1__GPIO_1_17 \
3535 IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0)
3536 #define _MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \
3537 IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0)
3538 #define _MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \
3539 IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0)
3541 #define _MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \
3542 IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0)
3543 #define _MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \
3544 IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0)
3545 #define _MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \
3546 IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0)
3547 #define _MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \
3548 IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0)
3549 #define _MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \
3550 IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0)
3551 #define _MX6Q_PAD_SD1_DAT0__GPIO_1_16 \
3552 IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0)
3553 #define _MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \
3554 IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0)
3555 #define _MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \
3556 IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0)
3558 #define _MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \
3559 IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0)
3560 #define _MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \
3561 IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0)
3562 #define _MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \
3563 IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0)
3564 #define _MX6Q_PAD_SD1_DAT3__PWM1_PWMO \
3565 IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0)
3566 #define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \
3567 IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0)
3568 #define _MX6Q_PAD_SD1_DAT3__GPIO_1_21 \
3569 IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0)
3570 #define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \
3571 IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0)
3572 #define _MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \
3573 IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0)
3575 #define _MX6Q_PAD_SD1_CMD__USDHC1_CMD \
3576 IOMUX_PAD(0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
3577 #define _MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \
3578 IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0)
3579 #define _MX6Q_PAD_SD1_CMD__PWM4_PWMO \
3580 IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0)
3581 #define _MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \
3582 IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0)
3583 #define _MX6Q_PAD_SD1_CMD__GPIO_1_18 \
3584 IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0)
3585 #define _MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \
3586 IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0)
3588 #define _MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \
3589 IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0)
3590 #define _MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \
3591 IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0)
3592 #define _MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \
3593 IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0)
3594 #define _MX6Q_PAD_SD1_DAT2__PWM2_PWMO \
3595 IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0)
3596 #define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \
3597 IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0)
3598 #define _MX6Q_PAD_SD1_DAT2__GPIO_1_19 \
3599 IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0)
3600 #define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \
3601 IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0)
3602 #define _MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \
3603 IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0)
3605 #define _MX6Q_PAD_SD1_CLK__USDHC1_CLK \
3606 IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0)
3607 #define _MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \
3608 IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0)
3609 #define _MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \
3610 IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0)
3611 #define _MX6Q_PAD_SD1_CLK__GPT_CLKIN \
3612 IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0)
3613 #define _MX6Q_PAD_SD1_CLK__GPIO_1_20 \
3614 IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0)
3615 #define _MX6Q_PAD_SD1_CLK__PHY_DTB_0 \
3616 IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0)
3617 #define _MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \
3618 IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0)
3620 #define _MX6Q_PAD_SD2_CLK__USDHC2_CLK \
3621 IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0)
3622 #define _MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \
3623 IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0)
3624 #define _MX6Q_PAD_SD2_CLK__KPP_COL_5 \
3625 IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0)
3626 #define _MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \
3627 IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0)
3628 #define _MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \
3629 IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0)
3630 #define _MX6Q_PAD_SD2_CLK__GPIO_1_10 \
3631 IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0)
3632 #define _MX6Q_PAD_SD2_CLK__PHY_DTB_1 \
3633 IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0)
3634 #define _MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \
3635 IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0)
3637 #define _MX6Q_PAD_SD2_CMD__USDHC2_CMD \
3638 IOMUX_PAD(0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
3639 #define _MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \
3640 IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0)
3641 #define _MX6Q_PAD_SD2_CMD__KPP_ROW_5 \
3642 IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0)
3643 #define _MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \
3644 IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0)
3645 #define _MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \
3646 IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0)
3647 #define _MX6Q_PAD_SD2_CMD__GPIO_1_11 \
3648 IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0)
3650 #define _MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \
3651 IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0)
3652 #define _MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \
3653 IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0)
3654 #define _MX6Q_PAD_SD2_DAT3__KPP_COL_6 \
3655 IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0)
3656 #define _MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \
3657 IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0)
3658 #define _MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \
3659 IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0)
3660 #define _MX6Q_PAD_SD2_DAT3__GPIO_1_12 \
3661 IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0)
3662 #define _MX6Q_PAD_SD2_DAT3__SJC_DONE \
3663 IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0)
3664 #define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \
3665 IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0)
3669 #define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
3670 (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
3671 #define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
3672 (_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3673 #define MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \
3674 (_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3675 #define MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \
3676 (_MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
3677 #define MX6Q_PAD_SD2_DAT1__KPP_COL_7 \
3678 (_MX6Q_PAD_SD2_DAT1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
3679 #define MX6Q_PAD_SD2_DAT1__GPIO_1_14 \
3680 (_MX6Q_PAD_SD2_DAT1__GPIO_1_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
3681 #define MX6Q_PAD_SD2_DAT1__CCM_WAIT \
3682 (_MX6Q_PAD_SD2_DAT1__CCM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
3683 #define MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \
3684 (_MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3686 #define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \
3687 (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
3688 #define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \
3689 (_MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3690 #define MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \
3691 (_MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
3692 #define MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \
3693 (_MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
3694 #define MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \
3695 (_MX6Q_PAD_SD2_DAT2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
3696 #define MX6Q_PAD_SD2_DAT2__GPIO_1_13 \
3697 (_MX6Q_PAD_SD2_DAT2__GPIO_1_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
3698 #define MX6Q_PAD_SD2_DAT2__CCM_STOP \
3699 (_MX6Q_PAD_SD2_DAT2__CCM_STOP | MUX_PAD_CTRL(NO_PAD_CTRL))
3700 #define MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \
3701 (_MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3703 #define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \
3704 (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
3705 #define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \
3706 (_MX6Q_PAD_SD2_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
3707 #define MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
3708 (_MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
3709 #define MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \
3710 (_MX6Q_PAD_SD2_DAT0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
3711 #define MX6Q_PAD_SD2_DAT0__GPIO_1_15 \
3712 (_MX6Q_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
3713 #define MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \
3714 (_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
3715 #define MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \
3716 (_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3719 #define MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \
3720 (_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
3721 #define MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \
3722 (_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3723 #define MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \
3724 (_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
3725 #define MX6Q_PAD_RGMII_TXC__GPIO_6_19 \
3726 (_MX6Q_PAD_RGMII_TXC__GPIO_6_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
3727 #define MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \
3728 (_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3729 #define MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \
3730 (_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
3733 #define MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \
3734 (_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
3735 #define MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \
3736 (_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3737 #define MX6Q_PAD_RGMII_TD0__GPIO_6_20 \
3738 (_MX6Q_PAD_RGMII_TD0__GPIO_6_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
3739 #define MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \
3740 (_MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3742 #define MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \
3743 (_MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
3744 #define MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \
3745 (_MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3746 #define MX6Q_PAD_RGMII_TD1__GPIO_6_21 \
3747 (_MX6Q_PAD_RGMII_TD1__GPIO_6_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
3748 #define MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \
3749 (_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3750 #define MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \
3751 (_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
3754 #define MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \
3755 (_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
3756 #define MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \
3757 (_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3758 #define MX6Q_PAD_RGMII_TD2__GPIO_6_22 \
3759 (_MX6Q_PAD_RGMII_TD2__GPIO_6_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
3760 #define MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \
3761 (_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
3762 #define MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \
3763 (_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
3766 #define MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \
3767 (_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
3768 #define MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \
3769 (_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3770 #define MX6Q_PAD_RGMII_TD3__GPIO_6_23 \
3771 (_MX6Q_PAD_RGMII_TD3__GPIO_6_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
3772 #define MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \
3773 (_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
3776 #define MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \
3777 (_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
3778 #define MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \
3779 (_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3780 #define MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \
3781 (_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
3782 #define MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \
3783 (_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
3786 #define MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \
3787 (_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
3788 #define MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \
3789 (_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3790 #define MX6Q_PAD_RGMII_RD0__GPIO_6_25 \
3791 (_MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
3792 #define MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \
3793 (_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
3796 #define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \
3797 (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | MUX_PAD_CTRL(NO_PAD_CTRL))
3798 #define MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \
3799 (_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3800 #define MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \
3801 (_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
3802 #define MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \
3803 (_MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
3804 #define MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \
3805 (_MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
3807 #define MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \
3808 (_MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
3809 #define MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \
3810 (_MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3811 #define MX6Q_PAD_RGMII_RD1__GPIO_6_27 \
3812 (_MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
3813 #define MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \
3814 (_MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
3815 #define MX6Q_PAD_RGMII_RD1__SJC_FAIL \
3816 (_MX6Q_PAD_RGMII_RD1__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL))
3818 #define MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \
3819 (_MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
3820 #define MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \
3821 (_MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3822 #define MX6Q_PAD_RGMII_RD2__GPIO_6_28 \
3823 (_MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
3824 #define MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \
3825 (_MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
3827 #define MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \
3828 (_MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
3829 #define MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \
3830 (_MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3831 #define MX6Q_PAD_RGMII_RD3__GPIO_6_29 \
3832 (_MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
3833 #define MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \
3834 (_MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
3836 #define MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \
3837 (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE | MUX_PAD_CTRL(NO_PAD_CTRL))
3838 #define MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \
3839 (_MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3840 #define MX6Q_PAD_RGMII_RXC__GPIO_6_30 \
3841 (_MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
3842 #define MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \
3843 (_MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
3845 #define MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \
3846 (_MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
3847 #define MX6Q_PAD_EIM_A25__ECSPI4_SS1 \
3848 (_MX6Q_PAD_EIM_A25__ECSPI4_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3849 #define MX6Q_PAD_EIM_A25__ECSPI2_RDY \
3850 (_MX6Q_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
3851 #define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \
3852 (_MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
3853 #define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \
3854 (_MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
3855 #define MX6Q_PAD_EIM_A25__GPIO_5_2 \
3856 (_MX6Q_PAD_EIM_A25__GPIO_5_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3857 #define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \
3858 (_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
3859 #define MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \
3860 (_MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3862 #define MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \
3863 (_MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3864 #define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \
3865 (_MX6Q_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3866 #define MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \
3867 (_MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
3868 #define MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \
3869 (_MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
3870 #define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \
3871 (_MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
3872 #define MX6Q_PAD_EIM_EB2__GPIO_2_30 \
3873 (_MX6Q_PAD_EIM_EB2__GPIO_2_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
3874 #define MX6Q_PAD_EIM_EB2__I2C2_SCL \
3875 (_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
3876 #define MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \
3877 (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
3879 #define MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \
3880 (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
3881 #define MX6Q_PAD_EIM_D16__ECSPI1_SCLK \
3882 (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
3883 #define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \
3884 (_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
3885 #define MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \
3886 (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
3887 #define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \
3888 (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
3889 #define MX6Q_PAD_EIM_D16__GPIO_3_16 \
3890 (_MX6Q_PAD_EIM_D16__GPIO_3_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
3891 #define MX6Q_PAD_EIM_D16__I2C2_SDA \
3892 (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
3894 #define MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \
3895 (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
3896 #define MX6Q_PAD_EIM_D17__ECSPI1_MISO \
3897 (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
3898 #define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \
3899 (_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
3900 #define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \
3901 (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
3902 #define MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \
3903 (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
3904 #define MX6Q_PAD_EIM_D17__GPIO_3_17 \
3905 (_MX6Q_PAD_EIM_D17__GPIO_3_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
3906 #define MX6Q_PAD_EIM_D17__I2C3_SCL \
3907 (_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
3908 #define MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \
3909 (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3911 #define MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \
3912 (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
3913 #define MX6Q_PAD_EIM_D18__ECSPI1_MOSI \
3914 (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
3915 #define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \
3916 (_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
3917 #define MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \
3918 (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
3919 #define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \
3920 (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
3921 #define MX6Q_PAD_EIM_D18__GPIO_3_18 \
3922 (_MX6Q_PAD_EIM_D18__GPIO_3_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
3923 #define MX6Q_PAD_EIM_D18__I2C3_SDA \
3924 (_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
3925 #define MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \
3926 (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3928 #define MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \
3929 (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
3930 #define MX6Q_PAD_EIM_D19__ECSPI1_SS1 \
3931 (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3932 #define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \
3933 (_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
3934 #define MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \
3935 (_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
3936 #define MX6Q_PAD_EIM_D19__UART1_CTS \
3937 (_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3938 #define MX6Q_PAD_EIM_D19__GPIO_3_19 \
3939 (_MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
3940 #define MX6Q_PAD_EIM_D19__EPIT1_EPITO \
3941 (_MX6Q_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
3942 #define MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \
3943 (_MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP | MUX_PAD_CTRL(NO_PAD_CTRL))
3945 #define MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \
3946 (_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
3947 #define MX6Q_PAD_EIM_D20__ECSPI4_SS0 \
3948 (_MX6Q_PAD_EIM_D20__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3949 #define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \
3950 (_MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
3951 #define MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \
3952 (_MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
3953 #define MX6Q_PAD_EIM_D20__UART1_CTS \
3954 (_MX6Q_PAD_EIM_D20__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3955 #define MX6Q_PAD_EIM_D20__UART1_RTS \
3956 (_MX6Q_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3957 #define MX6Q_PAD_EIM_D20__GPIO_3_20 \
3958 (_MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
3959 #define MX6Q_PAD_EIM_D20__EPIT2_EPITO \
3960 (_MX6Q_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
3962 #define MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \
3963 (_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
3964 #define MX6Q_PAD_EIM_D21__ECSPI4_SCLK \
3965 (_MX6Q_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
3966 #define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \
3967 (_MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
3968 #define MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \
3969 (_MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
3970 #define MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \
3971 (_MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
3972 #define MX6Q_PAD_EIM_D21__GPIO_3_21 \
3973 (_MX6Q_PAD_EIM_D21__GPIO_3_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
3974 #define MX6Q_PAD_EIM_D21__I2C1_SCL \
3975 (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
3976 #define MX6Q_PAD_EIM_D21__SPDIF_IN1 \
3977 (_MX6Q_PAD_EIM_D21__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3979 #define MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \
3980 (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
3981 #define MX6Q_PAD_EIM_D22__ECSPI4_MISO \
3982 (_MX6Q_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
3983 #define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \
3984 (_MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3985 #define MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \
3986 (_MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
3987 #define MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \
3988 (_MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
3989 #define MX6Q_PAD_EIM_D22__GPIO_3_22 \
3990 (_MX6Q_PAD_EIM_D22__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
3991 #define MX6Q_PAD_EIM_D22__SPDIF_OUT1 \
3992 (_MX6Q_PAD_EIM_D22__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3993 #define MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \
3994 (_MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
3996 #define MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \
3997 (_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
3998 #define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \
3999 (_MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
4000 #define MX6Q_PAD_EIM_D23__UART3_CTS \
4001 (_MX6Q_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4002 #define MX6Q_PAD_EIM_D23__UART1_DCD \
4003 (_MX6Q_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4004 #define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \
4005 (_MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
4006 #define MX6Q_PAD_EIM_D23__GPIO_3_23 \
4007 (_MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4008 #define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \
4009 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4010 #define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \
4011 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4013 #define MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \
4014 (_MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4015 #define MX6Q_PAD_EIM_EB3__ECSPI4_RDY \
4016 (_MX6Q_PAD_EIM_EB3__ECSPI4_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
4017 #define MX6Q_PAD_EIM_EB3__UART3_CTS \
4018 (_MX6Q_PAD_EIM_EB3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4019 #define MX6Q_PAD_EIM_EB3__UART3_RTS \
4020 (_MX6Q_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4021 #define MX6Q_PAD_EIM_EB3__UART1_RI \
4022 (_MX6Q_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4023 #define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \
4024 (_MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
4025 #define MX6Q_PAD_EIM_EB3__GPIO_2_31 \
4026 (_MX6Q_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4027 #define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \
4028 (_MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4029 #define MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \
4030 (_MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4032 #define MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \
4033 (_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4034 #define MX6Q_PAD_EIM_D24__ECSPI4_SS2 \
4035 (_MX6Q_PAD_EIM_D24__ECSPI4_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4036 #define MX6Q_PAD_EIM_D24__UART3_TXD \
4037 (_MX6Q_PAD_EIM_D24__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4038 #define MX6Q_PAD_EIM_D24__UART3_RXD \
4039 (_MX6Q_PAD_EIM_D24__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4040 #define MX6Q_PAD_EIM_D24__ECSPI1_SS2 \
4041 (_MX6Q_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4042 #define MX6Q_PAD_EIM_D24__ECSPI2_SS2 \
4043 (_MX6Q_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4044 #define MX6Q_PAD_EIM_D24__GPIO_3_24 \
4045 (_MX6Q_PAD_EIM_D24__GPIO_3_24 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
4046 #define MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \
4047 (_MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
4048 #define MX6Q_PAD_EIM_D24__UART1_DTR \
4049 (_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4051 #define MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \
4052 (_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4053 #define MX6Q_PAD_EIM_D25__ECSPI4_SS3 \
4054 (_MX6Q_PAD_EIM_D25__ECSPI4_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4055 #define MX6Q_PAD_EIM_D25__UART3_TXD \
4056 (_MX6Q_PAD_EIM_D25__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4057 #define MX6Q_PAD_EIM_D25__UART3_RXD \
4058 (_MX6Q_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4059 #define MX6Q_PAD_EIM_D25__ECSPI1_SS3 \
4060 (_MX6Q_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4061 #define MX6Q_PAD_EIM_D25__ECSPI2_SS3 \
4062 (_MX6Q_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4063 #define MX6Q_PAD_EIM_D25__GPIO_3_25 \
4064 (_MX6Q_PAD_EIM_D25__GPIO_3_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4065 #define MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \
4066 (_MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
4067 #define MX6Q_PAD_EIM_D25__UART1_DSR \
4068 (_MX6Q_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4070 #define MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \
4071 (_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4072 #define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \
4073 (_MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4074 #define MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \
4075 (_MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4076 #define MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \
4077 (_MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4078 #define MX6Q_PAD_EIM_D26__UART2_TXD \
4079 (_MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4080 #define MX6Q_PAD_EIM_D26__UART2_RXD \
4081 (_MX6Q_PAD_EIM_D26__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4082 #define MX6Q_PAD_EIM_D26__GPIO_3_26 \
4083 (_MX6Q_PAD_EIM_D26__GPIO_3_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4084 #define MX6Q_PAD_EIM_D26__IPU1_SISG_2 \
4085 (_MX6Q_PAD_EIM_D26__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4086 #define MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \
4087 (_MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4089 #define MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \
4090 (_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4091 #define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \
4092 (_MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4093 #define MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \
4094 (_MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4095 #define MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \
4096 (_MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4097 #define MX6Q_PAD_EIM_D27__UART2_TXD \
4098 (_MX6Q_PAD_EIM_D27__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4099 #define MX6Q_PAD_EIM_D27__UART2_RXD \
4100 (_MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4101 #define MX6Q_PAD_EIM_D27__GPIO_3_27 \
4102 (_MX6Q_PAD_EIM_D27__GPIO_3_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4103 #define MX6Q_PAD_EIM_D27__IPU1_SISG_3 \
4104 (_MX6Q_PAD_EIM_D27__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4105 #define MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \
4106 (_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4108 #define MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \
4109 (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4110 #define MX6Q_PAD_EIM_D28__I2C1_SDA \
4111 (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
4112 #define MX6Q_PAD_EIM_D28__ECSPI4_MOSI \
4113 (_MX6Q_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
4114 #define MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \
4115 (_MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4116 #define MX6Q_PAD_EIM_D28__UART2_CTS \
4117 (_MX6Q_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4118 #define MX6Q_PAD_EIM_D28__GPIO_3_28 \
4119 (_MX6Q_PAD_EIM_D28__GPIO_3_28 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
4120 #define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \
4121 (_MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
4122 #define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \
4123 (_MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4125 #define MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \
4126 (_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4127 #define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \
4128 (_MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4129 #define MX6Q_PAD_EIM_D29__ECSPI4_SS0 \
4130 (_MX6Q_PAD_EIM_D29__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4131 #define MX6Q_PAD_EIM_D29__UART2_CTS \
4132 (_MX6Q_PAD_EIM_D29__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4133 #define MX6Q_PAD_EIM_D29__UART2_RTS \
4134 (_MX6Q_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4135 #define MX6Q_PAD_EIM_D29__GPIO_3_29 \
4136 (_MX6Q_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4137 #define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \
4138 (_MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
4139 #define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \
4140 (_MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4142 #define MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \
4143 (_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
4144 #define MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
4145 (_MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4146 #define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \
4147 (_MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4148 #define MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \
4149 (_MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4150 #define MX6Q_PAD_EIM_D30__UART3_CTS \
4151 (_MX6Q_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4152 #define MX6Q_PAD_EIM_D30__GPIO_3_30 \
4153 (_MX6Q_PAD_EIM_D30__GPIO_3_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
4154 #define MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \
4155 (_MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
4156 #define MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \
4157 (_MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4159 #define MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \
4160 (_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4161 #define MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
4162 (_MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4163 #define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \
4164 (_MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4165 #define MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \
4166 (_MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4167 #define MX6Q_PAD_EIM_D31__UART3_CTS \
4168 (_MX6Q_PAD_EIM_D31__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4169 #define MX6Q_PAD_EIM_D31__UART3_RTS \
4170 (_MX6Q_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4171 #define MX6Q_PAD_EIM_D31__GPIO_3_31 \
4172 (_MX6Q_PAD_EIM_D31__GPIO_3_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4173 #define MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \
4174 (_MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
4175 #define MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \
4176 (_MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4178 #define MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \
4179 (_MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4180 #define MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \
4181 (_MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4182 #define MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \
4183 (_MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4184 #define MX6Q_PAD_EIM_A24__IPU2_SISG_2 \
4185 (_MX6Q_PAD_EIM_A24__IPU2_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4186 #define MX6Q_PAD_EIM_A24__IPU1_SISG_2 \
4187 (_MX6Q_PAD_EIM_A24__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4188 #define MX6Q_PAD_EIM_A24__GPIO_5_4 \
4189 (_MX6Q_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4190 #define MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \
4191 (_MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4192 #define MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \
4193 (_MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4195 #define MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \
4196 (_MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4197 #define MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \
4198 (_MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4199 #define MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \
4200 (_MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4201 #define MX6Q_PAD_EIM_A23__IPU2_SISG_3 \
4202 (_MX6Q_PAD_EIM_A23__IPU2_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4203 #define MX6Q_PAD_EIM_A23__IPU1_SISG_3 \
4204 (_MX6Q_PAD_EIM_A23__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4205 #define MX6Q_PAD_EIM_A23__GPIO_6_6 \
4206 (_MX6Q_PAD_EIM_A23__GPIO_6_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4207 #define MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \
4208 (_MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4209 #define MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \
4210 (_MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4212 #define MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \
4213 (_MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4214 #define MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \
4215 (_MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4216 #define MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \
4217 (_MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4218 #define MX6Q_PAD_EIM_A22__GPIO_2_16 \
4219 (_MX6Q_PAD_EIM_A22__GPIO_2_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4220 #define MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \
4221 (_MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4222 #define MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \
4223 (_MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4225 #define MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \
4226 (_MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4227 #define MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \
4228 (_MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4229 #define MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \
4230 (_MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4231 #define MX6Q_PAD_EIM_A21__RESERVED_RESERVED \
4232 (_MX6Q_PAD_EIM_A21__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4233 #define MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \
4234 (_MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4235 #define MX6Q_PAD_EIM_A21__GPIO_2_17 \
4236 (_MX6Q_PAD_EIM_A21__GPIO_2_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4237 #define MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \
4238 (_MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4239 #define MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \
4240 (_MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4242 #define MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \
4243 (_MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4244 #define MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \
4245 (_MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4246 #define MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \
4247 (_MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4248 #define MX6Q_PAD_EIM_A20__RESERVED_RESERVED \
4249 (_MX6Q_PAD_EIM_A20__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4250 #define MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \
4251 (_MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4252 #define MX6Q_PAD_EIM_A20__GPIO_2_18 \
4253 (_MX6Q_PAD_EIM_A20__GPIO_2_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4254 #define MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \
4255 (_MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4256 #define MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \
4257 (_MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4259 #define MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \
4260 (_MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4261 #define MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \
4262 (_MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4263 #define MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \
4264 (_MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4265 #define MX6Q_PAD_EIM_A19__RESERVED_RESERVED \
4266 (_MX6Q_PAD_EIM_A19__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4267 #define MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \
4268 (_MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4269 #define MX6Q_PAD_EIM_A19__GPIO_2_19 \
4270 (_MX6Q_PAD_EIM_A19__GPIO_2_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4271 #define MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \
4272 (_MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4273 #define MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \
4274 (_MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4276 #define MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \
4277 (_MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4278 #define MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \
4279 (_MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4280 #define MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \
4281 (_MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4282 #define MX6Q_PAD_EIM_A18__RESERVED_RESERVED \
4283 (_MX6Q_PAD_EIM_A18__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4284 #define MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \
4285 (_MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4286 #define MX6Q_PAD_EIM_A18__GPIO_2_20 \
4287 (_MX6Q_PAD_EIM_A18__GPIO_2_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4288 #define MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \
4289 (_MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4290 #define MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \
4291 (_MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4293 #define MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \
4294 (_MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4295 #define MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \
4296 (_MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4297 #define MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \
4298 (_MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4299 #define MX6Q_PAD_EIM_A17__RESERVED_RESERVED \
4300 (_MX6Q_PAD_EIM_A17__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4301 #define MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \
4302 (_MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4303 #define MX6Q_PAD_EIM_A17__GPIO_2_21 \
4304 (_MX6Q_PAD_EIM_A17__GPIO_2_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4305 #define MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \
4306 (_MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4307 #define MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \
4308 (_MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4310 #define MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \
4311 (_MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4312 #define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \
4313 (_MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4314 #define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \
4315 (_MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4316 #define MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \
4317 (_MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4318 #define MX6Q_PAD_EIM_A16__GPIO_2_22 \
4319 (_MX6Q_PAD_EIM_A16__GPIO_2_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4320 #define MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \
4321 (_MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4322 #define MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \
4323 (_MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4325 #define MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \
4326 (_MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4327 #define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \
4328 (_MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4329 #define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \
4330 (_MX6Q_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4331 #define MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \
4332 (_MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4333 #define MX6Q_PAD_EIM_CS0__GPIO_2_23 \
4334 (_MX6Q_PAD_EIM_CS0__GPIO_2_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4335 #define MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \
4336 (_MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4338 #define MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \
4339 (_MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4340 #define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \
4341 (_MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4342 #define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \
4343 (_MX6Q_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
4344 #define MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \
4345 (_MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4346 #define MX6Q_PAD_EIM_CS1__GPIO_2_24 \
4347 (_MX6Q_PAD_EIM_CS1__GPIO_2_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4348 #define MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \
4349 (_MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4351 #define MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \
4352 (_MX6Q_PAD_EIM_OE__WEIM_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
4353 #define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \
4354 (_MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4355 #define MX6Q_PAD_EIM_OE__ECSPI2_MISO \
4356 (_MX6Q_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
4357 #define MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \
4358 (_MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4359 #define MX6Q_PAD_EIM_OE__GPIO_2_25 \
4360 (_MX6Q_PAD_EIM_OE__GPIO_2_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4361 #define MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \
4362 (_MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4364 #define MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \
4365 (_MX6Q_PAD_EIM_RW__WEIM_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL))
4366 #define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \
4367 (_MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4368 #define MX6Q_PAD_EIM_RW__ECSPI2_SS0 \
4369 (_MX6Q_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4370 #define MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \
4371 (_MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4372 #define MX6Q_PAD_EIM_RW__GPIO_2_26 \
4373 (_MX6Q_PAD_EIM_RW__GPIO_2_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4374 #define MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \
4375 (_MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4376 #define MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \
4377 (_MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4379 #define MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \
4380 (_MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
4381 #define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \
4382 (_MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4383 #define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \
4384 (_MX6Q_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4385 #define MX6Q_PAD_EIM_LBA__GPIO_2_27 \
4386 (_MX6Q_PAD_EIM_LBA__GPIO_2_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4387 #define MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \
4388 (_MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4389 #define MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \
4390 (_MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4392 #define MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \
4393 (_MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4394 #define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \
4395 (_MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4396 #define MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \
4397 (_MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4398 #define MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \
4399 (_MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4400 #define MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \
4401 (_MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
4402 #define MX6Q_PAD_EIM_EB0__GPIO_2_28 \
4403 (_MX6Q_PAD_EIM_EB0__GPIO_2_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4404 #define MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \
4405 (_MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4406 #define MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \
4407 (_MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4409 #define MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \
4410 (_MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4411 #define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \
4412 (_MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4413 #define MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \
4414 (_MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4415 #define MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \
4416 (_MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4417 #define MX6Q_PAD_EIM_EB1__GPIO_2_29 \
4418 (_MX6Q_PAD_EIM_EB1__GPIO_2_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4419 #define MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \
4420 (_MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4421 #define MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \
4422 (_MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4424 #define MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \
4425 (_MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4426 #define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \
4427 (_MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4428 #define MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \
4429 (_MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4430 #define MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \
4431 (_MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4432 #define MX6Q_PAD_EIM_DA0__GPIO_3_0 \
4433 (_MX6Q_PAD_EIM_DA0__GPIO_3_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4434 #define MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \
4435 (_MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4436 #define MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \
4437 (_MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4439 #define MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \
4440 (_MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4441 #define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \
4442 (_MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4443 #define MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \
4444 (_MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4445 #define MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \
4446 (_MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4447 #define MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \
4448 (_MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
4449 #define MX6Q_PAD_EIM_DA1__GPIO_3_1 \
4450 (_MX6Q_PAD_EIM_DA1__GPIO_3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4451 #define MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \
4452 (_MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4453 #define MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \
4454 (_MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4456 #define MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \
4457 (_MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4458 #define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \
4459 (_MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4460 #define MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \
4461 (_MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4462 #define MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \
4463 (_MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4464 #define MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \
4465 (_MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
4466 #define MX6Q_PAD_EIM_DA2__GPIO_3_2 \
4467 (_MX6Q_PAD_EIM_DA2__GPIO_3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4468 #define MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \
4469 (_MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4470 #define MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \
4471 (_MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4473 #define MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \
4474 (_MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4475 #define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \
4476 (_MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4477 #define MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \
4478 (_MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4479 #define MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \
4480 (_MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4481 #define MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \
4482 (_MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ | MUX_PAD_CTRL(NO_PAD_CTRL))
4483 #define MX6Q_PAD_EIM_DA3__GPIO_3_3 \
4484 (_MX6Q_PAD_EIM_DA3__GPIO_3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4485 #define MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \
4486 (_MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4487 #define MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \
4488 (_MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4490 #define MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \
4491 (_MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4492 #define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \
4493 (_MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4494 #define MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \
4495 (_MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4496 #define MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \
4497 (_MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4498 #define MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \
4499 (_MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
4500 #define MX6Q_PAD_EIM_DA4__GPIO_3_4 \
4501 (_MX6Q_PAD_EIM_DA4__GPIO_3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4502 #define MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \
4503 (_MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4504 #define MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \
4505 (_MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4507 #define MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \
4508 (_MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4509 #define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \
4510 (_MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4511 #define MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \
4512 (_MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4513 #define MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \
4514 (_MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4515 #define MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \
4516 (_MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
4517 #define MX6Q_PAD_EIM_DA5__GPIO_3_5 \
4518 (_MX6Q_PAD_EIM_DA5__GPIO_3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4519 #define MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \
4520 (_MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4521 #define MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \
4522 (_MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4524 #define MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \
4525 (_MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4526 #define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \
4527 (_MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4528 #define MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \
4529 (_MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4530 #define MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \
4531 (_MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4532 #define MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \
4533 (_MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN | MUX_PAD_CTRL(NO_PAD_CTRL))
4534 #define MX6Q_PAD_EIM_DA6__GPIO_3_6 \
4535 (_MX6Q_PAD_EIM_DA6__GPIO_3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4536 #define MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \
4537 (_MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4538 #define MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \
4539 (_MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4541 #define MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \
4542 (_MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4543 #define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \
4544 (_MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4545 #define MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \
4546 (_MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4547 #define MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \
4548 (_MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4549 #define MX6Q_PAD_EIM_DA7__GPIO_3_7 \
4550 (_MX6Q_PAD_EIM_DA7__GPIO_3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4551 #define MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \
4552 (_MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4553 #define MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \
4554 (_MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4556 #define MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \
4557 (_MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4558 #define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \
4559 (_MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4560 #define MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \
4561 (_MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4562 #define MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \
4563 (_MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4564 #define MX6Q_PAD_EIM_DA8__GPIO_3_8 \
4565 (_MX6Q_PAD_EIM_DA8__GPIO_3_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4566 #define MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \
4567 (_MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4568 #define MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \
4569 (_MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4571 #define MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \
4572 (_MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4573 #define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \
4574 (_MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4575 #define MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \
4576 (_MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4577 #define MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \
4578 (_MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4579 #define MX6Q_PAD_EIM_DA9__GPIO_3_9 \
4580 (_MX6Q_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4581 #define MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \
4582 (_MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4583 #define MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \
4584 (_MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4586 #define MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \
4587 (_MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4588 #define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \
4589 (_MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4590 #define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \
4591 (_MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
4592 #define MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \
4593 (_MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4594 #define MX6Q_PAD_EIM_DA10__GPIO_3_10 \
4595 (_MX6Q_PAD_EIM_DA10__GPIO_3_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4596 #define MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \
4597 (_MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4598 #define MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \
4599 (_MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4601 #define MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \
4602 (_MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4603 #define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \
4604 (_MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4605 #define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \
4606 (_MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
4607 #define MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \
4608 (_MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4609 #define MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \
4610 (_MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4611 #define MX6Q_PAD_EIM_DA11__GPIO_3_11 \
4612 (_MX6Q_PAD_EIM_DA11__GPIO_3_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4613 #define MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \
4614 (_MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4615 #define MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \
4616 (_MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4618 #define MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \
4619 (_MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4620 #define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \
4621 (_MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4622 #define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \
4623 (_MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
4624 #define MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \
4625 (_MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4626 #define MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \
4627 (_MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4628 #define MX6Q_PAD_EIM_DA12__GPIO_3_12 \
4629 (_MX6Q_PAD_EIM_DA12__GPIO_3_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4630 #define MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \
4631 (_MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4632 #define MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \
4633 (_MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4635 #define MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \
4636 (_MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4637 #define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \
4638 (_MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
4639 #define MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \
4640 (_MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4641 #define MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \
4642 (_MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4643 #define MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \
4644 (_MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4645 #define MX6Q_PAD_EIM_DA13__GPIO_3_13 \
4646 (_MX6Q_PAD_EIM_DA13__GPIO_3_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4647 #define MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \
4648 (_MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4649 #define MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \
4650 (_MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4652 #define MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \
4653 (_MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4654 #define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \
4655 (_MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
4656 #define MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \
4657 (_MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4658 #define MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \
4659 (_MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4660 #define MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \
4661 (_MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4662 #define MX6Q_PAD_EIM_DA14__GPIO_3_14 \
4663 (_MX6Q_PAD_EIM_DA14__GPIO_3_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4664 #define MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \
4665 (_MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4666 #define MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \
4667 (_MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4669 #define MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \
4670 (_MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4671 #define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \
4672 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4673 #define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \
4674 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4675 #define MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \
4676 (_MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4677 #define MX6Q_PAD_EIM_DA15__GPIO_3_15 \
4678 (_MX6Q_PAD_EIM_DA15__GPIO_3_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4679 #define MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \
4680 (_MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4681 #define MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \
4682 (_MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4684 #define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \
4685 (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
4686 #define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \
4687 (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL))
4688 #define MX6Q_PAD_EIM_WAIT__GPIO_5_0 \
4689 (_MX6Q_PAD_EIM_WAIT__GPIO_5_0 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
4690 #define MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \
4691 (_MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
4692 #define MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \
4693 (_MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4695 #define MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \
4696 (_MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4697 #define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \
4698 (_MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4699 #define MX6Q_PAD_EIM_BCLK__GPIO_6_31 \
4700 (_MX6Q_PAD_EIM_BCLK__GPIO_6_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4701 #define MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \
4702 (_MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4704 #define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \
4705 (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4706 #define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \
4707 (_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4708 #define MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \
4709 (_MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4710 #define MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \
4711 (_MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4712 #define MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \
4713 (_MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4714 #define MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \
4715 (_MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4717 #define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \
4718 (_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4719 #define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \
4720 (_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4721 #define MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \
4722 (_MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
4723 #define MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \
4724 (_MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4725 #define MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \
4726 (_MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4727 #define MX6Q_PAD_DI0_PIN15__GPIO_4_17 \
4728 (_MX6Q_PAD_DI0_PIN15__GPIO_4_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4729 #define MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \
4730 (_MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4732 #define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \
4733 (_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4734 #define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \
4735 (_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4736 #define MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \
4737 (_MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
4738 #define MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \
4739 (_MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
4740 #define MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \
4741 (_MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4742 #define MX6Q_PAD_DI0_PIN2__GPIO_4_18 \
4743 (_MX6Q_PAD_DI0_PIN2__GPIO_4_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4744 #define MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \
4745 (_MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4746 #define MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \
4747 (_MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4749 #define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \
4750 (_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4751 #define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \
4752 (_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4753 #define MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \
4754 (_MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
4755 #define MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \
4756 (_MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4757 #define MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \
4758 (_MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4759 #define MX6Q_PAD_DI0_PIN3__GPIO_4_19 \
4760 (_MX6Q_PAD_DI0_PIN3__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4761 #define MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \
4762 (_MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4763 #define MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \
4764 (_MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4766 #define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \
4767 (_MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4768 #define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \
4769 (_MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4770 #define MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \
4771 (_MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
4772 #define MX6Q_PAD_DI0_PIN4__USDHC1_WP \
4773 (_MX6Q_PAD_DI0_PIN4__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4774 #define MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \
4775 (_MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL))
4776 #define MX6Q_PAD_DI0_PIN4__GPIO_4_20 \
4777 (_MX6Q_PAD_DI0_PIN4__GPIO_4_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4778 #define MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \
4779 (_MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4780 #define MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \
4781 (_MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4783 #define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \
4784 (_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4785 #define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \
4786 (_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4787 #define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \
4788 (_MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4789 #define MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \
4790 (_MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4791 #define MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \
4792 (_MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL))
4793 #define MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \
4794 (_MX6Q_PAD_DISP0_DAT0__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4795 #define MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \
4796 (_MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4798 #define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \
4799 (_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4800 #define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \
4801 (_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4802 #define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \
4803 (_MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
4804 #define MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \
4805 (_MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4806 #define MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
4807 (_MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
4808 #define MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \
4809 (_MX6Q_PAD_DISP0_DAT1__GPIO_4_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4810 #define MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \
4811 (_MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4812 #define MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \
4813 (_MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4815 #define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \
4816 (_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4817 #define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \
4818 (_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4819 #define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \
4820 (_MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
4821 #define MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \
4822 (_MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4823 #define MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \
4824 (_MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
4825 #define MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \
4826 (_MX6Q_PAD_DISP0_DAT2__GPIO_4_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4827 #define MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \
4828 (_MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4829 #define MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \
4830 (_MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4832 #define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \
4833 (_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4834 #define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \
4835 (_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4836 #define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \
4837 (_MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4838 #define MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \
4839 (_MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4840 #define MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \
4841 (_MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
4842 #define MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \
4843 (_MX6Q_PAD_DISP0_DAT3__GPIO_4_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4844 #define MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \
4845 (_MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4846 #define MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \
4847 (_MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4849 #define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \
4850 (_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4851 #define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \
4852 (_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4853 #define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \
4854 (_MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4855 #define MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \
4856 (_MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4857 #define MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \
4858 (_MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL))
4859 #define MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \
4860 (_MX6Q_PAD_DISP0_DAT4__GPIO_4_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4861 #define MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \
4862 (_MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4863 #define MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \
4864 (_MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4866 #define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \
4867 (_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4868 #define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \
4869 (_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4870 #define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \
4871 (_MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4872 #define MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \
4873 (_MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
4874 #define MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \
4875 (_MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL))
4876 #define MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \
4877 (_MX6Q_PAD_DISP0_DAT5__GPIO_4_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4878 #define MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \
4879 (_MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4880 #define MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \
4881 (_MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4883 #define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \
4884 (_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4885 #define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \
4886 (_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4887 #define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \
4888 (_MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4889 #define MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \
4890 (_MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
4891 #define MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \
4892 (_MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
4893 #define MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \
4894 (_MX6Q_PAD_DISP0_DAT6__GPIO_4_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4895 #define MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \
4896 (_MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4897 #define MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \
4898 (_MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4900 #define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \
4901 (_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4902 #define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \
4903 (_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4904 #define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \
4905 (_MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
4906 #define MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \
4907 (_MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4908 #define MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \
4909 (_MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4910 #define MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \
4911 (_MX6Q_PAD_DISP0_DAT7__GPIO_4_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4912 #define MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \
4913 (_MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4914 #define MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \
4915 (_MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4917 #define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \
4918 (_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4919 #define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \
4920 (_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4921 #define MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \
4922 (_MX6Q_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
4923 #define MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \
4924 (_MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
4925 #define MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \
4926 (_MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4927 #define MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \
4928 (_MX6Q_PAD_DISP0_DAT8__GPIO_4_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4929 #define MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \
4930 (_MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4931 #define MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \
4932 (_MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4934 #define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \
4935 (_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4936 #define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \
4937 (_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4938 #define MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \
4939 (_MX6Q_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
4940 #define MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \
4941 (_MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
4942 #define MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \
4943 (_MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4944 #define MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \
4945 (_MX6Q_PAD_DISP0_DAT9__GPIO_4_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
4946 #define MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \
4947 (_MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4948 #define MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \
4949 (_MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4951 #define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \
4952 (_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4953 #define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \
4954 (_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4955 #define MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \
4956 (_MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4957 #define MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
4958 (_MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4959 #define MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \
4960 (_MX6Q_PAD_DISP0_DAT10__GPIO_4_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4961 #define MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \
4962 (_MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4963 #define MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \
4964 (_MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4966 #define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \
4967 (_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4968 #define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \
4969 (_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4970 #define MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \
4971 (_MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4972 #define MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
4973 (_MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4974 #define MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \
4975 (_MX6Q_PAD_DISP0_DAT11__GPIO_5_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4976 #define MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \
4977 (_MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4978 #define MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \
4979 (_MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4981 #define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \
4982 (_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4983 #define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \
4984 (_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4985 #define MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED \
4986 (_MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4987 #define MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
4988 (_MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4989 #define MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \
4990 (_MX6Q_PAD_DISP0_DAT12__GPIO_5_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4991 #define MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \
4992 (_MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4993 #define MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \
4994 (_MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4996 #define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \
4997 (_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4998 #define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \
4999 (_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5000 #define MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \
5001 (_MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
5002 #define MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
5003 (_MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5004 #define MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \
5005 (_MX6Q_PAD_DISP0_DAT13__GPIO_5_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5006 #define MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \
5007 (_MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
5008 #define MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \
5009 (_MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
5011 #define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \
5012 (_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5013 #define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \
5014 (_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5015 #define MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \
5016 (_MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
5017 #define MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
5018 (_MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5019 #define MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \
5020 (_MX6Q_PAD_DISP0_DAT14__GPIO_5_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5021 #define MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \
5022 (_MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
5024 #define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \
5025 (_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5026 #define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \
5027 (_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5028 #define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \
5029 (_MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5030 #define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \
5031 (_MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5032 #define MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
5033 (_MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5034 #define MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \
5035 (_MX6Q_PAD_DISP0_DAT15__GPIO_5_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
5036 #define MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \
5037 (_MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
5038 #define MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \
5039 (_MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
5041 #define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \
5042 (_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5043 #define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \
5044 (_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5045 #define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \
5046 (_MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
5047 #define MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \
5048 (_MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
5049 #define MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \
5050 (_MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5051 #define MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \
5052 (_MX6Q_PAD_DISP0_DAT16__GPIO_5_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
5053 #define MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \
5054 (_MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
5055 #define MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \
5056 (_MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
5058 #define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \
5059 (_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5060 #define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \
5061 (_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5062 #define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \
5063 (_MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
5064 #define MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \
5065 (_MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5066 #define MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \
5067 (_MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5068 #define MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \
5069 (_MX6Q_PAD_DISP0_DAT17__GPIO_5_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
5070 #define MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \
5071 (_MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
5072 #define MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \
5073 (_MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
5075 #define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \
5076 (_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5077 #define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \
5078 (_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5079 #define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \
5080 (_MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5081 #define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \
5082 (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
5083 #define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \
5084 (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
5085 #define MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \
5086 (_MX6Q_PAD_DISP0_DAT18__GPIO_5_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
5087 #define MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \
5088 (_MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
5089 #define MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \
5090 (_MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5092 #define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \
5093 (_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5094 #define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \
5095 (_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5096 #define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \
5097 (_MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5098 #define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \
5099 (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5100 #define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \
5101 (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
5102 #define MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \
5103 (_MX6Q_PAD_DISP0_DAT19__GPIO_5_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
5104 #define MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \
5105 (_MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
5106 #define MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \
5107 (_MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5109 #define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \
5110 (_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5111 #define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \
5112 (_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5113 #define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \
5114 (_MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5115 #define MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \
5116 (_MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
5117 #define MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
5118 (_MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5119 #define MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \
5120 (_MX6Q_PAD_DISP0_DAT20__GPIO_5_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
5121 #define MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \
5122 (_MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
5123 #define MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \
5124 (_MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
5126 #define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \
5127 (_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5128 #define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \
5129 (_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5130 #define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \
5131 (_MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
5132 #define MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \
5133 (_MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5134 #define MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \
5135 (_MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5136 #define MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \
5137 (_MX6Q_PAD_DISP0_DAT21__GPIO_5_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
5138 #define MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \
5139 (_MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
5140 #define MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \
5141 (_MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
5143 #define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \
5144 (_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5145 #define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \
5146 (_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5147 #define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \
5148 (_MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
5149 #define MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \
5150 (_MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
5151 #define MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \
5152 (_MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5153 #define MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \
5154 (_MX6Q_PAD_DISP0_DAT22__GPIO_5_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
5155 #define MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \
5156 (_MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
5157 #define MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \
5158 (_MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
5160 #define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \
5161 (_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5162 #define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \
5163 (_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5164 #define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \
5165 (_MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5166 #define MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \
5167 (_MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5168 #define MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \
5169 (_MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5170 #define MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \
5171 (_MX6Q_PAD_DISP0_DAT23__GPIO_5_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
5172 #define MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \
5173 (_MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
5174 #define MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \
5175 (_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
5177 #define MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED \
5178 (_MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5179 #define MX6Q_PAD_ENET_MDIO__ENET_MDIO \
5180 (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
5181 #define MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \
5182 (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5183 #define MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \
5184 (_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5185 #define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \
5186 (_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5187 #define MX6Q_PAD_ENET_MDIO__GPIO_1_22 \
5188 (_MX6Q_PAD_ENET_MDIO__GPIO_1_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
5189 #define MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \
5190 (_MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
5192 #define MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED \
5193 (_MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5194 #define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \
5195 (_MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
5196 #define MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \
5197 (_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5198 #define MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \
5199 (_MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5200 #define MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \
5201 (_MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
5202 #define MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \
5203 (_MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5204 #define MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \
5205 (_MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))
5207 #define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \
5208 (_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
5209 #define MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \
5210 (_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5211 #define MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \
5212 (_MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5213 #define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \
5214 (_MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5215 #define MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \
5216 (_MX6Q_PAD_ENET_RX_ER__GPIO_1_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
5217 #define MX6Q_PAD_ENET_RX_ER__PHY_TDI \
5218 (_MX6Q_PAD_ENET_RX_ER__PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
5219 #define MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \
5220 (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5222 #define MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED \
5223 (_MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5224 #define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \
5225 (_MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
5226 #define MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \
5227 (_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5228 #define MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \
5229 (_MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5230 #define MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \
5231 (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
5232 #define MX6Q_PAD_ENET_CRS_DV__PHY_TDO \
5233 (_MX6Q_PAD_ENET_CRS_DV__PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
5234 #define MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \
5235 (_MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5237 #define MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \
5238 (_MX6Q_PAD_ENET_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
5239 #define MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \
5240 (_MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5241 #define MX6Q_PAD_ENET_RXD1__ESAI1_FST \
5242 (_MX6Q_PAD_ENET_RXD1__ESAI1_FST | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5243 #define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \
5244 (_MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5245 #define MX6Q_PAD_ENET_RXD1__GPIO_1_26 \
5246 (_MX6Q_PAD_ENET_RXD1__GPIO_1_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
5247 #define MX6Q_PAD_ENET_RXD1__PHY_TCK \
5248 (_MX6Q_PAD_ENET_RXD1__PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
5249 #define MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \
5250 (_MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))
5252 #define MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \
5253 (_MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5254 #define MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \
5255 (_MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5256 #define MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \
5257 (_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5258 #define MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \
5259 (_MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5260 #define MX6Q_PAD_ENET_RXD0__GPIO_1_27 \
5261 (_MX6Q_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
5262 #define MX6Q_PAD_ENET_RXD0__PHY_TMS \
5263 (_MX6Q_PAD_ENET_RXD0__PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
5264 #define MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \
5265 (_MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))
5267 #define MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED \
5268 (_MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5269 #define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \
5270 (_MX6Q_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
5271 #define MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \
5272 (_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5273 #define MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \
5274 (_MX6Q_PAD_ENET_TX_EN__GPIO_1_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
5275 #define MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \
5276 (_MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
5277 #define MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \
5278 (_MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))
5280 #define MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \
5281 (_MX6Q_PAD_ENET_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5282 #define MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \
5283 (_MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5284 #define MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \
5285 (_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5286 #define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \
5287 (_MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
5288 #define MX6Q_PAD_ENET_TXD1__GPIO_1_29 \
5289 (_MX6Q_PAD_ENET_TXD1__GPIO_1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
5290 #define MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \
5291 (_MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
5292 #define MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \
5293 (_MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5295 #define MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED \
5296 (_MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5297 #define MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \
5298 (_MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5299 #define MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \
5300 (_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5301 #define MX6Q_PAD_ENET_TXD0__GPIO_1_30 \
5302 (_MX6Q_PAD_ENET_TXD0__GPIO_1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
5303 #define MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \
5304 (_MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
5305 #define MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \
5306 (_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5308 #define MX6Q_PAD_ENET_MDC__MLB_MLBDAT \
5309 (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
5310 #define MX6Q_PAD_ENET_MDC__ENET_MDC \
5311 (_MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
5312 #define MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \
5313 (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
5314 #define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \
5315 (_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
5316 #define MX6Q_PAD_ENET_MDC__GPIO_1_31 \
5317 (_MX6Q_PAD_ENET_MDC__GPIO_1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
5318 #define MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \
5319 (_MX6Q_PAD_ENET_MDC__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
5320 #define MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \
5321 (_MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))
5323 #define MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \
5324 (_MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
5326 #define MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \
5327 (_MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
5329 #define MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \
5330 (_MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
5332 #define MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \
5333 (_MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
5335 #define MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \
5336 (_MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
5338 #define MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \
5339 (_MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
5341 #define MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \
5342 (_MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
5344 #define MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \
5345 (_MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
5347 #define MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \
5348 (_MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5350 #define MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \
5351 (_MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5353 #define MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \
5354 (_MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
5356 #define MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \
5357 (_MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
5359 #define MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \
5360 (_MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
5362 #define MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \
5363 (_MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
5365 #define MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \
5366 (_MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
5368 #define MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \
5369 (_MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
5371 #define MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \
5372 (_MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
5374 #define MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \
5375 (_MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
5377 #define MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \
5378 (_MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5380 #define MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \
5381 (_MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5383 #define MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \
5384 (_MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
5386 #define MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \
5387 (_MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
5389 #define MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \
5390 (_MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
5392 #define MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \
5393 (_MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
5395 #define MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \
5396 (_MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
5398 #define MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \
5399 (_MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
5401 #define MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \
5402 (_MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5404 #define MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \
5405 (_MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
5407 #define MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \
5408 (_MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
5410 #define MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \
5411 (_MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5413 #define MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \
5414 (_MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
5416 #define MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \
5417 (_MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
5419 #define MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \
5420 (_MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
5422 #define MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \
5423 (_MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
5425 #define MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \
5426 (_MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
5428 #define MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \
5429 (_MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
5431 #define MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \
5432 (_MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
5434 #define MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \
5435 (_MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5437 #define MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \
5438 (_MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
5440 #define MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \
5441 (_MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5443 #define MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \
5444 (_MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5446 #define MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \
5447 (_MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5449 #define MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \
5450 (_MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5452 #define MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \
5453 (_MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5455 #define MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \
5456 (_MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5458 #define MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \
5459 (_MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5461 #define MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \
5462 (_MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5464 #define MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \
5465 (_MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5467 #define MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \
5468 (_MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5470 #define MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \
5471 (_MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
5473 #define MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \
5474 (_MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
5476 #define MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \
5477 (_MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
5479 #define MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \
5480 (_MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
5482 #define MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \
5483 (_MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
5485 #define MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \
5486 (_MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
5488 #define MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \
5489 (_MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
5491 #define MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \
5492 (_MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS | MUX_PAD_CTRL(NO_PAD_CTRL))
5494 #define MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \
5495 (_MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5497 #define MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \
5498 (_MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5500 #define MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \
5501 (_MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS | MUX_PAD_CTRL(NO_PAD_CTRL))
5503 #define MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \
5504 (_MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET | MUX_PAD_CTRL(NO_PAD_CTRL))
5506 #define MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \
5507 (_MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5509 #define MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \
5510 (_MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5512 #define MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \
5513 (_MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5515 #define MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \
5516 (_MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5518 #define MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \
5519 (_MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5521 #define MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \
5522 (_MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5524 #define MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \
5525 (_MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5527 #define MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \
5528 (_MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5530 #define MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \
5531 (_MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5533 #define MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \
5534 (_MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE | MUX_PAD_CTRL(NO_PAD_CTRL))
5536 #define MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \
5537 (_MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5539 #define MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \
5540 (_MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5542 #define MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \
5543 (_MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5545 #define MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \
5546 (_MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5548 #define MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \
5549 (_MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5551 #define MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \
5552 (_MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5554 #define MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \
5555 (_MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5557 #define MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \
5558 (_MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5560 #define MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \
5561 (_MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5563 #define MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \
5564 (_MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5566 #define MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \
5567 (_MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5569 #define MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \
5570 (_MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
5572 #define MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \
5573 (_MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
5575 #define MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \
5576 (_MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
5578 #define MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \
5579 (_MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
5581 #define MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \
5582 (_MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
5584 #define MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \
5585 (_MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
5587 #define MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \
5588 (_MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5590 #define MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \
5591 (_MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
5593 #define MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \
5594 (_MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5596 #define MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \
5597 (_MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
5599 #define MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \
5600 (_MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
5602 #define MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \
5603 (_MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
5605 #define MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \
5606 (_MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 | MUX_PAD_CTRL(NO_PAD_CTRL))
5608 #define MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \
5609 (_MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 | MUX_PAD_CTRL(NO_PAD_CTRL))
5611 #define MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \
5612 (_MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 | MUX_PAD_CTRL(NO_PAD_CTRL))
5614 #define MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \
5615 (_MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 | MUX_PAD_CTRL(NO_PAD_CTRL))
5617 #define MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \
5618 (_MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 | MUX_PAD_CTRL(NO_PAD_CTRL))
5620 #define MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \
5621 (_MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5623 #define MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \
5624 (_MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5626 #define MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \
5627 (_MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 | MUX_PAD_CTRL(NO_PAD_CTRL))
5629 #define MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \
5630 (_MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5632 #define MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \
5633 (_MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 | MUX_PAD_CTRL(NO_PAD_CTRL))
5635 #define MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \
5636 (_MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 | MUX_PAD_CTRL(NO_PAD_CTRL))
5638 #define MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \
5639 (_MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 | MUX_PAD_CTRL(NO_PAD_CTRL))
5641 #define MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \
5642 (_MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 | MUX_PAD_CTRL(NO_PAD_CTRL))
5644 #define MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \
5645 (_MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5647 #define MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \
5648 (_MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 | MUX_PAD_CTRL(NO_PAD_CTRL))
5650 #define MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \
5651 (_MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 | MUX_PAD_CTRL(NO_PAD_CTRL))
5653 #define MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \
5654 (_MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 | MUX_PAD_CTRL(NO_PAD_CTRL))
5656 #define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \
5657 (_MX6Q_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5658 #define MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \
5659 (_MX6Q_PAD_KEY_COL0__ENET_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5660 #define MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \
5661 (_MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
5662 #define MX6Q_PAD_KEY_COL0__KPP_COL_0 \
5663 (_MX6Q_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5664 #define MX6Q_PAD_KEY_COL0__UART4_TXD \
5665 (_MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5666 #define MX6Q_PAD_KEY_COL0__UART4_RXD \
5667 (_MX6Q_PAD_KEY_COL0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5668 #define MX6Q_PAD_KEY_COL0__GPIO_4_6 \
5669 (_MX6Q_PAD_KEY_COL0__GPIO_4_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5670 #define MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \
5671 (_MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5672 #define MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \
5673 (_MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
5675 #define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \
5676 (_MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
5677 #define MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \
5678 (_MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5679 #define MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \
5680 (_MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5681 #define MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \
5682 (_MX6Q_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5683 #define MX6Q_PAD_KEY_ROW0__UART4_TXD \
5684 (_MX6Q_PAD_KEY_ROW0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5685 #define MX6Q_PAD_KEY_ROW0__UART4_RXD \
5686 (_MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5687 #define MX6Q_PAD_KEY_ROW0__GPIO_4_7 \
5688 (_MX6Q_PAD_KEY_ROW0__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5689 #define MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \
5690 (_MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5691 #define MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \
5692 (_MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5694 #define MX6Q_PAD_KEY_COL1__ECSPI1_MISO \
5695 (_MX6Q_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
5696 #define MX6Q_PAD_KEY_COL1__ENET_MDIO \
5697 (_MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
5698 #define MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \
5699 (_MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
5700 #define MX6Q_PAD_KEY_COL1__KPP_COL_1 \
5701 (_MX6Q_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5702 #define MX6Q_PAD_KEY_COL1__UART5_TXD \
5703 (_MX6Q_PAD_KEY_COL1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5704 #define MX6Q_PAD_KEY_COL1__UART5_RXD \
5705 (_MX6Q_PAD_KEY_COL1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5706 #define MX6Q_PAD_KEY_COL1__GPIO_4_8 \
5707 (_MX6Q_PAD_KEY_COL1__GPIO_4_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5708 #define MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \
5709 (_MX6Q_PAD_KEY_COL1__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5710 #define MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \
5711 (_MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5713 #define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \
5714 (_MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5715 #define MX6Q_PAD_KEY_ROW1__ENET_COL \
5716 (_MX6Q_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
5717 #define MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \
5718 (_MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5719 #define MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \
5720 (_MX6Q_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5721 #define MX6Q_PAD_KEY_ROW1__UART5_TXD \
5722 (_MX6Q_PAD_KEY_ROW1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5723 #define MX6Q_PAD_KEY_ROW1__UART5_RXD \
5724 (_MX6Q_PAD_KEY_ROW1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5725 #define MX6Q_PAD_KEY_ROW1__GPIO_4_9 \
5726 (_MX6Q_PAD_KEY_ROW1__GPIO_4_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
5727 #define MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \
5728 (_MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5729 #define MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \
5730 (_MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5732 #define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \
5733 (_MX6Q_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5734 #define MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \
5735 (_MX6Q_PAD_KEY_COL2__ENET_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5736 #define MX6Q_PAD_KEY_COL2__CAN1_TXCAN \
5737 (_MX6Q_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5738 #define MX6Q_PAD_KEY_COL2__KPP_COL_2 \
5739 (_MX6Q_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5740 #define MX6Q_PAD_KEY_COL2__ENET_MDC \
5741 (_MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
5742 #define MX6Q_PAD_KEY_COL2__GPIO_4_10 \
5743 (_MX6Q_PAD_KEY_COL2__GPIO_4_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
5744 #define MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \
5745 (_MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))
5746 #define MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \
5747 (_MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5749 #define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \
5750 (_MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5751 #define MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \
5752 (_MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5753 #define MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \
5754 (_MX6Q_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5755 #define MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \
5756 (_MX6Q_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5757 #define MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \
5758 (_MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5759 #define MX6Q_PAD_KEY_ROW2__GPIO_4_11 \
5760 (_MX6Q_PAD_KEY_ROW2__GPIO_4_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
5761 #define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \
5762 (_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
5763 #define MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \
5764 (_MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5766 #define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \
5767 (_MX6Q_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5768 #define MX6Q_PAD_KEY_COL3__ENET_CRS \
5769 (_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
5770 #define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \
5771 (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
5772 #define MX6Q_PAD_KEY_COL3__KPP_COL_3 \
5773 (_MX6Q_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5774 #define MX6Q_PAD_KEY_COL3__I2C2_SCL \
5775 (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
5776 #define MX6Q_PAD_KEY_COL3__GPIO_4_12 \
5777 (_MX6Q_PAD_KEY_COL3__GPIO_4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
5778 #define MX6Q_PAD_KEY_COL3__SPDIF_IN1 \
5779 (_MX6Q_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5780 #define MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \
5781 (_MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5783 #define MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \
5784 (_MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5785 #define MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \
5786 (_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5787 #define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \
5788 (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
5789 #define MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \
5790 (_MX6Q_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5791 #define MX6Q_PAD_KEY_ROW3__I2C2_SDA \
5792 (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
5793 #define MX6Q_PAD_KEY_ROW3__GPIO_4_13 \
5794 (_MX6Q_PAD_KEY_ROW3__GPIO_4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
5795 #define MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \
5796 (_MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5797 #define MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \
5798 (_MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5800 #define MX6Q_PAD_KEY_COL4__CAN2_TXCAN \
5801 (_MX6Q_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5802 #define MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \
5803 (_MX6Q_PAD_KEY_COL4__IPU1_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5804 #define MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \
5805 (_MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
5806 #define MX6Q_PAD_KEY_COL4__KPP_COL_4 \
5807 (_MX6Q_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5808 #define MX6Q_PAD_KEY_COL4__UART5_CTS \
5809 (_MX6Q_PAD_KEY_COL4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5810 #define MX6Q_PAD_KEY_COL4__UART5_RTS \
5811 (_MX6Q_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5812 #define MX6Q_PAD_KEY_COL4__GPIO_4_14 \
5813 (_MX6Q_PAD_KEY_COL4__GPIO_4_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
5814 #define MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \
5815 (_MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
5816 #define MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \
5817 (_MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5819 #define MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \
5820 (_MX6Q_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5821 #define MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \
5822 (_MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5823 #define MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \
5824 (_MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
5825 #define MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \
5826 (_MX6Q_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5827 #define MX6Q_PAD_KEY_ROW4__UART5_CTS \
5828 (_MX6Q_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5829 #define MX6Q_PAD_KEY_ROW4__GPIO_4_15 \
5830 (_MX6Q_PAD_KEY_ROW4__GPIO_4_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
5831 #define MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \
5832 (_MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
5833 #define MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \
5834 (_MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5836 #define MX6Q_PAD_GPIO_0__CCM_CLKO \
5837 (_MX6Q_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(MX6Q_CCM_CLK0_PAD_CTRL))
5838 #define MX6Q_PAD_GPIO_0__KPP_COL_5 \
5839 (_MX6Q_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5840 #define MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \
5841 (_MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5842 #define MX6Q_PAD_GPIO_0__EPIT1_EPITO \
5843 (_MX6Q_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
5844 #define MX6Q_PAD_GPIO_0__GPIO_1_0 \
5845 (_MX6Q_PAD_GPIO_0__GPIO_1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5846 #define MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \
5847 (_MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
5848 #define MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \
5849 (_MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5851 #define MX6Q_PAD_GPIO_1__ESAI1_SCKR \
5852 (_MX6Q_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
5853 #define MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \
5854 (_MX6Q_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
5855 #define MX6Q_PAD_GPIO_1__KPP_ROW_5 \
5856 (_MX6Q_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5857 #define MX6Q_PAD_GPIO_1__PWM2_PWMO \
5858 (_MX6Q_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
5859 #define MX6Q_PAD_GPIO_1__GPIO_1_1 \
5860 (_MX6Q_PAD_GPIO_1__GPIO_1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5861 #define MX6Q_PAD_GPIO_1__USDHC1_CD \
5862 (_MX6Q_PAD_GPIO_1__USDHC1_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5863 #define MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \
5864 (_MX6Q_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL))
5866 #define MX6Q_PAD_GPIO_9__ESAI1_FSR \
5867 (_MX6Q_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
5868 #define MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \
5869 (_MX6Q_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
5870 #define MX6Q_PAD_GPIO_9__KPP_COL_6 \
5871 (_MX6Q_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5872 #define MX6Q_PAD_GPIO_9__CCM_REF_EN_B \
5873 (_MX6Q_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
5874 #define MX6Q_PAD_GPIO_9__PWM1_PWMO \
5875 (_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
5876 #define MX6Q_PAD_GPIO_9__GPIO_1_9 \
5877 (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
5878 #define MX6Q_PAD_GPIO_9__USDHC1_WP \
5879 (_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5880 #define MX6Q_PAD_GPIO_9__SRC_EARLY_RST \
5881 (_MX6Q_PAD_GPIO_9__SRC_EARLY_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
5883 #define MX6Q_PAD_GPIO_3__ESAI1_HCKR \
5884 (_MX6Q_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
5885 #define MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \
5886 (_MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5887 #define MX6Q_PAD_GPIO_3__I2C3_SCL \
5888 (_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
5889 #define MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \
5890 (_MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5891 #define MX6Q_PAD_GPIO_3__CCM_CLKO2 \
5892 (_MX6Q_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5893 #define MX6Q_PAD_GPIO_3__GPIO_1_3 \
5894 (_MX6Q_PAD_GPIO_3__GPIO_1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5895 #define MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \
5896 (_MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
5897 #define MX6Q_PAD_GPIO_3__MLB_MLBCLK \
5898 (_MX6Q_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5900 #define MX6Q_PAD_GPIO_6__ESAI1_SCKT \
5901 (_MX6Q_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
5902 #define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
5903 (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5904 #define MX6Q_PAD_GPIO_6__I2C3_SDA \
5905 (_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
5906 #define MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \
5907 (_MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5908 #define MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \
5909 (_MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
5910 #define MX6Q_PAD_GPIO_6__GPIO_1_6 \
5911 (_MX6Q_PAD_GPIO_6__GPIO_1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5912 #define MX6Q_PAD_GPIO_6__USDHC2_LCTL \
5913 (_MX6Q_PAD_GPIO_6__USDHC2_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5914 #define MX6Q_PAD_GPIO_6__MLB_MLBSIG \
5915 (_MX6Q_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
5917 #define MX6Q_PAD_GPIO_2__ESAI1_FST \
5918 (_MX6Q_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
5919 #define MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \
5920 (_MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5921 #define MX6Q_PAD_GPIO_2__KPP_ROW_6 \
5922 (_MX6Q_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5923 #define MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \
5924 (_MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5925 #define MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \
5926 (_MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5927 #define MX6Q_PAD_GPIO_2__GPIO_1_2 \
5928 (_MX6Q_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5929 #define MX6Q_PAD_GPIO_2__USDHC2_WP \
5930 (_MX6Q_PAD_GPIO_2__USDHC2_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5931 #define MX6Q_PAD_GPIO_2__MLB_MLBDAT \
5932 (_MX6Q_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
5934 #define MX6Q_PAD_GPIO_4__ESAI1_HCKT \
5935 (_MX6Q_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
5936 #define MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \
5937 (_MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5938 #define MX6Q_PAD_GPIO_4__KPP_COL_7 \
5939 (_MX6Q_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5940 #define MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \
5941 (_MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5942 #define MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \
5943 (_MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5944 #define MX6Q_PAD_GPIO_4__GPIO_1_4 \
5945 (_MX6Q_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5946 #define MX6Q_PAD_GPIO_4__USDHC2_CD \
5947 (_MX6Q_PAD_GPIO_4__USDHC2_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5948 #define MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \
5949 (_MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED | MUX_PAD_CTRL(NO_PAD_CTRL))
5951 #define MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \
5952 (_MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5953 #define MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \
5954 (_MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5955 #define MX6Q_PAD_GPIO_5__KPP_ROW_7 \
5956 (_MX6Q_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5957 #define MX6Q_PAD_GPIO_5__CCM_CLKO \
5958 (_MX6Q_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
5959 #define MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \
5960 (_MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5961 #define MX6Q_PAD_GPIO_5__GPIO_1_5 \
5962 (_MX6Q_PAD_GPIO_5__GPIO_1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5963 #define MX6Q_PAD_GPIO_5__I2C3_SCL \
5964 (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
5965 #define MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \
5966 (_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI | MUX_PAD_CTRL(NO_PAD_CTRL))
5968 #define MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \
5969 (_MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5970 #define MX6Q_PAD_GPIO_7__ECSPI5_RDY \
5971 (_MX6Q_PAD_GPIO_7__ECSPI5_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
5972 #define MX6Q_PAD_GPIO_7__EPIT1_EPITO \
5973 (_MX6Q_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
5974 #define MX6Q_PAD_GPIO_7__CAN1_TXCAN \
5975 (_MX6Q_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5976 #define MX6Q_PAD_GPIO_7__UART2_TXD \
5977 (_MX6Q_PAD_GPIO_7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5978 #define MX6Q_PAD_GPIO_7__UART2_RXD \
5979 (_MX6Q_PAD_GPIO_7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5980 #define MX6Q_PAD_GPIO_7__GPIO_1_7 \
5981 (_MX6Q_PAD_GPIO_7__GPIO_1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5982 #define MX6Q_PAD_GPIO_7__SPDIF_PLOCK \
5983 (_MX6Q_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
5984 #define MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \
5985 (_MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
5987 #define MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \
5988 (_MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5989 #define MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \
5990 (_MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5991 #define MX6Q_PAD_GPIO_8__EPIT2_EPITO \
5992 (_MX6Q_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
5993 #define MX6Q_PAD_GPIO_8__CAN1_RXCAN \
5994 (_MX6Q_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5995 #define MX6Q_PAD_GPIO_8__UART2_TXD \
5996 (_MX6Q_PAD_GPIO_8__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5997 #define MX6Q_PAD_GPIO_8__UART2_RXD \
5998 (_MX6Q_PAD_GPIO_8__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5999 #define MX6Q_PAD_GPIO_8__GPIO_1_8 \
6000 (_MX6Q_PAD_GPIO_8__GPIO_1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6001 #define MX6Q_PAD_GPIO_8__SPDIF_SRCLK \
6002 (_MX6Q_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6003 #define MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \
6004 (_MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))
6006 #define MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \
6007 (_MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6008 #define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \
6009 (_MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
6010 #define MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
6011 (_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
6012 #define MX6Q_PAD_GPIO_16__USDHC1_LCTL \
6013 (_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6014 #define MX6Q_PAD_GPIO_16__SPDIF_IN1 \
6015 (_MX6Q_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6016 #define MX6Q_PAD_GPIO_16__GPIO_7_11 \
6017 (_MX6Q_PAD_GPIO_16__GPIO_7_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6018 #define MX6Q_PAD_GPIO_16__I2C3_SDA \
6019 (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
6020 #define MX6Q_PAD_GPIO_16__SJC_DE_B \
6021 (_MX6Q_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
6023 #define MX6Q_PAD_GPIO_17__ESAI1_TX0 \
6024 (_MX6Q_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6025 #define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \
6026 (_MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
6027 #define MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \
6028 (_MX6Q_PAD_GPIO_17__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
6029 #define MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \
6030 (_MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6031 #define MX6Q_PAD_GPIO_17__SPDIF_OUT1 \
6032 (_MX6Q_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6033 #define MX6Q_PAD_GPIO_17__GPIO_7_12 \
6034 (_MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6035 #define MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \
6036 (_MX6Q_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL))
6038 #define MX6Q_PAD_GPIO_18__ESAI1_TX1 \
6039 (_MX6Q_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6040 #define MX6Q_PAD_GPIO_18__ENET_RX_CLK \
6041 (_MX6Q_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6042 #define MX6Q_PAD_GPIO_18__USDHC3_VSELECT \
6043 (_MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6044 #define MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \
6045 (_MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6046 #define MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \
6047 (_MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6048 #define MX6Q_PAD_GPIO_18__GPIO_7_13 \
6049 (_MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6050 #define MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \
6051 (_MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL | MUX_PAD_CTRL(NO_PAD_CTRL))
6052 #define MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \
6053 (_MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
6055 #define MX6Q_PAD_GPIO_19__KPP_COL_5 \
6056 (_MX6Q_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6057 #define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \
6058 (_MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
6059 #define MX6Q_PAD_GPIO_19__SPDIF_OUT1 \
6060 (_MX6Q_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6061 #define MX6Q_PAD_GPIO_19__CCM_CLKO \
6062 (_MX6Q_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
6063 #define MX6Q_PAD_GPIO_19__ECSPI1_RDY \
6064 (_MX6Q_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
6065 #define MX6Q_PAD_GPIO_19__GPIO_4_5 \
6066 (_MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
6067 #define MX6Q_PAD_GPIO_19__ENET_TX_ER \
6068 (_MX6Q_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
6069 #define MX6Q_PAD_GPIO_19__SRC_INT_BOOT \
6070 (_MX6Q_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL))
6072 #define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \
6073 (_MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6074 #define MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \
6075 (_MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6076 #define MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \
6077 (_MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6078 #define MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \
6079 (_MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6080 #define MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \
6081 (_MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
6082 #define MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \
6083 (_MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO | MUX_PAD_CTRL(NO_PAD_CTRL))
6085 #define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \
6086 (_MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
6087 #define MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \
6088 (_MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6089 #define MX6Q_PAD_CSI0_MCLK__CCM_CLKO \
6090 (_MX6Q_PAD_CSI0_MCLK__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
6091 #define MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \
6092 (_MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6093 #define MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \
6094 (_MX6Q_PAD_CSI0_MCLK__GPIO_5_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6095 #define MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \
6096 (_MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
6097 #define MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \
6098 (_MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
6100 #define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \
6101 (_MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
6102 #define MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \
6103 (_MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6104 #define MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \
6105 (_MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6106 #define MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \
6107 (_MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6108 #define MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \
6109 (_MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
6110 #define MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \
6111 (_MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
6112 #define MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \
6113 (_MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6115 #define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \
6116 (_MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
6117 #define MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \
6118 (_MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6119 #define MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \
6120 (_MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6121 #define MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \
6122 (_MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6123 #define MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \
6124 (_MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
6125 #define MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \
6126 (_MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
6127 #define MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \
6128 (_MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6130 #define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \
6131 (_MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6132 #define MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \
6133 (_MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6134 #define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \
6135 (_MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6136 #define MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \
6137 (_MX6Q_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6138 #define MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \
6139 (_MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
6140 #define MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \
6141 (_MX6Q_PAD_CSI0_DAT4__GPIO_5_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
6142 #define MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \
6143 (_MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
6144 #define MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \
6145 (_MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6147 #define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \
6148 (_MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6149 #define MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \
6150 (_MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6151 #define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \
6152 (_MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
6153 #define MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \
6154 (_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6155 #define MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \
6156 (_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
6157 #define MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \
6158 (_MX6Q_PAD_CSI0_DAT5__GPIO_5_23 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
6159 #define MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \
6160 (_MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
6161 #define MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \
6162 (_MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6164 #define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \
6165 (_MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6166 #define MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \
6167 (_MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6168 #define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \
6169 (_MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
6170 #define MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \
6171 (_MX6Q_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6172 #define MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \
6173 (_MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
6174 #define MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \
6175 (_MX6Q_PAD_CSI0_DAT6__GPIO_5_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
6176 #define MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \
6177 (_MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
6178 #define MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \
6179 (_MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6181 #define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \
6182 (_MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6183 #define MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \
6184 (_MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6185 #define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \
6186 (_MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6187 #define MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \
6188 (_MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6189 #define MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \
6190 (_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
6191 #define MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \
6192 (_MX6Q_PAD_CSI0_DAT7__GPIO_5_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
6193 #define MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \
6194 (_MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
6195 #define MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \
6196 (_MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6198 #define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \
6199 (_MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6200 #define MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \
6201 (_MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6202 #define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \
6203 (_MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6204 #define MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \
6205 (_MX6Q_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6206 #define MX6Q_PAD_CSI0_DAT8__I2C1_SDA \
6207 (_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
6208 #define MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \
6209 (_MX6Q_PAD_CSI0_DAT8__GPIO_5_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
6210 #define MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \
6211 (_MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
6212 #define MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \
6213 (_MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6215 #define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \
6216 (_MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6217 #define MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \
6218 (_MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6219 #define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \
6220 (_MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
6221 #define MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \
6222 (_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6223 #define MX6Q_PAD_CSI0_DAT9__I2C1_SCL \
6224 (_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
6225 #define MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \
6226 (_MX6Q_PAD_CSI0_DAT9__GPIO_5_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
6227 #define MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \
6228 (_MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
6229 #define MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \
6230 (_MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6232 #define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \
6233 (_MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6234 #define MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \
6235 (_MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
6236 #define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \
6237 (_MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
6238 #define MX6Q_PAD_CSI0_DAT10__UART1_TXD \
6239 (_MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6240 #define MX6Q_PAD_CSI0_DAT10__UART1_RXD \
6241 (_MX6Q_PAD_CSI0_DAT10__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6242 #define MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \
6243 (_MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6244 #define MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \
6245 (_MX6Q_PAD_CSI0_DAT10__GPIO_5_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
6246 #define MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \
6247 (_MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
6248 #define MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \
6249 (_MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6251 #define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \
6252 (_MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6253 #define MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \
6254 (_MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
6255 #define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \
6256 (_MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6257 #define MX6Q_PAD_CSI0_DAT11__UART1_TXD \
6258 (_MX6Q_PAD_CSI0_DAT11__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6259 #define MX6Q_PAD_CSI0_DAT11__UART1_RXD \
6260 (_MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6261 #define MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \
6262 (_MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6263 #define MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \
6264 (_MX6Q_PAD_CSI0_DAT11__GPIO_5_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
6265 #define MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \
6266 (_MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
6267 #define MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \
6268 (_MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6270 #define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \
6271 (_MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6272 #define MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \
6273 (_MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6274 #define MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \
6275 (_MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6276 #define MX6Q_PAD_CSI0_DAT12__UART4_TXD \
6277 (_MX6Q_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6278 #define MX6Q_PAD_CSI0_DAT12__UART4_RXD \
6279 (_MX6Q_PAD_CSI0_DAT12__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6280 #define MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \
6281 (_MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6282 #define MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \
6283 (_MX6Q_PAD_CSI0_DAT12__GPIO_5_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
6284 #define MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \
6285 (_MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
6286 #define MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \
6287 (_MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6289 #define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \
6290 (_MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6291 #define MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \
6292 (_MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6293 #define MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \
6294 (_MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6295 #define MX6Q_PAD_CSI0_DAT13__UART4_TXD \
6296 (_MX6Q_PAD_CSI0_DAT13__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6297 #define MX6Q_PAD_CSI0_DAT13__UART4_RXD \
6298 (_MX6Q_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6299 #define MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \
6300 (_MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6301 #define MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \
6302 (_MX6Q_PAD_CSI0_DAT13__GPIO_5_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
6303 #define MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \
6304 (_MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
6305 #define MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \
6306 (_MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6308 #define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \
6309 (_MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6310 #define MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \
6311 (_MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6312 #define MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \
6313 (_MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6314 #define MX6Q_PAD_CSI0_DAT14__UART5_TXD \
6315 (_MX6Q_PAD_CSI0_DAT14__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6316 #define MX6Q_PAD_CSI0_DAT14__UART5_RXD \
6317 (_MX6Q_PAD_CSI0_DAT14__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6318 #define MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \
6319 (_MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6320 #define MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \
6321 (_MX6Q_PAD_CSI0_DAT14__GPIO_6_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6322 #define MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \
6323 (_MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
6324 #define MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \
6325 (_MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6327 #define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \
6328 (_MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6329 #define MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \
6330 (_MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6331 #define MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \
6332 (_MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6333 #define MX6Q_PAD_CSI0_DAT15__UART5_TXD \
6334 (_MX6Q_PAD_CSI0_DAT15__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6335 #define MX6Q_PAD_CSI0_DAT15__UART5_RXD \
6336 (_MX6Q_PAD_CSI0_DAT15__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6337 #define MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \
6338 (_MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6339 #define MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \
6340 (_MX6Q_PAD_CSI0_DAT15__GPIO_6_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6341 #define MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \
6342 (_MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
6343 #define MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \
6344 (_MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6346 #define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \
6347 (_MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6348 #define MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \
6349 (_MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6350 #define MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \
6351 (_MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
6352 #define MX6Q_PAD_CSI0_DAT16__UART4_CTS \
6353 (_MX6Q_PAD_CSI0_DAT16__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6354 #define MX6Q_PAD_CSI0_DAT16__UART4_RTS \
6355 (_MX6Q_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6356 #define MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \
6357 (_MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6358 #define MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \
6359 (_MX6Q_PAD_CSI0_DAT16__GPIO_6_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6360 #define MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \
6361 (_MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
6362 #define MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \
6363 (_MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6365 #define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \
6366 (_MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6367 #define MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \
6368 (_MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6369 #define MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \
6370 (_MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
6371 #define MX6Q_PAD_CSI0_DAT17__UART4_CTS \
6372 (_MX6Q_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6373 #define MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \
6374 (_MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6375 #define MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \
6376 (_MX6Q_PAD_CSI0_DAT17__GPIO_6_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6377 #define MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \
6378 (_MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
6379 #define MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \
6380 (_MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6382 #define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \
6383 (_MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6384 #define MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \
6385 (_MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6386 #define MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \
6387 (_MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
6388 #define MX6Q_PAD_CSI0_DAT18__UART5_CTS \
6389 (_MX6Q_PAD_CSI0_DAT18__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6390 #define MX6Q_PAD_CSI0_DAT18__UART5_RTS \
6391 (_MX6Q_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6392 #define MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \
6393 (_MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6394 #define MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \
6395 (_MX6Q_PAD_CSI0_DAT18__GPIO_6_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6396 #define MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \
6397 (_MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
6398 #define MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \
6399 (_MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6401 #define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \
6402 (_MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6403 #define MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \
6404 (_MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6405 #define MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \
6406 (_MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
6407 #define MX6Q_PAD_CSI0_DAT19__UART5_CTS \
6408 (_MX6Q_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6409 #define MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \
6410 (_MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6411 #define MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \
6412 (_MX6Q_PAD_CSI0_DAT19__GPIO_6_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6413 #define MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \
6414 (_MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
6415 #define MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \
6416 (_MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6418 #define MX6Q_PAD_JTAG_TMS__SJC_TMS \
6419 (_MX6Q_PAD_JTAG_TMS__SJC_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
6421 #define MX6Q_PAD_JTAG_MOD__SJC_MOD \
6422 (_MX6Q_PAD_JTAG_MOD__SJC_MOD | MUX_PAD_CTRL(NO_PAD_CTRL))
6424 #define MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \
6425 (_MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB | MUX_PAD_CTRL(NO_PAD_CTRL))
6427 #define MX6Q_PAD_JTAG_TDI__SJC_TDI \
6428 (_MX6Q_PAD_JTAG_TDI__SJC_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
6430 #define MX6Q_PAD_JTAG_TCK__SJC_TCK \
6431 (_MX6Q_PAD_JTAG_TCK__SJC_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
6433 #define MX6Q_PAD_JTAG_TDO__SJC_TDO \
6434 (_MX6Q_PAD_JTAG_TDO__SJC_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
6436 #define MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \
6437 (_MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6439 #define MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \
6440 (_MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6442 #define MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \
6443 (_MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6445 #define MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \
6446 (_MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6448 #define MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \
6449 (_MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6451 #define MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \
6452 (_MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6454 #define MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \
6455 (_MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6457 #define MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \
6458 (_MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6460 #define MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \
6461 (_MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6463 #define MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \
6464 (_MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6466 #define MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \
6467 (_MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6469 #define MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \
6470 (_MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM | MUX_PAD_CTRL(NO_PAD_CTRL))
6472 #define MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \
6473 (_MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ | MUX_PAD_CTRL(NO_PAD_CTRL))
6475 #define MX6Q_PAD_POR_B__SRC_POR_B \
6476 (_MX6Q_PAD_POR_B__SRC_POR_B | MUX_PAD_CTRL(NO_PAD_CTRL))
6478 #define MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \
6479 (_MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6481 #define MX6Q_PAD_RESET_IN_B__SRC_RESET_B \
6482 (_MX6Q_PAD_RESET_IN_B__SRC_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
6484 #define MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \
6485 (_MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6487 #define MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \
6488 (_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
6490 #define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ \
6491 (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6492 #define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_100MHZ \
6493 (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6494 #define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_200MHZ \
6495 (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6496 #define MX6Q_PAD_SD3_DAT7__UART1_TXD \
6497 (_MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6498 #define MX6Q_PAD_SD3_DAT7__UART1_RXD \
6499 (_MX6Q_PAD_SD3_DAT7__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6500 #define MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \
6501 (_MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
6502 #define MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \
6503 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6504 #define MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \
6505 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6506 #define MX6Q_PAD_SD3_DAT7__GPIO_6_17 \
6507 (_MX6Q_PAD_SD3_DAT7__GPIO_6_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6508 #define MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \
6509 (_MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6510 #define MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \
6511 (_MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))
6513 #define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ \
6514 (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6515 #define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_100MHZ \
6516 (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6517 #define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_200MHZ \
6518 (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6519 #define MX6Q_PAD_SD3_DAT6__UART1_TXD \
6520 (_MX6Q_PAD_SD3_DAT6__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6521 #define MX6Q_PAD_SD3_DAT6__UART1_RXD \
6522 (_MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6523 #define MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \
6524 (_MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
6525 #define MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \
6526 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6527 #define MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \
6528 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6529 #define MX6Q_PAD_SD3_DAT6__GPIO_6_18 \
6530 (_MX6Q_PAD_SD3_DAT6__GPIO_6_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6531 #define MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \
6532 (_MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6533 #define MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \
6534 (_MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6536 #define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ \
6537 (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6538 #define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_100MHZ \
6539 (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6540 #define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_200MHZ \
6541 (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6542 #define MX6Q_PAD_SD3_DAT5__UART2_TXD \
6543 (_MX6Q_PAD_SD3_DAT5__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6544 #define MX6Q_PAD_SD3_DAT5__UART2_RXD \
6545 (_MX6Q_PAD_SD3_DAT5__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6546 #define MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \
6547 (_MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
6548 #define MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \
6549 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6550 #define MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \
6551 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6552 #define MX6Q_PAD_SD3_DAT5__GPIO_7_0 \
6553 (_MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6554 #define MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \
6555 (_MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6556 #define MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \
6557 (_MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6559 #define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ \
6560 (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6561 #define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_100MHZ \
6562 (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6563 #define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_200MHZ \
6564 (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6565 #define MX6Q_PAD_SD3_DAT4__UART2_TXD \
6566 (_MX6Q_PAD_SD3_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6567 #define MX6Q_PAD_SD3_DAT4__UART2_RXD \
6568 (_MX6Q_PAD_SD3_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6569 #define MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \
6570 (_MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
6571 #define MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \
6572 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6573 #define MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \
6574 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6575 #define MX6Q_PAD_SD3_DAT4__GPIO_7_1 \
6576 (_MX6Q_PAD_SD3_DAT4__GPIO_7_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6577 #define MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \
6578 (_MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6579 #define MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \
6580 (_MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6582 #define MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ \
6583 (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6584 #define MX6Q_PAD_SD3_CMD__USDHC3_CMD_100MHZ \
6585 (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6586 #define MX6Q_PAD_SD3_CMD__USDHC3_CMD_200MHZ \
6587 (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6588 #define MX6Q_PAD_SD3_CMD__UART2_CTS \
6589 (_MX6Q_PAD_SD3_CMD__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6590 #define MX6Q_PAD_SD3_CMD__CAN1_TXCAN \
6591 (_MX6Q_PAD_SD3_CMD__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
6592 #define MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \
6593 (_MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6594 #define MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \
6595 (_MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6596 #define MX6Q_PAD_SD3_CMD__GPIO_7_2 \
6597 (_MX6Q_PAD_SD3_CMD__GPIO_7_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6598 #define MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \
6599 (_MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6600 #define MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \
6601 (_MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6603 #define MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ \
6604 (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6605 #define MX6Q_PAD_SD3_CLK__USDHC3_CLK_100MHZ \
6606 (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6607 #define MX6Q_PAD_SD3_CLK__USDHC3_CLK_200MHZ \
6608 (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6609 #define MX6Q_PAD_SD3_CLK__UART2_CTS \
6610 (_MX6Q_PAD_SD3_CLK__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6611 #define MX6Q_PAD_SD3_CLK__UART2_RTS \
6612 (_MX6Q_PAD_SD3_CLK__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6613 #define MX6Q_PAD_SD3_CLK__CAN1_RXCAN \
6614 (_MX6Q_PAD_SD3_CLK__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
6615 #define MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \
6616 (_MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6617 #define MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \
6618 (_MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6619 #define MX6Q_PAD_SD3_CLK__GPIO_7_3 \
6620 (_MX6Q_PAD_SD3_CLK__GPIO_7_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6621 #define MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \
6622 (_MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6623 #define MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \
6624 (_MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6626 #define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ \
6627 (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6628 #define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_100MHZ \
6629 (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6630 #define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_200MHZ \
6631 (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6632 #define MX6Q_PAD_SD3_DAT0__UART1_CTS \
6633 (_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6634 #define MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \
6635 (_MX6Q_PAD_SD3_DAT0__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
6636 #define MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
6637 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6638 #define MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \
6639 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6640 #define MX6Q_PAD_SD3_DAT0__GPIO_7_4 \
6641 (_MX6Q_PAD_SD3_DAT0__GPIO_7_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6642 #define MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \
6643 (_MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6644 #define MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \
6645 (_MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6647 #define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ \
6648 (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6649 #define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_100MHZ \
6650 (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6651 #define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_200MHZ \
6652 (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6653 #define MX6Q_PAD_SD3_DAT1__UART1_CTS \
6654 (_MX6Q_PAD_SD3_DAT1__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6655 #define MX6Q_PAD_SD3_DAT1__UART1_RTS \
6656 (_MX6Q_PAD_SD3_DAT1__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6657 #define MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \
6658 (_MX6Q_PAD_SD3_DAT1__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
6659 #define MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \
6660 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6661 #define MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \
6662 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6663 #define MX6Q_PAD_SD3_DAT1__GPIO_7_5 \
6664 (_MX6Q_PAD_SD3_DAT1__GPIO_7_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6665 #define MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \
6666 (_MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6667 #define MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \
6668 (_MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6670 #define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ \
6671 (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6672 #define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_100MHZ \
6673 (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6674 #define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_200MHZ \
6675 (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6676 #define MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \
6677 (_MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
6678 #define MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \
6679 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6680 #define MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \
6681 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6682 #define MX6Q_PAD_SD3_DAT2__GPIO_7_6 \
6683 (_MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6684 #define MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \
6685 (_MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
6686 #define MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \
6687 (_MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6689 #define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ \
6690 (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6691 #define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_100MHZ \
6692 (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6693 #define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_200MHZ \
6694 (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6695 #define MX6Q_PAD_SD3_DAT3__UART3_CTS \
6696 (_MX6Q_PAD_SD3_DAT3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6697 #define MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \
6698 (_MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
6699 #define MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \
6700 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6701 #define MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \
6702 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6703 #define MX6Q_PAD_SD3_DAT3__GPIO_7_7 \
6704 (_MX6Q_PAD_SD3_DAT3__GPIO_7_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6705 #define MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \
6706 (_MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
6707 #define MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \
6708 (_MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6710 #define MX6Q_PAD_SD3_RST__USDHC3_RST \
6711 (_MX6Q_PAD_SD3_RST__USDHC3_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6712 #define MX6Q_PAD_SD3_RST__UART3_CTS \
6713 (_MX6Q_PAD_SD3_RST__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6714 #define MX6Q_PAD_SD3_RST__UART3_RTS \
6715 (_MX6Q_PAD_SD3_RST__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6716 #define MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \
6717 (_MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
6718 #define MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \
6719 (_MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6720 #define MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \
6721 (_MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6722 #define MX6Q_PAD_SD3_RST__GPIO_7_8 \
6723 (_MX6Q_PAD_SD3_RST__GPIO_7_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6724 #define MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \
6725 (_MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
6726 #define MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \
6727 (_MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6729 #define MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \
6730 (_MX6Q_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6731 #define MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \
6732 (_MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6733 #define MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \
6734 (_MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
6735 #define MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \
6736 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6737 #define MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \
6738 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6739 #define MX6Q_PAD_NANDF_CLE__GPIO_6_7 \
6740 (_MX6Q_PAD_NANDF_CLE__GPIO_6_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6741 #define MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \
6742 (_MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
6743 #define MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \
6744 (_MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6746 #define MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \
6747 (_MX6Q_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6748 #define MX6Q_PAD_NANDF_ALE__USDHC4_RST \
6749 (_MX6Q_PAD_NANDF_ALE__USDHC4_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6750 #define MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \
6751 (_MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6752 #define MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \
6753 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6754 #define MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \
6755 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6756 #define MX6Q_PAD_NANDF_ALE__GPIO_6_8 \
6757 (_MX6Q_PAD_NANDF_ALE__GPIO_6_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6758 #define MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \
6759 (_MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
6760 #define MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \
6761 (_MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6763 #define MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \
6764 (_MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6765 #define MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \
6766 (_MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6767 #define MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \
6768 (_MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6769 #define MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \
6770 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6771 #define MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \
6772 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6773 #define MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \
6774 (_MX6Q_PAD_NANDF_WP_B__GPIO_6_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6775 #define MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \
6776 (_MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
6777 #define MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \
6778 (_MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6780 #define MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \
6781 (_MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL0))
6782 #define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \
6783 (_MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6784 #define MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \
6785 (_MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6786 #define MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \
6787 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6788 #define MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \
6789 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6790 #define MX6Q_PAD_NANDF_RB0__GPIO_6_10 \
6791 (_MX6Q_PAD_NANDF_RB0__GPIO_6_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6792 #define MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \
6793 (_MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
6794 #define MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \
6795 (_MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6797 #define MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \
6798 (_MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6799 #define MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \
6800 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6801 #define MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \
6802 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6803 #define MX6Q_PAD_NANDF_CS0__GPIO_6_11 \
6804 (_MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6805 #define MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \
6806 (_MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6808 #define MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \
6809 (_MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6810 #define MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \
6811 (_MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6812 #define MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \
6813 (_MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6814 #define MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \
6815 (_MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6816 #define MX6Q_PAD_NANDF_CS1__GPIO_6_14 \
6817 (_MX6Q_PAD_NANDF_CS1__GPIO_6_14 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6818 #define MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \
6819 (_MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT | MUX_PAD_CTRL(NO_PAD_CTRL))
6821 #define MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \
6822 (_MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6823 #define MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \
6824 (_MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6825 #define MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \
6826 (_MX6Q_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
6827 #define MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \
6828 (_MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
6829 #define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \
6830 (_MX6Q_PAD_NANDF_CS2__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6831 #define MX6Q_PAD_NANDF_CS2__GPIO_6_15 \
6832 (_MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6833 #define MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \
6834 (_MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6836 #define MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \
6837 (_MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6838 #define MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \
6839 (_MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6840 #define MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \
6841 (_MX6Q_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
6842 #define MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \
6843 (_MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
6844 #define MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \
6845 (_MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6846 #define MX6Q_PAD_NANDF_CS3__GPIO_6_16 \
6847 (_MX6Q_PAD_NANDF_CS3__GPIO_6_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6848 #define MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \
6849 (_MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6850 #define MX6Q_PAD_NANDF_CS3__TPSMP_CLK \
6851 (_MX6Q_PAD_NANDF_CS3__TPSMP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6853 #define MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ \
6854 (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6855 #define MX6Q_PAD_SD4_CMD__USDHC4_CMD_100MHZ \
6856 (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6857 #define MX6Q_PAD_SD4_CMD__USDHC4_CMD_200MHZ \
6858 (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6859 #define MX6Q_PAD_SD4_CMD__RAWNAND_RDN \
6860 (_MX6Q_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6861 #define MX6Q_PAD_SD4_CMD__UART3_TXD \
6862 (_MX6Q_PAD_SD4_CMD__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6863 #define MX6Q_PAD_SD4_CMD__UART3_RXD \
6864 (_MX6Q_PAD_SD4_CMD__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6865 #define MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \
6866 (_MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6867 #define MX6Q_PAD_SD4_CMD__GPIO_7_9 \
6868 (_MX6Q_PAD_SD4_CMD__GPIO_7_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6869 #define MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \
6870 (_MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
6872 #define MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ \
6873 (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6874 #define MX6Q_PAD_SD4_CLK__USDHC4_CLK_100MHZ \
6875 (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
6876 #define MX6Q_PAD_SD4_CLK__USDHC4_CLK_200MHZ \
6877 (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
6878 #define MX6Q_PAD_SD4_CLK__RAWNAND_WRN \
6879 (_MX6Q_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6880 #define MX6Q_PAD_SD4_CLK__UART3_TXD \
6881 (_MX6Q_PAD_SD4_CLK__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6882 #define MX6Q_PAD_SD4_CLK__UART3_RXD \
6883 (_MX6Q_PAD_SD4_CLK__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6884 #define MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \
6885 (_MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6886 #define MX6Q_PAD_SD4_CLK__GPIO_7_10 \
6887 (_MX6Q_PAD_SD4_CLK__GPIO_7_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6889 #define MX6Q_PAD_NANDF_D0__RAWNAND_D0 \
6890 (_MX6Q_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6891 #define MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \
6892 (_MX6Q_PAD_NANDF_D0__USDHC1_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6893 #define MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \
6894 (_MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6895 #define MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \
6896 (_MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6897 #define MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \
6898 (_MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6899 #define MX6Q_PAD_NANDF_D0__GPIO_2_0 \
6900 (_MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6901 #define MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \
6902 (_MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6903 #define MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \
6904 (_MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6906 #define MX6Q_PAD_NANDF_D1__RAWNAND_D1 \
6907 (_MX6Q_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6908 #define MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \
6909 (_MX6Q_PAD_NANDF_D1__USDHC1_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6910 #define MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \
6911 (_MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6912 #define MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \
6913 (_MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6914 #define MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \
6915 (_MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6916 #define MX6Q_PAD_NANDF_D1__GPIO_2_1 \
6917 (_MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6918 #define MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \
6919 (_MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6920 #define MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \
6921 (_MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6923 #define MX6Q_PAD_NANDF_D2__RAWNAND_D2 \
6924 (_MX6Q_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6925 #define MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \
6926 (_MX6Q_PAD_NANDF_D2__USDHC1_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6927 #define MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \
6928 (_MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6929 #define MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \
6930 (_MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6931 #define MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \
6932 (_MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6933 #define MX6Q_PAD_NANDF_D2__GPIO_2_2 \
6934 (_MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6935 #define MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \
6936 (_MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6937 #define MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \
6938 (_MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6940 #define MX6Q_PAD_NANDF_D3__RAWNAND_D3 \
6941 (_MX6Q_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6942 #define MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \
6943 (_MX6Q_PAD_NANDF_D3__USDHC1_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6944 #define MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \
6945 (_MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6946 #define MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \
6947 (_MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6948 #define MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \
6949 (_MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6950 #define MX6Q_PAD_NANDF_D3__GPIO_2_3 \
6951 (_MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6952 #define MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \
6953 (_MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6954 #define MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \
6955 (_MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6957 #define MX6Q_PAD_NANDF_D4__RAWNAND_D4 \
6958 (_MX6Q_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6959 #define MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \
6960 (_MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6961 #define MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \
6962 (_MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6963 #define MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \
6964 (_MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
6965 #define MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \
6966 (_MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
6967 #define MX6Q_PAD_NANDF_D4__GPIO_2_4 \
6968 (_MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6969 #define MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \
6970 (_MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6971 #define MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \
6972 (_MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6974 #define MX6Q_PAD_NANDF_D5__RAWNAND_D5 \
6975 (_MX6Q_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6976 #define MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \
6977 (_MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6978 #define MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \
6979 (_MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6980 #define MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \
6981 (_MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
6982 #define MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \
6983 (_MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
6984 #define MX6Q_PAD_NANDF_D5__GPIO_2_5 \
6985 (_MX6Q_PAD_NANDF_D5__GPIO_2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6986 #define MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \
6987 (_MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6988 #define MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \
6989 (_MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6991 #define MX6Q_PAD_NANDF_D6__RAWNAND_D6 \
6992 (_MX6Q_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
6993 #define MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \
6994 (_MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6995 #define MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \
6996 (_MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6997 #define MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \
6998 (_MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
6999 #define MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \
7000 (_MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
7001 #define MX6Q_PAD_NANDF_D6__GPIO_2_6 \
7002 (_MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
7003 #define MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \
7004 (_MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
7005 #define MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \
7006 (_MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
7008 #define MX6Q_PAD_NANDF_D7__RAWNAND_D7 \
7009 (_MX6Q_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
7010 #define MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \
7011 (_MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7012 #define MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \
7013 (_MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
7014 #define MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \
7015 (_MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
7016 #define MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \
7017 (_MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
7018 #define MX6Q_PAD_NANDF_D7__GPIO_2_7 \
7019 (_MX6Q_PAD_NANDF_D7__GPIO_2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
7020 #define MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \
7021 (_MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
7022 #define MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \
7023 (_MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
7025 #define MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \
7026 (_MX6Q_PAD_SD4_DAT0__RAWNAND_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
7027 #define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ \
7028 (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7029 #define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_100MHZ \
7030 (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7031 #define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_200MHZ \
7032 (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7033 #define MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \
7034 (_MX6Q_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL1))
7035 #define MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \
7036 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
7037 #define MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \
7038 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
7039 #define MX6Q_PAD_SD4_DAT0__GPIO_2_8 \
7040 (_MX6Q_PAD_SD4_DAT0__GPIO_2_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
7041 #define MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \
7042 (_MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
7043 #define MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \
7044 (_MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
7046 #define MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \
7047 (_MX6Q_PAD_SD4_DAT1__RAWNAND_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
7048 #define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ \
7049 (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7050 #define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_100MHZ \
7051 (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7052 #define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_200MHZ \
7053 (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7054 #define MX6Q_PAD_SD4_DAT1__PWM3_PWMO \
7055 (_MX6Q_PAD_SD4_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7056 #define MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \
7057 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
7058 #define MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \
7059 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
7060 #define MX6Q_PAD_SD4_DAT1__GPIO_2_9 \
7061 (_MX6Q_PAD_SD4_DAT1__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
7062 #define MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \
7063 (_MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
7064 #define MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \
7065 (_MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
7067 #define MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \
7068 (_MX6Q_PAD_SD4_DAT2__RAWNAND_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7069 #define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ \
7070 (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7071 #define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_100MHZ \
7072 (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7073 #define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_200MHZ \
7074 (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7075 #define MX6Q_PAD_SD4_DAT2__PWM4_PWMO \
7076 (_MX6Q_PAD_SD4_DAT2__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7077 #define MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \
7078 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
7079 #define MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \
7080 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
7081 #define MX6Q_PAD_SD4_DAT2__GPIO_2_10 \
7082 (_MX6Q_PAD_SD4_DAT2__GPIO_2_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7083 #define MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \
7084 (_MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7085 #define MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \
7086 (_MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7088 #define MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \
7089 (_MX6Q_PAD_SD4_DAT3__RAWNAND_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7090 #define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ \
7091 (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7092 #define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_100MHZ \
7093 (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7094 #define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_200MHZ \
7095 (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7096 #define MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \
7097 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
7098 #define MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \
7099 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
7100 #define MX6Q_PAD_SD4_DAT3__GPIO_2_11 \
7101 (_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7102 #define MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \
7103 (_MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7104 #define MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \
7105 (_MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7107 #define MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \
7108 (_MX6Q_PAD_SD4_DAT4__RAWNAND_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
7109 #define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ \
7110 (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7111 #define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_100MHZ \
7112 (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7113 #define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_200MHZ \
7114 (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7115 #define MX6Q_PAD_SD4_DAT4__UART2_TXD \
7116 (_MX6Q_PAD_SD4_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7117 #define MX6Q_PAD_SD4_DAT4__UART2_RXD \
7118 (_MX6Q_PAD_SD4_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7119 #define MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \
7120 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
7121 #define MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \
7122 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
7123 #define MX6Q_PAD_SD4_DAT4__GPIO_2_12 \
7124 (_MX6Q_PAD_SD4_DAT4__GPIO_2_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
7125 #define MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \
7126 (_MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
7127 #define MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \
7128 (_MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
7130 #define MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \
7131 (_MX6Q_PAD_SD4_DAT5__RAWNAND_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
7132 #define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ \
7133 (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7134 #define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_100MHZ \
7135 (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7136 #define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_200MHZ \
7137 (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7138 #define MX6Q_PAD_SD4_DAT5__UART2_CTS \
7139 (_MX6Q_PAD_SD4_DAT5__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7140 #define MX6Q_PAD_SD4_DAT5__UART2_RTS \
7141 (_MX6Q_PAD_SD4_DAT5__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7142 #define MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \
7143 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
7144 #define MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \
7145 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
7146 #define MX6Q_PAD_SD4_DAT5__GPIO_2_13 \
7147 (_MX6Q_PAD_SD4_DAT5__GPIO_2_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
7148 #define MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \
7149 (_MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
7150 #define MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \
7151 (_MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
7153 #define MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \
7154 (_MX6Q_PAD_SD4_DAT6__RAWNAND_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
7155 #define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ \
7156 (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7157 #define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_100MHZ \
7158 (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7159 #define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_200MHZ \
7160 (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7161 #define MX6Q_PAD_SD4_DAT6__UART2_CTS \
7162 (_MX6Q_PAD_SD4_DAT6__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7163 #define MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \
7164 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
7165 #define MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \
7166 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
7167 #define MX6Q_PAD_SD4_DAT6__GPIO_2_14 \
7168 (_MX6Q_PAD_SD4_DAT6__GPIO_2_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
7169 #define MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \
7170 (_MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
7171 #define MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \
7172 (_MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
7174 #define MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \
7175 (_MX6Q_PAD_SD4_DAT7__RAWNAND_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
7176 #define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ \
7177 (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7178 #define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_100MHZ \
7179 (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
7180 #define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_200MHZ \
7181 (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
7182 #define MX6Q_PAD_SD4_DAT7__UART2_TXD \
7183 (_MX6Q_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7184 #define MX6Q_PAD_SD4_DAT7__UART2_RXD \
7185 (_MX6Q_PAD_SD4_DAT7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7186 #define MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \
7187 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
7188 #define MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \
7189 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
7190 #define MX6Q_PAD_SD4_DAT7__GPIO_2_15 \
7191 (_MX6Q_PAD_SD4_DAT7__GPIO_2_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
7192 #define MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \
7193 (_MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
7194 #define MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \
7195 (_MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
7197 #define MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \
7198 (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7199 #define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \
7200 (_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
7201 #define MX6Q_PAD_SD1_DAT1__PWM3_PWMO \
7202 (_MX6Q_PAD_SD1_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7203 #define MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \
7204 (_MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
7205 #define MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \
7206 (_MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
7207 #define MX6Q_PAD_SD1_DAT1__GPIO_1_17 \
7208 (_MX6Q_PAD_SD1_DAT1__GPIO_1_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
7209 #define MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \
7210 (_MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
7211 #define MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \
7212 (_MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
7214 #define MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \
7215 (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7216 #define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \
7217 (_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
7218 #define MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \
7219 (_MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS | MUX_PAD_CTRL(NO_PAD_CTRL))
7220 #define MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \
7221 (_MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7222 #define MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \
7223 (_MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
7224 #define MX6Q_PAD_SD1_DAT0__GPIO_1_16 \
7225 (_MX6Q_PAD_SD1_DAT0__GPIO_1_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
7226 #define MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \
7227 (_MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7228 #define MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \
7229 (_MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
7231 #define MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \
7232 (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7233 #define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \
7234 (_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
7235 #define MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \
7236 (_MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
7237 #define MX6Q_PAD_SD1_DAT3__PWM1_PWMO \
7238 (_MX6Q_PAD_SD1_DAT3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7239 #define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \
7240 (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
7241 #define MX6Q_PAD_SD1_DAT3__GPIO_1_21 \
7242 (_MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
7243 #define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \
7244 (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
7245 #define MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \
7246 (_MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
7248 #define MX6Q_PAD_SD1_CMD__USDHC1_CMD \
7249 (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7250 #define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \
7251 (_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
7252 #define MX6Q_PAD_SD1_CMD__PWM4_PWMO \
7253 (_MX6Q_PAD_SD1_CMD__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7254 #define MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \
7255 (_MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7256 #define MX6Q_PAD_SD1_CMD__GPIO_1_18 \
7257 (_MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
7258 #define MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \
7259 (_MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
7261 #define MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \
7262 (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7263 #define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \
7264 (_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7265 #define MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \
7266 (_MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
7267 #define MX6Q_PAD_SD1_DAT2__PWM2_PWMO \
7268 (_MX6Q_PAD_SD1_DAT2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7269 #define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \
7270 (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
7271 #define MX6Q_PAD_SD1_DAT2__GPIO_1_19 \
7272 (_MX6Q_PAD_SD1_DAT2__GPIO_1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
7273 #define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \
7274 (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
7275 #define MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \
7276 (_MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
7278 #define MX6Q_PAD_SD1_CLK__USDHC1_CLK \
7279 (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7280 #define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \
7281 (_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
7282 #define MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \
7283 (_MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
7284 #define MX6Q_PAD_SD1_CLK__GPT_CLKIN \
7285 (_MX6Q_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL))
7286 #define MX6Q_PAD_SD1_CLK__GPIO_1_20 \
7287 (_MX6Q_PAD_SD1_CLK__GPIO_1_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
7288 #define MX6Q_PAD_SD1_CLK__PHY_DTB_0 \
7289 (_MX6Q_PAD_SD1_CLK__PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
7290 #define MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \
7291 (_MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
7293 #define MX6Q_PAD_SD2_CLK__USDHC2_CLK \
7294 (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7295 #define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \
7296 (_MX6Q_PAD_SD2_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
7297 #define MX6Q_PAD_SD2_CLK__KPP_COL_5 \
7298 (_MX6Q_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
7299 #define MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \
7300 (_MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
7301 #define MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \
7302 (_MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
7303 #define MX6Q_PAD_SD2_CLK__GPIO_1_10 \
7304 (_MX6Q_PAD_SD2_CLK__GPIO_1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7305 #define MX6Q_PAD_SD2_CLK__PHY_DTB_1 \
7306 (_MX6Q_PAD_SD2_CLK__PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7307 #define MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \
7308 (_MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7310 #define MX6Q_PAD_SD2_CMD__USDHC2_CMD \
7311 (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7312 #define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \
7313 (_MX6Q_PAD_SD2_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
7314 #define MX6Q_PAD_SD2_CMD__KPP_ROW_5 \
7315 (_MX6Q_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
7316 #define MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \
7317 (_MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
7318 #define MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \
7319 (_MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7320 #define MX6Q_PAD_SD2_CMD__GPIO_1_11 \
7321 (_MX6Q_PAD_SD2_CMD__GPIO_1_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7323 #define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \
7324 (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7325 #define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \
7326 (_MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
7327 #define MX6Q_PAD_SD2_DAT3__KPP_COL_6 \
7328 (_MX6Q_PAD_SD2_DAT3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
7329 #define MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \
7330 (_MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
7331 #define MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \
7332 (_MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7333 #define MX6Q_PAD_SD2_DAT3__GPIO_1_12 \
7334 (_MX6Q_PAD_SD2_DAT3__GPIO_1_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
7335 #define MX6Q_PAD_SD2_DAT3__SJC_DONE \
7336 (_MX6Q_PAD_SD2_DAT3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL))
7337 #define MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \
7338 (_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 | MUX_PAD_CTRL(NO_PAD_CTRL))