2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 * Auto Generate file, please don't edit it
22 #ifndef __MACH_IOMUX_MX6Q_H__
23 #define __MACH_IOMUX_MX6Q_H__
25 #include <mach/iomux-v3.h>
28 * various IOMUX alternate output functions (1-7)
30 typedef enum iomux_config {
39 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
42 #define NON_MUX_I 0x3FF
43 #define NON_PAD_I 0x7FF
45 #define MX6Q_HIGH_DRV (PAD_CTL_DSE_240ohm)
46 #define MX6Q_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
50 #define MX6Q_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
51 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
52 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
54 #define MX6Q_ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
55 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
56 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
58 #define MX6Q_DISP_PAD_CLT MX6Q_HIGH_DRV
59 #define MX6Q_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
60 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_40ohm | \
61 PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_SPEED_MED)
63 #define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
64 IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
65 #define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
66 IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0)
67 #define _MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \
68 IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0)
69 #define _MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \
70 IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0)
71 #define _MX6Q_PAD_SD2_DAT1__KPP_COL_7 \
72 IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0)
73 #define _MX6Q_PAD_SD2_DAT1__GPIO_1_14 \
74 IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0)
75 #define _MX6Q_PAD_SD2_DAT1__CCM_WAIT \
76 IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0)
77 #define _MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \
78 IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0)
80 #define _MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \
81 IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0)
82 #define _MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \
83 IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0)
84 #define _MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \
85 IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0)
86 #define _MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \
87 IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0)
88 #define _MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \
89 IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0)
90 #define _MX6Q_PAD_SD2_DAT2__GPIO_1_13 \
91 IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0)
92 #define _MX6Q_PAD_SD2_DAT2__CCM_STOP \
93 IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0)
94 #define _MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \
95 IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0)
97 #define _MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \
98 IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0)
99 #define _MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \
100 IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0)
101 #define _MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
102 IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0)
103 #define _MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \
104 IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0)
105 #define _MX6Q_PAD_SD2_DAT0__GPIO_1_15 \
106 IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0)
107 #define _MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \
108 IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0)
109 #define _MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \
110 IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0)
112 #define _MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \
113 IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0)
114 #define _MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \
115 IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0)
116 #define _MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \
117 IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0)
118 #define _MX6Q_PAD_RGMII_TXC__GPIO_6_19 \
119 IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0)
120 #define _MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \
121 IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0)
122 #define _MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \
123 IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0)
125 #define _MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \
126 IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0)
127 #define _MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \
128 IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0)
129 #define _MX6Q_PAD_RGMII_TD0__GPIO_6_20 \
130 IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0)
131 #define _MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \
132 IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0)
134 #define _MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \
135 IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0)
136 #define _MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \
137 IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0)
138 #define _MX6Q_PAD_RGMII_TD1__GPIO_6_21 \
139 IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0)
140 #define _MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \
141 IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0)
142 #define _MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \
143 IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0)
145 #define _MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \
146 IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0)
147 #define _MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \
148 IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0)
149 #define _MX6Q_PAD_RGMII_TD2__GPIO_6_22 \
150 IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0)
151 #define _MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \
152 IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0)
153 #define _MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \
154 IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0)
156 #define _MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \
157 IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0)
158 #define _MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \
159 IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0)
160 #define _MX6Q_PAD_RGMII_TD3__GPIO_6_23 \
161 IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0)
162 #define _MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \
163 IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0)
165 #define _MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \
166 IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0)
167 #define _MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \
168 IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0)
169 #define _MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \
170 IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0)
171 #define _MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \
172 IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0)
174 #define _MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \
175 IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0)
176 #define _MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \
177 IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0)
178 #define _MX6Q_PAD_RGMII_RD0__GPIO_6_25 \
179 IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0)
180 #define _MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \
181 IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0)
183 #define _MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \
184 IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0)
185 #define _MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \
186 IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0)
187 #define _MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \
188 IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0)
189 #define _MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \
190 IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0)
191 #define _MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \
192 IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0)
194 #define _MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \
195 IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0)
196 #define _MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \
197 IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0)
198 #define _MX6Q_PAD_RGMII_RD1__GPIO_6_27 \
199 IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0)
200 #define _MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \
201 IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0)
202 #define _MX6Q_PAD_RGMII_RD1__SJC_FAIL \
203 IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0)
205 #define _MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \
206 IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0)
207 #define _MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \
208 IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0)
209 #define _MX6Q_PAD_RGMII_RD2__GPIO_6_28 \
210 IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0)
211 #define _MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \
212 IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0)
214 #define _MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \
215 IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0)
216 #define _MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \
217 IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0)
218 #define _MX6Q_PAD_RGMII_RD3__GPIO_6_29 \
219 IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0)
220 #define _MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \
221 IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0)
223 #define _MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \
224 IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0)
225 #define _MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \
226 IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0)
227 #define _MX6Q_PAD_RGMII_RXC__GPIO_6_30 \
228 IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0)
229 #define _MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \
230 IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0)
232 #define _MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \
233 IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0)
234 #define _MX6Q_PAD_EIM_A25__ECSPI4_SS1 \
235 IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0)
236 #define _MX6Q_PAD_EIM_A25__ECSPI2_RDY \
237 IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0)
238 #define _MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \
239 IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0)
240 #define _MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \
241 IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0)
242 #define _MX6Q_PAD_EIM_A25__GPIO_5_2 \
243 IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0)
244 #define _MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \
245 IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0)
246 #define _MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \
247 IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0)
249 #define _MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \
250 IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0)
251 #define _MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \
252 IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0)
253 #define _MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \
254 IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0)
255 #define _MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \
256 IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0)
257 #define _MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \
258 IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0)
259 #define _MX6Q_PAD_EIM_EB2__GPIO_2_30 \
260 IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0)
261 #define _MX6Q_PAD_EIM_EB2__I2C2_SCL \
262 IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0)
263 #define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \
264 IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0)
266 #define _MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \
267 IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0)
268 #define _MX6Q_PAD_EIM_D16__ECSPI1_SCLK \
269 IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0)
270 #define _MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \
271 IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0)
272 #define _MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \
273 IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0)
274 #define _MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \
275 IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0)
276 #define _MX6Q_PAD_EIM_D16__GPIO_3_16 \
277 IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0)
278 #define _MX6Q_PAD_EIM_D16__I2C2_SDA \
279 IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0)
281 #define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \
282 IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0)
283 #define _MX6Q_PAD_EIM_D17__ECSPI1_MISO \
284 IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0)
285 #define _MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \
286 IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0)
287 #define _MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \
288 IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0)
289 #define _MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \
290 IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0)
291 #define _MX6Q_PAD_EIM_D17__GPIO_3_17 \
292 IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0)
293 #define _MX6Q_PAD_EIM_D17__I2C3_SCL \
294 IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0)
295 #define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \
296 IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0)
298 #define _MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \
299 IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0)
300 #define _MX6Q_PAD_EIM_D18__ECSPI1_MOSI \
301 IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0)
302 #define _MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \
303 IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0)
304 #define _MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \
305 IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0)
306 #define _MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \
307 IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0)
308 #define _MX6Q_PAD_EIM_D18__GPIO_3_18 \
309 IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0)
310 #define _MX6Q_PAD_EIM_D18__I2C3_SDA \
311 IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0)
312 #define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \
313 IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0)
315 #define _MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \
316 IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0)
317 #define _MX6Q_PAD_EIM_D19__ECSPI1_SS1 \
318 IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0)
319 #define _MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \
320 IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0)
321 #define _MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \
322 IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0)
323 #define _MX6Q_PAD_EIM_D19__UART1_CTS \
324 IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0)
325 #define _MX6Q_PAD_EIM_D19__GPIO_3_19 \
326 IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0)
327 #define _MX6Q_PAD_EIM_D19__EPIT1_EPITO \
328 IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0)
329 #define _MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \
330 IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0)
332 #define _MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \
333 IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0)
334 #define _MX6Q_PAD_EIM_D20__ECSPI4_SS0 \
335 IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0)
336 #define _MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \
337 IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0)
338 #define _MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \
339 IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0)
340 #define _MX6Q_PAD_EIM_D20__UART1_CTS \
341 IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0)
342 #define _MX6Q_PAD_EIM_D20__UART1_RTS \
343 IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0)
344 #define _MX6Q_PAD_EIM_D20__GPIO_3_20 \
345 IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0)
346 #define _MX6Q_PAD_EIM_D20__EPIT2_EPITO \
347 IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0)
349 #define _MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \
350 IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0)
351 #define _MX6Q_PAD_EIM_D21__ECSPI4_SCLK \
352 IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0)
353 #define _MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \
354 IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0)
355 #define _MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \
356 IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0)
357 #define _MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \
358 IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0)
359 #define _MX6Q_PAD_EIM_D21__GPIO_3_21 \
360 IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0)
361 #define _MX6Q_PAD_EIM_D21__I2C1_SCL \
362 IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0)
363 #define _MX6Q_PAD_EIM_D21__SPDIF_IN1 \
364 IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0)
366 #define _MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \
367 IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0)
368 #define _MX6Q_PAD_EIM_D22__ECSPI4_MISO \
369 IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0)
370 #define _MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \
371 IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0)
372 #define _MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \
373 IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0)
374 #define _MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \
375 IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0)
376 #define _MX6Q_PAD_EIM_D22__GPIO_3_22 \
377 IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0)
378 #define _MX6Q_PAD_EIM_D22__SPDIF_OUT1 \
379 IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0)
380 #define _MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \
381 IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0)
383 #define _MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \
384 IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0)
385 #define _MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \
386 IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0)
387 #define _MX6Q_PAD_EIM_D23__UART3_CTS \
388 IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0)
389 #define _MX6Q_PAD_EIM_D23__UART1_DCD \
390 IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0)
391 #define _MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \
392 IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0)
393 #define _MX6Q_PAD_EIM_D23__GPIO_3_23 \
394 IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0)
395 #define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \
396 IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0)
397 #define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \
398 IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0)
400 #define _MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \
401 IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0)
402 #define _MX6Q_PAD_EIM_EB3__ECSPI4_RDY \
403 IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0)
404 #define _MX6Q_PAD_EIM_EB3__UART3_CTS \
405 IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0)
406 #define _MX6Q_PAD_EIM_EB3__UART3_RTS \
407 IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0)
408 #define _MX6Q_PAD_EIM_EB3__UART1_RI \
409 IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0)
410 #define _MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \
411 IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0)
412 #define _MX6Q_PAD_EIM_EB3__GPIO_2_31 \
413 IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0)
414 #define _MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \
415 IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0)
416 #define _MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \
417 IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0)
419 #define _MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \
420 IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0)
421 #define _MX6Q_PAD_EIM_D24__ECSPI4_SS2 \
422 IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0)
423 #define _MX6Q_PAD_EIM_D24__UART3_TXD \
424 IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0)
425 #define _MX6Q_PAD_EIM_D24__UART3_RXD \
426 IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0)
427 #define _MX6Q_PAD_EIM_D24__ECSPI1_SS2 \
428 IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0)
429 #define _MX6Q_PAD_EIM_D24__ECSPI2_SS2 \
430 IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0)
431 #define _MX6Q_PAD_EIM_D24__GPIO_3_24 \
432 IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0)
433 #define _MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \
434 IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0)
435 #define _MX6Q_PAD_EIM_D24__UART1_DTR \
436 IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0)
438 #define _MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \
439 IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0)
440 #define _MX6Q_PAD_EIM_D25__ECSPI4_SS3 \
441 IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0)
442 #define _MX6Q_PAD_EIM_D25__UART3_TXD \
443 IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0)
444 #define _MX6Q_PAD_EIM_D25__UART3_RXD \
445 IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0)
446 #define _MX6Q_PAD_EIM_D25__ECSPI1_SS3 \
447 IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0)
448 #define _MX6Q_PAD_EIM_D25__ECSPI2_SS3 \
449 IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0)
450 #define _MX6Q_PAD_EIM_D25__GPIO_3_25 \
451 IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0)
452 #define _MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \
453 IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0)
454 #define _MX6Q_PAD_EIM_D25__UART1_DSR \
455 IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0)
457 #define _MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \
458 IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0)
459 #define _MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \
460 IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0)
461 #define _MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \
462 IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0)
463 #define _MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \
464 IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0)
465 #define _MX6Q_PAD_EIM_D26__UART2_TXD \
466 IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0)
467 #define _MX6Q_PAD_EIM_D26__UART2_RXD \
468 IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0)
469 #define _MX6Q_PAD_EIM_D26__GPIO_3_26 \
470 IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0)
471 #define _MX6Q_PAD_EIM_D26__IPU1_SISG_2 \
472 IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0)
473 #define _MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \
474 IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0)
476 #define _MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \
477 IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0)
478 #define _MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \
479 IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0)
480 #define _MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \
481 IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0)
482 #define _MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \
483 IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0)
484 #define _MX6Q_PAD_EIM_D27__UART2_TXD \
485 IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0)
486 #define _MX6Q_PAD_EIM_D27__UART2_RXD \
487 IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0)
488 #define _MX6Q_PAD_EIM_D27__GPIO_3_27 \
489 IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0)
490 #define _MX6Q_PAD_EIM_D27__IPU1_SISG_3 \
491 IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0)
492 #define _MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \
493 IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0)
495 #define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \
496 IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0)
497 #define _MX6Q_PAD_EIM_D28__I2C1_SDA \
498 IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0)
499 #define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI \
500 IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0)
501 #define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \
502 IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0)
503 #define _MX6Q_PAD_EIM_D28__UART2_CTS \
504 IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0)
505 #define _MX6Q_PAD_EIM_D28__GPIO_3_28 \
506 IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0)
507 #define _MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \
508 IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0)
509 #define _MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \
510 IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0)
512 #define _MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \
513 IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0)
514 #define _MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \
515 IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0)
516 #define _MX6Q_PAD_EIM_D29__ECSPI4_SS0 \
517 IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0)
518 #define _MX6Q_PAD_EIM_D29__UART2_CTS \
519 IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0)
520 #define _MX6Q_PAD_EIM_D29__UART2_RTS \
521 IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0)
522 #define _MX6Q_PAD_EIM_D29__GPIO_3_29 \
523 IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0)
524 #define _MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \
525 IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0)
526 #define _MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \
527 IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0)
529 #define _MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \
530 IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0)
531 #define _MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
532 IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0)
533 #define _MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \
534 IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0)
535 #define _MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \
536 IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0)
537 #define _MX6Q_PAD_EIM_D30__UART3_CTS \
538 IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0)
539 #define _MX6Q_PAD_EIM_D30__GPIO_3_30 \
540 IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0)
541 #define _MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \
542 IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0)
543 #define _MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \
544 IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0)
546 #define _MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \
547 IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0)
548 #define _MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
549 IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0)
550 #define _MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \
551 IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0)
552 #define _MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \
553 IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0)
554 #define _MX6Q_PAD_EIM_D31__UART3_CTS \
555 IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0)
556 #define _MX6Q_PAD_EIM_D31__UART3_RTS \
557 IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0)
558 #define _MX6Q_PAD_EIM_D31__GPIO_3_31 \
559 IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0)
560 #define _MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \
561 IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0)
562 #define _MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \
563 IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0)
565 #define _MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \
566 IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0)
567 #define _MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \
568 IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0)
569 #define _MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \
570 IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0)
571 #define _MX6Q_PAD_EIM_A24__IPU2_SISG_2 \
572 IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0)
573 #define _MX6Q_PAD_EIM_A24__IPU1_SISG_2 \
574 IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0)
575 #define _MX6Q_PAD_EIM_A24__GPIO_5_4 \
576 IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0)
577 #define _MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \
578 IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0)
579 #define _MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \
580 IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0)
582 #define _MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \
583 IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0)
584 #define _MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \
585 IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0)
586 #define _MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \
587 IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0)
588 #define _MX6Q_PAD_EIM_A23__IPU2_SISG_3 \
589 IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0)
590 #define _MX6Q_PAD_EIM_A23__IPU1_SISG_3 \
591 IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0)
592 #define _MX6Q_PAD_EIM_A23__GPIO_6_6 \
593 IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0)
594 #define _MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \
595 IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0)
596 #define _MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \
597 IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0)
599 #define _MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \
600 IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0)
601 #define _MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \
602 IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0)
603 #define _MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \
604 IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0)
605 #define _MX6Q_PAD_EIM_A22__GPIO_2_16 \
606 IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0)
607 #define _MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \
608 IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0)
609 #define _MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \
610 IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0)
612 #define _MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \
613 IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0)
614 #define _MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \
615 IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0)
616 #define _MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \
617 IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0)
618 #define _MX6Q_PAD_EIM_A21__RESERVED_RESERVED \
619 IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0)
620 #define _MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \
621 IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0)
622 #define _MX6Q_PAD_EIM_A21__GPIO_2_17 \
623 IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0)
624 #define _MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \
625 IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0)
626 #define _MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \
627 IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0)
629 #define _MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \
630 IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0)
631 #define _MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \
632 IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0)
633 #define _MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \
634 IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0)
635 #define _MX6Q_PAD_EIM_A20__RESERVED_RESERVED \
636 IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0)
637 #define _MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \
638 IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0)
639 #define _MX6Q_PAD_EIM_A20__GPIO_2_18 \
640 IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0)
641 #define _MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \
642 IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0)
643 #define _MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \
644 IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0)
646 #define _MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \
647 IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0)
648 #define _MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \
649 IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0)
650 #define _MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \
651 IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0)
652 #define _MX6Q_PAD_EIM_A19__RESERVED_RESERVED \
653 IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0)
654 #define _MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \
655 IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0)
656 #define _MX6Q_PAD_EIM_A19__GPIO_2_19 \
657 IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0)
658 #define _MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \
659 IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0)
660 #define _MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \
661 IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0)
663 #define _MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \
664 IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0)
665 #define _MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \
666 IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0)
667 #define _MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \
668 IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0)
669 #define _MX6Q_PAD_EIM_A18__RESERVED_RESERVED \
670 IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0)
671 #define _MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \
672 IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0)
673 #define _MX6Q_PAD_EIM_A18__GPIO_2_20 \
674 IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0)
675 #define _MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \
676 IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0)
677 #define _MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \
678 IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0)
680 #define _MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \
681 IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0)
682 #define _MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \
683 IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0)
684 #define _MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \
685 IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0)
686 #define _MX6Q_PAD_EIM_A17__RESERVED_RESERVED \
687 IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0)
688 #define _MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \
689 IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0)
690 #define _MX6Q_PAD_EIM_A17__GPIO_2_21 \
691 IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0)
692 #define _MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \
693 IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0)
694 #define _MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \
695 IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0)
697 #define _MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \
698 IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0)
699 #define _MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \
700 IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0)
701 #define _MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \
702 IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0)
703 #define _MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \
704 IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0)
705 #define _MX6Q_PAD_EIM_A16__GPIO_2_22 \
706 IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0)
707 #define _MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \
708 IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0)
709 #define _MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \
710 IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0)
712 #define _MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \
713 IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0)
714 #define _MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \
715 IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0)
716 #define _MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \
717 IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0)
718 #define _MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \
719 IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0)
720 #define _MX6Q_PAD_EIM_CS0__GPIO_2_23 \
721 IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0)
722 #define _MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \
723 IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0)
725 #define _MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \
726 IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0)
727 #define _MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \
728 IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0)
729 #define _MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \
730 IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0)
731 #define _MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \
732 IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0)
733 #define _MX6Q_PAD_EIM_CS1__GPIO_2_24 \
734 IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0)
735 #define _MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \
736 IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0)
738 #define _MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \
739 IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0)
740 #define _MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \
741 IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0)
742 #define _MX6Q_PAD_EIM_OE__ECSPI2_MISO \
743 IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0)
744 #define _MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \
745 IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0)
746 #define _MX6Q_PAD_EIM_OE__GPIO_2_25 \
747 IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0)
748 #define _MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \
749 IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0)
751 #define _MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \
752 IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0)
753 #define _MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \
754 IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0)
755 #define _MX6Q_PAD_EIM_RW__ECSPI2_SS0 \
756 IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0)
757 #define _MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \
758 IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0)
759 #define _MX6Q_PAD_EIM_RW__GPIO_2_26 \
760 IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0)
761 #define _MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \
762 IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0)
763 #define _MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \
764 IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0)
766 #define _MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \
767 IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0)
768 #define _MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \
769 IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0)
770 #define _MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \
771 IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0)
772 #define _MX6Q_PAD_EIM_LBA__GPIO_2_27 \
773 IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0)
774 #define _MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \
775 IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0)
776 #define _MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \
777 IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0)
779 #define _MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \
780 IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0)
781 #define _MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \
782 IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0)
783 #define _MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \
784 IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0)
785 #define _MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \
786 IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0)
787 #define _MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \
788 IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0)
789 #define _MX6Q_PAD_EIM_EB0__GPIO_2_28 \
790 IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0)
791 #define _MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \
792 IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0)
793 #define _MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \
794 IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0)
796 #define _MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \
797 IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0)
798 #define _MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \
799 IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0)
800 #define _MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \
801 IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0)
802 #define _MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \
803 IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0)
804 #define _MX6Q_PAD_EIM_EB1__GPIO_2_29 \
805 IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0)
806 #define _MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \
807 IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0)
808 #define _MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \
809 IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0)
811 #define _MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \
812 IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0)
813 #define _MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \
814 IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0)
815 #define _MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \
816 IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0)
817 #define _MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \
818 IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0)
819 #define _MX6Q_PAD_EIM_DA0__GPIO_3_0 \
820 IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0)
821 #define _MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \
822 IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0)
823 #define _MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \
824 IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0)
826 #define _MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \
827 IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0)
828 #define _MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \
829 IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0)
830 #define _MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \
831 IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0)
832 #define _MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \
833 IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0)
834 #define _MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \
835 IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0)
836 #define _MX6Q_PAD_EIM_DA1__GPIO_3_1 \
837 IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0)
838 #define _MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \
839 IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0)
840 #define _MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \
841 IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0)
843 #define _MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \
844 IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0)
845 #define _MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \
846 IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0)
847 #define _MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \
848 IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0)
849 #define _MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \
850 IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0)
851 #define _MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \
852 IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0)
853 #define _MX6Q_PAD_EIM_DA2__GPIO_3_2 \
854 IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0)
855 #define _MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \
856 IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0)
857 #define _MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \
858 IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0)
860 #define _MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \
861 IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0)
862 #define _MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \
863 IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0)
864 #define _MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \
865 IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0)
866 #define _MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \
867 IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0)
868 #define _MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \
869 IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0)
870 #define _MX6Q_PAD_EIM_DA3__GPIO_3_3 \
871 IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0)
872 #define _MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \
873 IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0)
874 #define _MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \
875 IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0)
877 #define _MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \
878 IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0)
879 #define _MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \
880 IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0)
881 #define _MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \
882 IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0)
883 #define _MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \
884 IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0)
885 #define _MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \
886 IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0)
887 #define _MX6Q_PAD_EIM_DA4__GPIO_3_4 \
888 IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0)
889 #define _MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \
890 IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0)
891 #define _MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \
892 IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0)
894 #define _MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \
895 IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0)
896 #define _MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \
897 IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0)
898 #define _MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \
899 IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0)
900 #define _MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \
901 IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0)
902 #define _MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \
903 IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0)
904 #define _MX6Q_PAD_EIM_DA5__GPIO_3_5 \
905 IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0)
906 #define _MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \
907 IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0)
908 #define _MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \
909 IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0)
911 #define _MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \
912 IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0)
913 #define _MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \
914 IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0)
915 #define _MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \
916 IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0)
917 #define _MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \
918 IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0)
919 #define _MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \
920 IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0)
921 #define _MX6Q_PAD_EIM_DA6__GPIO_3_6 \
922 IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0)
923 #define _MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \
924 IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0)
925 #define _MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \
926 IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0)
928 #define _MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \
929 IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0)
930 #define _MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \
931 IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0)
932 #define _MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \
933 IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0)
934 #define _MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \
935 IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0)
936 #define _MX6Q_PAD_EIM_DA7__GPIO_3_7 \
937 IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0)
938 #define _MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \
939 IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0)
940 #define _MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \
941 IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0)
943 #define _MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \
944 IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0)
945 #define _MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \
946 IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0)
947 #define _MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \
948 IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0)
949 #define _MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \
950 IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0)
951 #define _MX6Q_PAD_EIM_DA8__GPIO_3_8 \
952 IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0)
953 #define _MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \
954 IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0)
955 #define _MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \
956 IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0)
958 #define _MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \
959 IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0)
960 #define _MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \
961 IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0)
962 #define _MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \
963 IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0)
964 #define _MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \
965 IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0)
966 #define _MX6Q_PAD_EIM_DA9__GPIO_3_9 \
967 IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0)
968 #define _MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \
969 IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0)
970 #define _MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \
971 IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0)
973 #define _MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \
974 IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0)
975 #define _MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \
976 IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0)
977 #define _MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \
978 IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0)
979 #define _MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \
980 IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0)
981 #define _MX6Q_PAD_EIM_DA10__GPIO_3_10 \
982 IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0)
983 #define _MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \
984 IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0)
985 #define _MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \
986 IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0)
988 #define _MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \
989 IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0)
990 #define _MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \
991 IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0)
992 #define _MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \
993 IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0)
994 #define _MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \
995 IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0)
996 #define _MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \
997 IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0)
998 #define _MX6Q_PAD_EIM_DA11__GPIO_3_11 \
999 IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0)
1000 #define _MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \
1001 IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0)
1002 #define _MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \
1003 IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0)
1005 #define _MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \
1006 IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0)
1007 #define _MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \
1008 IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0)
1009 #define _MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \
1010 IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0)
1011 #define _MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \
1012 IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0)
1013 #define _MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \
1014 IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0)
1015 #define _MX6Q_PAD_EIM_DA12__GPIO_3_12 \
1016 IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0)
1017 #define _MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \
1018 IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0)
1019 #define _MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \
1020 IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0)
1022 #define _MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \
1023 IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0)
1024 #define _MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \
1025 IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0)
1026 #define _MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \
1027 IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0)
1028 #define _MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \
1029 IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0)
1030 #define _MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \
1031 IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0)
1032 #define _MX6Q_PAD_EIM_DA13__GPIO_3_13 \
1033 IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0)
1034 #define _MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \
1035 IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0)
1036 #define _MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \
1037 IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0)
1039 #define _MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \
1040 IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0)
1041 #define _MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \
1042 IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0)
1043 #define _MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \
1044 IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0)
1045 #define _MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \
1046 IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0)
1047 #define _MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \
1048 IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0)
1049 #define _MX6Q_PAD_EIM_DA14__GPIO_3_14 \
1050 IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0)
1051 #define _MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \
1052 IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0)
1053 #define _MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \
1054 IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0)
1056 #define _MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \
1057 IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0)
1058 #define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \
1059 IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0)
1060 #define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \
1061 IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0)
1062 #define _MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \
1063 IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0)
1064 #define _MX6Q_PAD_EIM_DA15__GPIO_3_15 \
1065 IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0)
1066 #define _MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \
1067 IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0)
1068 #define _MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \
1069 IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0)
1071 #define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \
1072 IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0)
1073 #define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \
1074 IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0)
1075 #define _MX6Q_PAD_EIM_WAIT__GPIO_5_0 \
1076 IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0)
1077 #define _MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \
1078 IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0)
1079 #define _MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \
1080 IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0)
1082 #define _MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \
1083 IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0)
1084 #define _MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \
1085 IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0)
1086 #define _MX6Q_PAD_EIM_BCLK__GPIO_6_31 \
1087 IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0)
1088 #define _MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \
1089 IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0)
1091 #define _MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \
1092 IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0)
1093 #define _MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \
1094 IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0)
1095 #define _MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \
1096 IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0)
1097 #define _MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \
1098 IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0)
1099 #define _MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \
1100 IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0)
1101 #define _MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \
1102 IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0)
1104 #define _MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \
1105 IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0)
1106 #define _MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \
1107 IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0)
1108 #define _MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \
1109 IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0)
1110 #define _MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \
1111 IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0)
1112 #define _MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \
1113 IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0)
1114 #define _MX6Q_PAD_DI0_PIN15__GPIO_4_17 \
1115 IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0)
1116 #define _MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \
1117 IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0)
1119 #define _MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \
1120 IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0)
1121 #define _MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \
1122 IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0)
1123 #define _MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \
1124 IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0)
1125 #define _MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \
1126 IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0)
1127 #define _MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \
1128 IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0)
1129 #define _MX6Q_PAD_DI0_PIN2__GPIO_4_18 \
1130 IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0)
1131 #define _MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \
1132 IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0)
1133 #define _MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \
1134 IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0)
1136 #define _MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \
1137 IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0)
1138 #define _MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \
1139 IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0)
1140 #define _MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \
1141 IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0)
1142 #define _MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \
1143 IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0)
1144 #define _MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \
1145 IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0)
1146 #define _MX6Q_PAD_DI0_PIN3__GPIO_4_19 \
1147 IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0)
1148 #define _MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \
1149 IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0)
1150 #define _MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \
1151 IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0)
1153 #define _MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \
1154 IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0)
1155 #define _MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \
1156 IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0)
1157 #define _MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \
1158 IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0)
1159 #define _MX6Q_PAD_DI0_PIN4__USDHC1_WP \
1160 IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0)
1161 #define _MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \
1162 IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0)
1163 #define _MX6Q_PAD_DI0_PIN4__GPIO_4_20 \
1164 IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0)
1165 #define _MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \
1166 IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0)
1167 #define _MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \
1168 IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0)
1170 #define _MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \
1171 IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0)
1172 #define _MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \
1173 IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0)
1174 #define _MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \
1175 IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0)
1176 #define _MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \
1177 IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0)
1178 #define _MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \
1179 IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0)
1180 #define _MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \
1181 IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0)
1182 #define _MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \
1183 IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0)
1185 #define _MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \
1186 IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0)
1187 #define _MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \
1188 IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0)
1189 #define _MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \
1190 IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0)
1191 #define _MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \
1192 IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0)
1193 #define _MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
1194 IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0)
1195 #define _MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \
1196 IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0)
1197 #define _MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \
1198 IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0)
1199 #define _MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \
1200 IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0)
1202 #define _MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \
1203 IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0)
1204 #define _MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \
1205 IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0)
1206 #define _MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \
1207 IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0)
1208 #define _MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \
1209 IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0)
1210 #define _MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \
1211 IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0)
1212 #define _MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \
1213 IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0)
1214 #define _MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \
1215 IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0)
1216 #define _MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \
1217 IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0)
1219 #define _MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \
1220 IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0)
1221 #define _MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \
1222 IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0)
1223 #define _MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \
1224 IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0)
1225 #define _MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \
1226 IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0)
1227 #define _MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \
1228 IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0)
1229 #define _MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \
1230 IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0)
1231 #define _MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \
1232 IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0)
1233 #define _MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \
1234 IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0)
1236 #define _MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \
1237 IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0)
1238 #define _MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \
1239 IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0)
1240 #define _MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \
1241 IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0)
1242 #define _MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \
1243 IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0)
1244 #define _MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \
1245 IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0)
1246 #define _MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \
1247 IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0)
1248 #define _MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \
1249 IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0)
1250 #define _MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \
1251 IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0)
1253 #define _MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \
1254 IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0)
1255 #define _MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \
1256 IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0)
1257 #define _MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \
1258 IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0)
1259 #define _MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \
1260 IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0)
1261 #define _MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \
1262 IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0)
1263 #define _MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \
1264 IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0)
1265 #define _MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \
1266 IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0)
1267 #define _MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \
1268 IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0)
1270 #define _MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \
1271 IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0)
1272 #define _MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \
1273 IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0)
1274 #define _MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \
1275 IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0)
1276 #define _MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \
1277 IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0)
1278 #define _MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \
1279 IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0)
1280 #define _MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \
1281 IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0)
1282 #define _MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \
1283 IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0)
1284 #define _MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \
1285 IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0)
1287 #define _MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \
1288 IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0)
1289 #define _MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \
1290 IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0)
1291 #define _MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \
1292 IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0)
1293 #define _MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \
1294 IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0)
1295 #define _MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \
1296 IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0)
1297 #define _MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \
1298 IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0)
1299 #define _MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \
1300 IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0)
1301 #define _MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \
1302 IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0)
1304 #define _MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \
1305 IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0)
1306 #define _MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \
1307 IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0)
1308 #define _MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \
1309 IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0)
1310 #define _MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \
1311 IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0)
1312 #define _MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \
1313 IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0)
1314 #define _MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \
1315 IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0)
1316 #define _MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \
1317 IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0)
1318 #define _MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \
1319 IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0)
1321 #define _MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \
1322 IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0)
1323 #define _MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \
1324 IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0)
1325 #define _MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \
1326 IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0)
1327 #define _MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \
1328 IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0)
1329 #define _MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \
1330 IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0)
1331 #define _MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \
1332 IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0)
1333 #define _MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \
1334 IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0)
1335 #define _MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \
1336 IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0)
1338 #define _MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \
1339 IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0)
1340 #define _MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \
1341 IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0)
1342 #define _MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \
1343 IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0)
1344 #define _MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
1345 IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0)
1346 #define _MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \
1347 IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0)
1348 #define _MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \
1349 IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0)
1350 #define _MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \
1351 IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0)
1353 #define _MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \
1354 IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0)
1355 #define _MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \
1356 IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0)
1357 #define _MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \
1358 IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0)
1359 #define _MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
1360 IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0)
1361 #define _MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \
1362 IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0)
1363 #define _MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \
1364 IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0)
1365 #define _MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \
1366 IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0)
1368 #define _MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \
1369 IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0)
1370 #define _MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \
1371 IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0)
1372 #define _MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED \
1373 IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0)
1374 #define _MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
1375 IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0)
1376 #define _MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \
1377 IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0)
1378 #define _MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \
1379 IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0)
1380 #define _MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \
1381 IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0)
1383 #define _MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \
1384 IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0)
1385 #define _MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \
1386 IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0)
1387 #define _MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \
1388 IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0)
1389 #define _MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
1390 IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0)
1391 #define _MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \
1392 IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0)
1393 #define _MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \
1394 IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0)
1395 #define _MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \
1396 IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0)
1398 #define _MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \
1399 IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0)
1400 #define _MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \
1401 IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0)
1402 #define _MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \
1403 IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0)
1404 #define _MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
1405 IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0)
1406 #define _MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \
1407 IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0)
1408 #define _MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \
1409 IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0)
1411 #define _MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \
1412 IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0)
1413 #define _MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \
1414 IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0)
1415 #define _MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \
1416 IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0)
1417 #define _MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \
1418 IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0)
1419 #define _MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
1420 IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0)
1421 #define _MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \
1422 IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0)
1423 #define _MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \
1424 IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0)
1425 #define _MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \
1426 IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0)
1428 #define _MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \
1429 IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0)
1430 #define _MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \
1431 IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0)
1432 #define _MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \
1433 IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0)
1434 #define _MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \
1435 IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0)
1436 #define _MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \
1437 IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0)
1438 #define _MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \
1439 IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0)
1440 #define _MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \
1441 IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0)
1442 #define _MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \
1443 IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0)
1445 #define _MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \
1446 IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0)
1447 #define _MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \
1448 IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0)
1449 #define _MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \
1450 IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0)
1451 #define _MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \
1452 IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0)
1453 #define _MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \
1454 IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0)
1455 #define _MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \
1456 IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0)
1457 #define _MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \
1458 IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0)
1459 #define _MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \
1460 IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0)
1462 #define _MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \
1463 IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0)
1464 #define _MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \
1465 IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0)
1466 #define _MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \
1467 IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0)
1468 #define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \
1469 IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0)
1470 #define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \
1471 IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0)
1472 #define _MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \
1473 IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0)
1474 #define _MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \
1475 IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0)
1476 #define _MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \
1477 IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0)
1479 #define _MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \
1480 IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0)
1481 #define _MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \
1482 IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0)
1483 #define _MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \
1484 IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0)
1485 #define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \
1486 IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0)
1487 #define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \
1488 IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0)
1489 #define _MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \
1490 IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0)
1491 #define _MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \
1492 IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0)
1493 #define _MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \
1494 IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0)
1496 #define _MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \
1497 IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0)
1498 #define _MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \
1499 IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0)
1500 #define _MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \
1501 IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0)
1502 #define _MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \
1503 IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0)
1504 #define _MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
1505 IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0)
1506 #define _MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \
1507 IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0)
1508 #define _MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \
1509 IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0)
1510 #define _MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \
1511 IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0)
1513 #define _MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \
1514 IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0)
1515 #define _MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \
1516 IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0)
1517 #define _MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \
1518 IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0)
1519 #define _MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \
1520 IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0)
1521 #define _MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \
1522 IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0)
1523 #define _MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \
1524 IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0)
1525 #define _MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \
1526 IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0)
1527 #define _MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \
1528 IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0)
1530 #define _MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \
1531 IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0)
1532 #define _MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \
1533 IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0)
1534 #define _MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \
1535 IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0)
1536 #define _MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \
1537 IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0)
1538 #define _MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \
1539 IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0)
1540 #define _MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \
1541 IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0)
1542 #define _MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \
1543 IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0)
1544 #define _MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \
1545 IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0)
1547 #define _MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \
1548 IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0)
1549 #define _MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \
1550 IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0)
1551 #define _MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \
1552 IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0)
1553 #define _MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \
1554 IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0)
1555 #define _MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \
1556 IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0)
1557 #define _MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \
1558 IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0)
1559 #define _MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \
1560 IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0)
1561 #define _MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \
1562 IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0)
1564 #define _MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED \
1565 IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0)
1566 #define _MX6Q_PAD_ENET_MDIO__ENET_MDIO \
1567 IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0)
1568 #define _MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \
1569 IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0)
1570 #define _MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \
1571 IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0)
1572 #define _MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \
1573 IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0)
1574 #define _MX6Q_PAD_ENET_MDIO__GPIO_1_22 \
1575 IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0)
1576 #define _MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \
1577 IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0)
1579 #define _MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED \
1580 IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0)
1581 #define _MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \
1582 IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0)
1583 #define _MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \
1584 IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0)
1585 #define _MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \
1586 IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0)
1587 #define _MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \
1588 IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0)
1589 #define _MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \
1590 IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0)
1591 #define _MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \
1592 IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0)
1594 #define _MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \
1595 IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0)
1596 #define _MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \
1597 IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0)
1598 #define _MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \
1599 IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0)
1600 #define _MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \
1601 IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0)
1602 #define _MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \
1603 IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0)
1604 #define _MX6Q_PAD_ENET_RX_ER__PHY_TDI \
1605 IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0)
1606 #define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \
1607 IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0)
1609 #define _MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED \
1610 IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0)
1611 #define _MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \
1612 IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0)
1613 #define _MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \
1614 IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0)
1615 #define _MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \
1616 IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0)
1617 #define _MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \
1618 IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0)
1619 #define _MX6Q_PAD_ENET_CRS_DV__PHY_TDO \
1620 IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0)
1621 #define _MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \
1622 IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0)
1624 #define _MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \
1625 IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0)
1626 #define _MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \
1627 IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0)
1628 #define _MX6Q_PAD_ENET_RXD1__ESAI1_FST \
1629 IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0)
1630 #define _MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \
1631 IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0)
1632 #define _MX6Q_PAD_ENET_RXD1__GPIO_1_26 \
1633 IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0)
1634 #define _MX6Q_PAD_ENET_RXD1__PHY_TCK \
1635 IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0)
1636 #define _MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \
1637 IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0)
1639 #define _MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \
1640 IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0)
1641 #define _MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \
1642 IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0)
1643 #define _MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \
1644 IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0)
1645 #define _MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \
1646 IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0)
1647 #define _MX6Q_PAD_ENET_RXD0__GPIO_1_27 \
1648 IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0)
1649 #define _MX6Q_PAD_ENET_RXD0__PHY_TMS \
1650 IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0)
1651 #define _MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \
1652 IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0)
1654 #define _MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED \
1655 IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0)
1656 #define _MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \
1657 IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0)
1658 #define _MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \
1659 IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0)
1660 #define _MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \
1661 IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0)
1662 #define _MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \
1663 IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0)
1664 #define _MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \
1665 IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0)
1667 #define _MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \
1668 IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0)
1669 #define _MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \
1670 IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0)
1671 #define _MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \
1672 IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0)
1673 #define _MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \
1674 IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0)
1675 #define _MX6Q_PAD_ENET_TXD1__GPIO_1_29 \
1676 IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0)
1677 #define _MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \
1678 IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0)
1679 #define _MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \
1680 IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0)
1682 #define _MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED \
1683 IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0)
1684 #define _MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \
1685 IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0)
1686 #define _MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \
1687 IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0)
1688 #define _MX6Q_PAD_ENET_TXD0__GPIO_1_30 \
1689 IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0)
1690 #define _MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \
1691 IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0)
1692 #define _MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \
1693 IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0)
1695 #define _MX6Q_PAD_ENET_MDC__MLB_MLBDAT \
1696 IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0)
1697 #define _MX6Q_PAD_ENET_MDC__ENET_MDC \
1698 IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0)
1699 #define _MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \
1700 IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0)
1701 #define _MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \
1702 IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0)
1703 #define _MX6Q_PAD_ENET_MDC__GPIO_1_31 \
1704 IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0)
1705 #define _MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \
1706 IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0)
1707 #define _MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \
1708 IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0)
1710 #define _MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \
1711 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1713 #define _MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \
1714 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1716 #define _MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \
1717 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1719 #define _MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \
1720 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1722 #define _MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \
1723 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1725 #define _MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \
1726 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1728 #define _MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \
1729 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1731 #define _MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \
1732 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1734 #define _MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \
1735 IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0)
1737 #define _MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \
1738 IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0)
1740 #define _MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \
1741 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1743 #define _MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \
1744 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1746 #define _MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \
1747 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1749 #define _MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \
1750 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1752 #define _MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \
1753 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1755 #define _MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \
1756 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1758 #define _MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \
1759 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1761 #define _MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \
1762 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1764 #define _MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \
1765 IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0)
1767 #define _MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \
1768 IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0)
1770 #define _MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \
1771 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1773 #define _MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \
1774 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1776 #define _MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \
1777 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1779 #define _MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \
1780 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1782 #define _MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \
1783 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1785 #define _MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \
1786 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1788 #define _MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \
1789 IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0)
1791 #define _MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \
1792 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1794 #define _MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \
1795 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1797 #define _MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \
1798 IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0)
1800 #define _MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \
1801 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1803 #define _MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \
1804 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1806 #define _MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \
1807 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1809 #define _MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \
1810 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1812 #define _MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \
1813 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1815 #define _MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \
1816 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1818 #define _MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \
1819 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1821 #define _MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \
1822 IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0)
1824 #define _MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \
1825 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1827 #define _MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \
1828 IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0)
1830 #define _MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \
1831 IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0)
1833 #define _MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \
1834 IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0)
1836 #define _MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \
1837 IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0)
1839 #define _MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \
1840 IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0)
1842 #define _MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \
1843 IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0)
1845 #define _MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \
1846 IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0)
1848 #define _MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \
1849 IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0)
1851 #define _MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \
1852 IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0)
1854 #define _MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \
1855 IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0)
1857 #define _MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \
1858 IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0)
1860 #define _MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \
1861 IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0)
1863 #define _MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \
1864 IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0)
1866 #define _MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \
1867 IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0)
1869 #define _MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \
1870 IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0)
1872 #define _MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \
1873 IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0)
1875 #define _MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \
1876 IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0)
1878 #define _MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \
1879 IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0)
1881 #define _MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \
1882 IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0)
1884 #define _MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \
1885 IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0)
1887 #define _MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \
1888 IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0)
1890 #define _MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \
1891 IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0)
1893 #define _MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \
1894 IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0)
1896 #define _MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \
1897 IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0)
1899 #define _MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \
1900 IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0)
1902 #define _MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \
1903 IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0)
1905 #define _MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \
1906 IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0)
1908 #define _MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \
1909 IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0)
1911 #define _MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \
1912 IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0)
1914 #define _MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \
1915 IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0)
1917 #define _MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \
1918 IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0)
1920 #define _MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \
1921 IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0)
1923 #define _MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \
1924 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1926 #define _MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \
1927 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1929 #define _MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \
1930 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1932 #define _MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \
1933 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1935 #define _MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \
1936 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1938 #define _MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \
1939 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1941 #define _MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \
1942 IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0)
1944 #define _MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \
1945 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1947 #define _MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \
1948 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1950 #define _MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \
1951 IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0)
1953 #define _MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \
1954 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1956 #define _MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \
1957 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1959 #define _MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \
1960 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1962 #define _MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \
1963 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1965 #define _MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \
1966 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1968 #define _MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \
1969 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1971 #define _MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \
1972 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1974 #define _MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \
1975 IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0)
1977 #define _MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \
1978 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1980 #define _MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \
1981 IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0)
1983 #define _MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \
1984 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1986 #define _MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \
1987 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1989 #define _MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \
1990 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1992 #define _MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \
1993 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1995 #define _MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \
1996 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1998 #define _MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \
1999 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2001 #define _MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \
2002 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2004 #define _MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \
2005 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2007 #define _MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \
2008 IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0)
2010 #define _MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \
2011 IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0)
2013 #define _MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \
2014 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2016 #define _MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \
2017 IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0)
2019 #define _MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \
2020 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2022 #define _MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \
2023 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2025 #define _MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \
2026 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2028 #define _MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \
2029 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2031 #define _MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \
2032 IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0)
2034 #define _MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \
2035 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2037 #define _MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \
2038 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2040 #define _MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \
2041 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2043 #define _MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \
2044 IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0)
2045 #define _MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \
2046 IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0)
2047 #define _MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \
2048 IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0)
2049 #define _MX6Q_PAD_KEY_COL0__KPP_COL_0 \
2050 IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0)
2051 #define _MX6Q_PAD_KEY_COL0__UART4_TXD \
2052 IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0)
2053 #define _MX6Q_PAD_KEY_COL0__UART4_RXD \
2054 IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0)
2055 #define _MX6Q_PAD_KEY_COL0__GPIO_4_6 \
2056 IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0)
2057 #define _MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \
2058 IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0)
2059 #define _MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \
2060 IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0)
2062 #define _MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \
2063 IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0)
2064 #define _MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \
2065 IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0)
2066 #define _MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \
2067 IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0)
2068 #define _MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \
2069 IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0)
2070 #define _MX6Q_PAD_KEY_ROW0__UART4_TXD \
2071 IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0)
2072 #define _MX6Q_PAD_KEY_ROW0__UART4_RXD \
2073 IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0)
2074 #define _MX6Q_PAD_KEY_ROW0__GPIO_4_7 \
2075 IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0)
2076 #define _MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \
2077 IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0)
2078 #define _MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \
2079 IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0)
2081 #define _MX6Q_PAD_KEY_COL1__ECSPI1_MISO \
2082 IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0)
2083 #define _MX6Q_PAD_KEY_COL1__ENET_MDIO \
2084 IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0)
2085 #define _MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \
2086 IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0)
2087 #define _MX6Q_PAD_KEY_COL1__KPP_COL_1 \
2088 IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0)
2089 #define _MX6Q_PAD_KEY_COL1__UART5_TXD \
2090 IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0)
2091 #define _MX6Q_PAD_KEY_COL1__UART5_RXD \
2092 IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0)
2093 #define _MX6Q_PAD_KEY_COL1__GPIO_4_8 \
2094 IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0)
2095 #define _MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \
2096 IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0)
2097 #define _MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \
2098 IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0)
2100 #define _MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \
2101 IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0)
2102 #define _MX6Q_PAD_KEY_ROW1__ENET_COL \
2103 IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0)
2104 #define _MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \
2105 IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0)
2106 #define _MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \
2107 IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0)
2108 #define _MX6Q_PAD_KEY_ROW1__UART5_TXD \
2109 IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0)
2110 #define _MX6Q_PAD_KEY_ROW1__UART5_RXD \
2111 IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0)
2112 #define _MX6Q_PAD_KEY_ROW1__GPIO_4_9 \
2113 IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0)
2114 #define _MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \
2115 IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0)
2116 #define _MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \
2117 IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0)
2119 #define _MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \
2120 IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0)
2121 #define _MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \
2122 IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0)
2123 #define _MX6Q_PAD_KEY_COL2__CAN1_TXCAN \
2124 IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0)
2125 #define _MX6Q_PAD_KEY_COL2__KPP_COL_2 \
2126 IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0)
2127 #define _MX6Q_PAD_KEY_COL2__ENET_MDC \
2128 IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0)
2129 #define _MX6Q_PAD_KEY_COL2__GPIO_4_10 \
2130 IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0)
2131 #define _MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \
2132 IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0)
2133 #define _MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \
2134 IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0)
2136 #define _MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \
2137 IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0)
2138 #define _MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \
2139 IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0)
2140 #define _MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \
2141 IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0)
2142 #define _MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \
2143 IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0)
2144 #define _MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \
2145 IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0)
2146 #define _MX6Q_PAD_KEY_ROW2__GPIO_4_11 \
2147 IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0)
2148 #define _MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \
2149 IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0)
2150 #define _MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \
2151 IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0)
2153 #define _MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \
2154 IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0)
2155 #define _MX6Q_PAD_KEY_COL3__ENET_CRS \
2156 IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0)
2157 #define _MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \
2158 IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0)
2159 #define _MX6Q_PAD_KEY_COL3__KPP_COL_3 \
2160 IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0)
2161 #define _MX6Q_PAD_KEY_COL3__I2C2_SCL \
2162 IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0)
2163 #define _MX6Q_PAD_KEY_COL3__GPIO_4_12 \
2164 IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0)
2165 #define _MX6Q_PAD_KEY_COL3__SPDIF_IN1 \
2166 IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0)
2167 #define _MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \
2168 IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0)
2170 #define _MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \
2171 IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0)
2172 #define _MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \
2173 IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0)
2174 #define _MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \
2175 IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0)
2176 #define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \
2177 IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0)
2178 #define _MX6Q_PAD_KEY_ROW3__I2C2_SDA \
2179 IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0)
2180 #define _MX6Q_PAD_KEY_ROW3__GPIO_4_13 \
2181 IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0)
2182 #define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \
2183 IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0)
2184 #define _MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \
2185 IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0)
2187 #define _MX6Q_PAD_KEY_COL4__CAN2_TXCAN \
2188 IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0)
2189 #define _MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \
2190 IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0)
2191 #define _MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \
2192 IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0)
2193 #define _MX6Q_PAD_KEY_COL4__KPP_COL_4 \
2194 IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0)
2195 #define _MX6Q_PAD_KEY_COL4__UART5_CTS \
2196 IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0)
2197 #define _MX6Q_PAD_KEY_COL4__UART5_RTS \
2198 IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0)
2199 #define _MX6Q_PAD_KEY_COL4__GPIO_4_14 \
2200 IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0)
2201 #define _MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \
2202 IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0)
2203 #define _MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \
2204 IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0)
2206 #define _MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \
2207 IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0)
2208 #define _MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \
2209 IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0)
2210 #define _MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \
2211 IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0)
2212 #define _MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \
2213 IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0)
2214 #define _MX6Q_PAD_KEY_ROW4__UART5_CTS \
2215 IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0)
2216 #define _MX6Q_PAD_KEY_ROW4__GPIO_4_15 \
2217 IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0)
2218 #define _MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \
2219 IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0)
2220 #define _MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \
2221 IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0)
2223 #define _MX6Q_PAD_GPIO_0__CCM_CLKO \
2224 IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0)
2225 #define _MX6Q_PAD_GPIO_0__KPP_COL_5 \
2226 IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0)
2227 #define _MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \
2228 IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0)
2229 #define _MX6Q_PAD_GPIO_0__EPIT1_EPITO \
2230 IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0)
2231 #define _MX6Q_PAD_GPIO_0__GPIO_1_0 \
2232 IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0)
2233 #define _MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \
2234 IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0)
2235 #define _MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \
2236 IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0)
2238 #define _MX6Q_PAD_GPIO_1__ESAI1_SCKR \
2239 IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0)
2240 #define _MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \
2241 IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0)
2242 #define _MX6Q_PAD_GPIO_1__KPP_ROW_5 \
2243 IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0)
2244 #define MX6Q_PAD_GPIO_1__USBOTG_ID \
2245 IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, MX6Q_USDHC_PAD_CTRL)
2246 #define _MX6Q_PAD_GPIO_1__PWM2_PWMO \
2247 IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0)
2248 #define _MX6Q_PAD_GPIO_1__GPIO_1_1 \
2249 IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0)
2250 #define _MX6Q_PAD_GPIO_1__USDHC1_CD \
2251 IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0)
2252 #define _MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \
2253 IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0)
2255 #define _MX6Q_PAD_GPIO_9__ESAI1_FSR \
2256 IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0)
2257 #define _MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \
2258 IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0)
2259 #define _MX6Q_PAD_GPIO_9__KPP_COL_6 \
2260 IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0)
2261 #define _MX6Q_PAD_GPIO_9__CCM_REF_EN_B \
2262 IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0)
2263 #define _MX6Q_PAD_GPIO_9__PWM1_PWMO \
2264 IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0)
2265 #define _MX6Q_PAD_GPIO_9__GPIO_1_9 \
2266 IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0)
2267 #define _MX6Q_PAD_GPIO_9__USDHC1_WP \
2268 IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0)
2269 #define _MX6Q_PAD_GPIO_9__SRC_EARLY_RST \
2270 IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0)
2272 #define _MX6Q_PAD_GPIO_3__ESAI1_HCKR \
2273 IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0)
2274 #define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \
2275 IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0)
2276 #define _MX6Q_PAD_GPIO_3__I2C3_SCL \
2277 IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0)
2278 #define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \
2279 IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0)
2280 #define _MX6Q_PAD_GPIO_3__CCM_CLKO2 \
2281 IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0)
2282 #define _MX6Q_PAD_GPIO_3__GPIO_1_3 \
2283 IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0)
2284 #define _MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \
2285 IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0)
2286 #define _MX6Q_PAD_GPIO_3__MLB_MLBCLK \
2287 IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0)
2289 #define _MX6Q_PAD_GPIO_6__ESAI1_SCKT \
2290 IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0)
2291 #define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
2292 IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0)
2293 #define _MX6Q_PAD_GPIO_6__I2C3_SDA \
2294 IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0)
2295 #define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \
2296 IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0)
2297 #define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \
2298 IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0)
2299 #define _MX6Q_PAD_GPIO_6__GPIO_1_6 \
2300 IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0)
2301 #define _MX6Q_PAD_GPIO_6__USDHC2_LCTL \
2302 IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0)
2303 #define _MX6Q_PAD_GPIO_6__MLB_MLBSIG \
2304 IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0)
2306 #define _MX6Q_PAD_GPIO_2__ESAI1_FST \
2307 IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0)
2308 #define _MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \
2309 IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0)
2310 #define _MX6Q_PAD_GPIO_2__KPP_ROW_6 \
2311 IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0)
2312 #define _MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \
2313 IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0)
2314 #define _MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \
2315 IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0)
2316 #define _MX6Q_PAD_GPIO_2__GPIO_1_2 \
2317 IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0)
2318 #define _MX6Q_PAD_GPIO_2__USDHC2_WP \
2319 IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0)
2320 #define _MX6Q_PAD_GPIO_2__MLB_MLBDAT \
2321 IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0)
2323 #define _MX6Q_PAD_GPIO_4__ESAI1_HCKT \
2324 IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0)
2325 #define _MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \
2326 IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0)
2327 #define _MX6Q_PAD_GPIO_4__KPP_COL_7 \
2328 IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0)
2329 #define _MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \
2330 IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0)
2331 #define _MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \
2332 IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0)
2333 #define _MX6Q_PAD_GPIO_4__GPIO_1_4 \
2334 IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0)
2335 #define _MX6Q_PAD_GPIO_4__USDHC2_CD \
2336 IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0)
2337 #define _MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \
2338 IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0)
2340 #define _MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \
2341 IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0)
2342 #define _MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \
2343 IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0)
2344 #define _MX6Q_PAD_GPIO_5__KPP_ROW_7 \
2345 IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0)
2346 #define _MX6Q_PAD_GPIO_5__CCM_CLKO \
2347 IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0)
2348 #define _MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \
2349 IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0)
2350 #define _MX6Q_PAD_GPIO_5__GPIO_1_5 \
2351 IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0)
2352 #define _MX6Q_PAD_GPIO_5__I2C3_SCL \
2353 IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0)
2354 #define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \
2355 IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0)
2357 #define _MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \
2358 IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0)
2359 #define _MX6Q_PAD_GPIO_7__ECSPI5_RDY \
2360 IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0)
2361 #define _MX6Q_PAD_GPIO_7__EPIT1_EPITO \
2362 IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0)
2363 #define _MX6Q_PAD_GPIO_7__CAN1_TXCAN \
2364 IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0)
2365 #define _MX6Q_PAD_GPIO_7__UART2_TXD \
2366 IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0)
2367 #define _MX6Q_PAD_GPIO_7__UART2_RXD \
2368 IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0)
2369 #define _MX6Q_PAD_GPIO_7__GPIO_1_7 \
2370 IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0)
2371 #define _MX6Q_PAD_GPIO_7__SPDIF_PLOCK \
2372 IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0)
2373 #define _MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \
2374 IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0)
2376 #define _MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \
2377 IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0)
2378 #define _MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \
2379 IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0)
2380 #define _MX6Q_PAD_GPIO_8__EPIT2_EPITO \
2381 IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0)
2382 #define _MX6Q_PAD_GPIO_8__CAN1_RXCAN \
2383 IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0)
2384 #define _MX6Q_PAD_GPIO_8__UART2_TXD \
2385 IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0)
2386 #define _MX6Q_PAD_GPIO_8__UART2_RXD \
2387 IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0)
2388 #define _MX6Q_PAD_GPIO_8__GPIO_1_8 \
2389 IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0)
2390 #define _MX6Q_PAD_GPIO_8__SPDIF_SRCLK \
2391 IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0)
2392 #define _MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \
2393 IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0)
2395 #define _MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \
2396 IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0)
2397 #define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \
2398 IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0)
2399 #define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
2400 IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0)
2401 #define _MX6Q_PAD_GPIO_16__USDHC1_LCTL \
2402 IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0)
2403 #define _MX6Q_PAD_GPIO_16__SPDIF_IN1 \
2404 IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0)
2405 #define _MX6Q_PAD_GPIO_16__GPIO_7_11 \
2406 IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0)
2407 #define _MX6Q_PAD_GPIO_16__I2C3_SDA \
2408 IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0)
2409 #define _MX6Q_PAD_GPIO_16__SJC_DE_B \
2410 IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0)
2412 #define _MX6Q_PAD_GPIO_17__ESAI1_TX0 \
2413 IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0)
2414 #define _MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \
2415 IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0)
2416 #define _MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \
2417 IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0)
2418 #define _MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \
2419 IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0)
2420 #define _MX6Q_PAD_GPIO_17__SPDIF_OUT1 \
2421 IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0)
2422 #define _MX6Q_PAD_GPIO_17__GPIO_7_12 \
2423 IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0)
2424 #define _MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \
2425 IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0)
2427 #define _MX6Q_PAD_GPIO_18__ESAI1_TX1 \
2428 IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0)
2429 #define _MX6Q_PAD_GPIO_18__ENET_RX_CLK \
2430 IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0)
2431 #define _MX6Q_PAD_GPIO_18__USDHC3_VSELECT \
2432 IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0)
2433 #define _MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \
2434 IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0)
2435 #define _MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \
2436 IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0)
2437 #define _MX6Q_PAD_GPIO_18__GPIO_7_13 \
2438 IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0)
2439 #define _MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \
2440 IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0)
2441 #define _MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \
2442 IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0)
2444 #define _MX6Q_PAD_GPIO_19__KPP_COL_5 \
2445 IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0)
2446 #define _MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \
2447 IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0)
2448 #define _MX6Q_PAD_GPIO_19__SPDIF_OUT1 \
2449 IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0)
2450 #define _MX6Q_PAD_GPIO_19__CCM_CLKO \
2451 IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0)
2452 #define _MX6Q_PAD_GPIO_19__ECSPI1_RDY \
2453 IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0)
2454 #define _MX6Q_PAD_GPIO_19__GPIO_4_5 \
2455 IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0)
2456 #define _MX6Q_PAD_GPIO_19__ENET_TX_ER \
2457 IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0)
2458 #define _MX6Q_PAD_GPIO_19__SRC_INT_BOOT \
2459 IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0)
2461 #define _MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \
2462 IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0)
2463 #define _MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \
2464 IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0)
2465 #define _MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \
2466 IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0)
2467 #define _MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \
2468 IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0)
2469 #define _MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \
2470 IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0)
2471 #define _MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \
2472 IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0)
2474 #define _MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \
2475 IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0)
2476 #define _MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \
2477 IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0)
2478 #define _MX6Q_PAD_CSI0_MCLK__CCM_CLKO \
2479 IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0)
2480 #define _MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \
2481 IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0)
2482 #define _MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \
2483 IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0)
2484 #define _MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \
2485 IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0)
2486 #define _MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \
2487 IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0)
2489 #define _MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \
2490 IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0)
2491 #define _MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \
2492 IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0)
2493 #define _MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \
2494 IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0)
2495 #define _MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \
2496 IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0)
2497 #define _MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \
2498 IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0)
2499 #define _MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \
2500 IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0)
2501 #define _MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \
2502 IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0)
2504 #define _MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \
2505 IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0)
2506 #define _MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \
2507 IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0)
2508 #define _MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \
2509 IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0)
2510 #define _MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \
2511 IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0)
2512 #define _MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \
2513 IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0)
2514 #define _MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \
2515 IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0)
2516 #define _MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \
2517 IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0)
2519 #define _MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \
2520 IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0)
2521 #define _MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \
2522 IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0)
2523 #define _MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \
2524 IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0)
2525 #define _MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \
2526 IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0)
2527 #define _MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \
2528 IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0)
2529 #define _MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \
2530 IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0)
2531 #define _MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \
2532 IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0)
2533 #define _MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \
2534 IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0)
2536 #define _MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \
2537 IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0)
2538 #define _MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \
2539 IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0)
2540 #define _MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \
2541 IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0)
2542 #define _MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \
2543 IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0)
2544 #define _MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \
2545 IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0)
2546 #define _MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \
2547 IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0)
2548 #define _MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \
2549 IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0)
2550 #define _MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \
2551 IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0)
2553 #define _MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \
2554 IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0)
2555 #define _MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \
2556 IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0)
2557 #define _MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \
2558 IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0)
2559 #define _MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \
2560 IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0)
2561 #define _MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \
2562 IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0)
2563 #define _MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \
2564 IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0)
2565 #define _MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \
2566 IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0)
2567 #define _MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \
2568 IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0)
2570 #define _MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \
2571 IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0)
2572 #define _MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \
2573 IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0)
2574 #define _MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \
2575 IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0)
2576 #define _MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \
2577 IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0)
2578 #define _MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \
2579 IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0)
2580 #define _MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \
2581 IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0)
2582 #define _MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \
2583 IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0)
2584 #define _MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \
2585 IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0)
2587 #define _MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \
2588 IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0)
2589 #define _MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \
2590 IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0)
2591 #define _MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \
2592 IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0)
2593 #define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \
2594 IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0)
2595 #define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA \
2596 IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0)
2597 #define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \
2598 IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0)
2599 #define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \
2600 IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0)
2601 #define _MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \
2602 IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0)
2604 #define _MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \
2605 IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0)
2606 #define _MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \
2607 IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0)
2608 #define _MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \
2609 IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0)
2610 #define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \
2611 IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0)
2612 #define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL \
2613 IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0)
2614 #define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \
2615 IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0)
2616 #define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \
2617 IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0)
2618 #define _MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \
2619 IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0)
2621 #define _MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \
2622 IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0)
2623 #define _MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \
2624 IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0)
2625 #define _MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \
2626 IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0)
2627 #define _MX6Q_PAD_CSI0_DAT10__UART1_TXD \
2628 IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0)
2629 #define _MX6Q_PAD_CSI0_DAT10__UART1_RXD \
2630 IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0)
2631 #define _MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \
2632 IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0)
2633 #define _MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \
2634 IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0)
2635 #define _MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \
2636 IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0)
2637 #define _MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \
2638 IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0)
2640 #define _MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \
2641 IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0)
2642 #define _MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \
2643 IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0)
2644 #define _MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \
2645 IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0)
2646 #define _MX6Q_PAD_CSI0_DAT11__UART1_TXD \
2647 IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0)
2648 #define _MX6Q_PAD_CSI0_DAT11__UART1_RXD \
2649 IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0)
2650 #define _MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \
2651 IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0)
2652 #define _MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \
2653 IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0)
2654 #define _MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \
2655 IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0)
2656 #define _MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \
2657 IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0)
2659 #define _MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \
2660 IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0)
2661 #define _MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \
2662 IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0)
2663 #define _MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \
2664 IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0)
2665 #define _MX6Q_PAD_CSI0_DAT12__UART4_TXD \
2666 IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0)
2667 #define _MX6Q_PAD_CSI0_DAT12__UART4_RXD \
2668 IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0)
2669 #define _MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \
2670 IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0)
2671 #define _MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \
2672 IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0)
2673 #define _MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \
2674 IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0)
2675 #define _MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \
2676 IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0)
2678 #define _MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \
2679 IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0)
2680 #define _MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \
2681 IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0)
2682 #define _MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \
2683 IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0)
2684 #define _MX6Q_PAD_CSI0_DAT13__UART4_TXD \
2685 IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0)
2686 #define _MX6Q_PAD_CSI0_DAT13__UART4_RXD \
2687 IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0)
2688 #define _MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \
2689 IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0)
2690 #define _MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \
2691 IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0)
2692 #define _MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \
2693 IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0)
2694 #define _MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \
2695 IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0)
2697 #define _MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \
2698 IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0)
2699 #define _MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \
2700 IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0)
2701 #define _MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \
2702 IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0)
2703 #define _MX6Q_PAD_CSI0_DAT14__UART5_TXD \
2704 IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0)
2705 #define _MX6Q_PAD_CSI0_DAT14__UART5_RXD \
2706 IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0)
2707 #define _MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \
2708 IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0)
2709 #define _MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \
2710 IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0)
2711 #define _MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \
2712 IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0)
2713 #define _MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \
2714 IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0)
2716 #define _MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \
2717 IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0)
2718 #define _MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \
2719 IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0)
2720 #define _MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \
2721 IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0)
2722 #define _MX6Q_PAD_CSI0_DAT15__UART5_TXD \
2723 IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0)
2724 #define _MX6Q_PAD_CSI0_DAT15__UART5_RXD \
2725 IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0)
2726 #define _MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \
2727 IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0)
2728 #define _MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \
2729 IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0)
2730 #define _MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \
2731 IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0)
2732 #define _MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \
2733 IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0)
2735 #define _MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \
2736 IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0)
2737 #define _MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \
2738 IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0)
2739 #define _MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \
2740 IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0)
2741 #define _MX6Q_PAD_CSI0_DAT16__UART4_CTS \
2742 IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0)
2743 #define _MX6Q_PAD_CSI0_DAT16__UART4_RTS \
2744 IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0)
2745 #define _MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \
2746 IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0)
2747 #define _MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \
2748 IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0)
2749 #define _MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \
2750 IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0)
2751 #define _MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \
2752 IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0)
2754 #define _MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \
2755 IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0)
2756 #define _MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \
2757 IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0)
2758 #define _MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \
2759 IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0)
2760 #define _MX6Q_PAD_CSI0_DAT17__UART4_CTS \
2761 IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0)
2762 #define _MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \
2763 IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0)
2764 #define _MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \
2765 IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0)
2766 #define _MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \
2767 IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0)
2768 #define _MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \
2769 IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0)
2771 #define _MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \
2772 IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0)
2773 #define _MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \
2774 IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0)
2775 #define _MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \
2776 IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0)
2777 #define _MX6Q_PAD_CSI0_DAT18__UART5_CTS \
2778 IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0)
2779 #define _MX6Q_PAD_CSI0_DAT18__UART5_RTS \
2780 IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0)
2781 #define _MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \
2782 IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0)
2783 #define _MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \
2784 IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0)
2785 #define _MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \
2786 IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0)
2787 #define _MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \
2788 IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0)
2790 #define _MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \
2791 IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0)
2792 #define _MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \
2793 IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0)
2794 #define _MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \
2795 IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0)
2796 #define _MX6Q_PAD_CSI0_DAT19__UART5_CTS \
2797 IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0)
2798 #define _MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \
2799 IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0)
2800 #define _MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \
2801 IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0)
2802 #define _MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \
2803 IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0)
2804 #define _MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \
2805 IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0)
2807 #define _MX6Q_PAD_JTAG_TMS__SJC_TMS \
2808 IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0)
2810 #define _MX6Q_PAD_JTAG_MOD__SJC_MOD \
2811 IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0)
2813 #define _MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \
2814 IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0)
2816 #define _MX6Q_PAD_JTAG_TDI__SJC_TDI \
2817 IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0)
2819 #define _MX6Q_PAD_JTAG_TCK__SJC_TCK \
2820 IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0)
2822 #define _MX6Q_PAD_JTAG_TDO__SJC_TDO \
2823 IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0)
2825 #define _MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \
2826 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2828 #define _MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \
2829 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2831 #define _MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \
2832 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2834 #define _MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \
2835 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2837 #define _MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \
2838 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2840 #define _MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \
2841 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2843 #define _MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \
2844 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2846 #define _MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \
2847 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2849 #define _MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \
2850 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2852 #define _MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \
2853 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2855 #define _MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \
2856 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2858 #define _MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \
2859 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2861 #define _MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \
2862 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2864 #define _MX6Q_PAD_POR_B__SRC_POR_B \
2865 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2867 #define _MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \
2868 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2870 #define _MX6Q_PAD_RESET_IN_B__SRC_RESET_B \
2871 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2873 #define _MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \
2874 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2876 #define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \
2877 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2879 #define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 \
2880 IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0)
2881 #define _MX6Q_PAD_SD3_DAT7__UART1_TXD \
2882 IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0)
2883 #define _MX6Q_PAD_SD3_DAT7__UART1_RXD \
2884 IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0)
2885 #define _MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \
2886 IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0)
2887 #define _MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \
2888 IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0)
2889 #define _MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \
2890 IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0)
2891 #define _MX6Q_PAD_SD3_DAT7__GPIO_6_17 \
2892 IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
2893 #define _MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \
2894 IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0)
2895 #define _MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \
2896 IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0)
2898 #define _MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 \
2899 IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0)
2900 #define _MX6Q_PAD_SD3_DAT6__UART1_TXD \
2901 IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0)
2902 #define _MX6Q_PAD_SD3_DAT6__UART1_RXD \
2903 IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0)
2904 #define _MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \
2905 IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0)
2906 #define _MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \
2907 IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0)
2908 #define _MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \
2909 IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0)
2910 #define _MX6Q_PAD_SD3_DAT6__GPIO_6_18 \
2911 IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0)
2912 #define _MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \
2913 IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0)
2914 #define _MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \
2915 IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0)
2917 #define _MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 \
2918 IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0)
2919 #define _MX6Q_PAD_SD3_DAT5__UART2_TXD \
2920 IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0)
2921 #define _MX6Q_PAD_SD3_DAT5__UART2_RXD \
2922 IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0)
2923 #define _MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \
2924 IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0)
2925 #define _MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \
2926 IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0)
2927 #define _MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \
2928 IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0)
2929 #define _MX6Q_PAD_SD3_DAT5__GPIO_7_0 \
2930 IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0)
2931 #define _MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \
2932 IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0)
2933 #define _MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \
2934 IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0)
2936 #define _MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 \
2937 IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0)
2938 #define _MX6Q_PAD_SD3_DAT4__UART2_TXD \
2939 IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0)
2940 #define _MX6Q_PAD_SD3_DAT4__UART2_RXD \
2941 IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0)
2942 #define _MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \
2943 IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0)
2944 #define _MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \
2945 IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0)
2946 #define _MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \
2947 IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0)
2948 #define _MX6Q_PAD_SD3_DAT4__GPIO_7_1 \
2949 IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0)
2950 #define _MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \
2951 IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0)
2952 #define _MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \
2953 IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0)
2955 #define _MX6Q_PAD_SD3_CMD__USDHC3_CMD \
2956 IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
2957 #define _MX6Q_PAD_SD3_CMD__UART2_CTS \
2958 IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0)
2959 #define _MX6Q_PAD_SD3_CMD__CAN1_TXCAN \
2960 IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0)
2961 #define _MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \
2962 IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0)
2963 #define _MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \
2964 IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0)
2965 #define _MX6Q_PAD_SD3_CMD__GPIO_7_2 \
2966 IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0)
2967 #define _MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \
2968 IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0)
2969 #define _MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \
2970 IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0)
2972 #define _MX6Q_PAD_SD3_CLK__USDHC3_CLK \
2973 IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0)
2974 #define _MX6Q_PAD_SD3_CLK__UART2_CTS \
2975 IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0)
2976 #define _MX6Q_PAD_SD3_CLK__UART2_RTS \
2977 IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0)
2978 #define _MX6Q_PAD_SD3_CLK__CAN1_RXCAN \
2979 IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0)
2980 #define _MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \
2981 IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0)
2982 #define _MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \
2983 IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0)
2984 #define _MX6Q_PAD_SD3_CLK__GPIO_7_3 \
2985 IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0)
2986 #define _MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \
2987 IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0)
2988 #define _MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \
2989 IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0)
2991 #define _MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 \
2992 IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0)
2993 #define _MX6Q_PAD_SD3_DAT0__UART1_CTS \
2994 IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0)
2995 #define _MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \
2996 IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0)
2997 #define _MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
2998 IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0)
2999 #define _MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \
3000 IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0)
3001 #define _MX6Q_PAD_SD3_DAT0__GPIO_7_4 \
3002 IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0)
3003 #define _MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \
3004 IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0)
3005 #define _MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \
3006 IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0)
3008 #define _MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 \
3009 IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0)
3010 #define _MX6Q_PAD_SD3_DAT1__UART1_CTS \
3011 IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0)
3012 #define _MX6Q_PAD_SD3_DAT1__UART1_RTS \
3013 IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0)
3014 #define _MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \
3015 IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0)
3016 #define _MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \
3017 IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0)
3018 #define _MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \
3019 IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0)
3020 #define _MX6Q_PAD_SD3_DAT1__GPIO_7_5 \
3021 IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0)
3022 #define _MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \
3023 IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0)
3024 #define _MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \
3025 IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0)
3027 #define _MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 \
3028 IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0)
3029 #define _MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \
3030 IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0)
3031 #define _MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \
3032 IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0)
3033 #define _MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \
3034 IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0)
3035 #define _MX6Q_PAD_SD3_DAT2__GPIO_7_6 \
3036 IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0)
3037 #define _MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \
3038 IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0)
3039 #define _MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \
3040 IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0)
3042 #define _MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 \
3043 IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0)
3044 #define _MX6Q_PAD_SD3_DAT3__UART3_CTS \
3045 IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0)
3046 #define _MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \
3047 IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0)
3048 #define _MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \
3049 IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0)
3050 #define _MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \
3051 IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0)
3052 #define _MX6Q_PAD_SD3_DAT3__GPIO_7_7 \
3053 IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0)
3054 #define _MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \
3055 IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0)
3056 #define _MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \
3057 IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0)
3059 #define _MX6Q_PAD_SD3_RST__USDHC3_RST \
3060 IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0)
3061 #define _MX6Q_PAD_SD3_RST__UART3_CTS \
3062 IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0)
3063 #define _MX6Q_PAD_SD3_RST__UART3_RTS \
3064 IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0)
3065 #define _MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \
3066 IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0)
3067 #define _MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \
3068 IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0)
3069 #define _MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \
3070 IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0)
3071 #define _MX6Q_PAD_SD3_RST__GPIO_7_8 \
3072 IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0)
3073 #define _MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \
3074 IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0)
3075 #define _MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \
3076 IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0)
3078 #define _MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \
3079 IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0)
3080 #define _MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \
3081 IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0)
3082 #define _MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \
3083 IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0)
3084 #define _MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \
3085 IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0)
3086 #define _MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \
3087 IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0)
3088 #define _MX6Q_PAD_NANDF_CLE__GPIO_6_7 \
3089 IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0)
3090 #define _MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \
3091 IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0)
3092 #define _MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \
3093 IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0)
3095 #define _MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \
3096 IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0)
3097 #define _MX6Q_PAD_NANDF_ALE__USDHC4_RST \
3098 IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0)
3099 #define _MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \
3100 IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0)
3101 #define _MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \
3102 IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0)
3103 #define _MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \
3104 IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0)
3105 #define _MX6Q_PAD_NANDF_ALE__GPIO_6_8 \
3106 IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0)
3107 #define _MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \
3108 IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0)
3109 #define _MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \
3110 IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0)
3112 #define _MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \
3113 IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0)
3114 #define _MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \
3115 IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0)
3116 #define _MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \
3117 IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0)
3118 #define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \
3119 IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0)
3120 #define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \
3121 IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0)
3122 #define _MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \
3123 IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0)
3124 #define _MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \
3125 IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0)
3126 #define _MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \
3127 IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0)
3129 #define _MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \
3130 IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0)
3131 #define _MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \
3132 IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0)
3133 #define _MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \
3134 IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0)
3135 #define _MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \
3136 IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0)
3137 #define _MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \
3138 IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0)
3139 #define _MX6Q_PAD_NANDF_RB0__GPIO_6_10 \
3140 IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0)
3141 #define _MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \
3142 IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0)
3143 #define _MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \
3144 IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0)
3146 #define _MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \
3147 IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0)
3148 #define _MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \
3149 IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0)
3150 #define _MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \
3151 IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0)
3152 #define _MX6Q_PAD_NANDF_CS0__GPIO_6_11 \
3153 IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0)
3154 #define _MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \
3155 IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0)
3157 #define _MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \
3158 IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0)
3159 #define _MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \
3160 IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0)
3161 #define _MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \
3162 IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0)
3163 #define _MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \
3164 IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0)
3165 #define _MX6Q_PAD_NANDF_CS1__GPIO_6_14 \
3166 IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0)
3167 #define _MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \
3168 IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0)
3170 #define _MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \
3171 IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0)
3172 #define _MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \
3173 IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0)
3174 #define _MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \
3175 IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0)
3176 #define _MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \
3177 IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0)
3178 #define _MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \
3179 IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0)
3180 #define _MX6Q_PAD_NANDF_CS2__GPIO_6_15 \
3181 IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0)
3182 #define _MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \
3183 IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0)
3185 #define _MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \
3186 IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0)
3187 #define _MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \
3188 IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0)
3189 #define _MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \
3190 IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0)
3191 #define _MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \
3192 IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0)
3193 #define _MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \
3194 IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0)
3195 #define _MX6Q_PAD_NANDF_CS3__GPIO_6_16 \
3196 IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0)
3197 #define _MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \
3198 IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0)
3199 #define _MX6Q_PAD_NANDF_CS3__TPSMP_CLK \
3200 IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0)
3202 #define _MX6Q_PAD_SD4_CMD__USDHC4_CMD \
3203 IOMUX_PAD(0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
3204 #define _MX6Q_PAD_SD4_CMD__RAWNAND_RDN \
3205 IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0)
3206 #define _MX6Q_PAD_SD4_CMD__UART3_TXD \
3207 IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0)
3208 #define _MX6Q_PAD_SD4_CMD__UART3_RXD \
3209 IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0)
3210 #define _MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \
3211 IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0)
3212 #define _MX6Q_PAD_SD4_CMD__GPIO_7_9 \
3213 IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0)
3214 #define _MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \
3215 IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0)
3217 #define _MX6Q_PAD_SD4_CLK__USDHC4_CLK \
3218 IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0)
3219 #define _MX6Q_PAD_SD4_CLK__RAWNAND_WRN \
3220 IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0)
3221 #define _MX6Q_PAD_SD4_CLK__UART3_TXD \
3222 IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0)
3223 #define _MX6Q_PAD_SD4_CLK__UART3_RXD \
3224 IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0)
3225 #define _MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \
3226 IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0)
3227 #define _MX6Q_PAD_SD4_CLK__GPIO_7_10 \
3228 IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0)
3230 #define _MX6Q_PAD_NANDF_D0__RAWNAND_D0 \
3231 IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0)
3232 #define _MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \
3233 IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0)
3234 #define _MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \
3235 IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0)
3236 #define _MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \
3237 IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0)
3238 #define _MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \
3239 IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0)
3240 #define _MX6Q_PAD_NANDF_D0__GPIO_2_0 \
3241 IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0)
3242 #define _MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \
3243 IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0)
3244 #define _MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \
3245 IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0)
3247 #define _MX6Q_PAD_NANDF_D1__RAWNAND_D1 \
3248 IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0)
3249 #define _MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \
3250 IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0)
3251 #define _MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \
3252 IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0)
3253 #define _MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \
3254 IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0)
3255 #define _MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \
3256 IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0)
3257 #define _MX6Q_PAD_NANDF_D1__GPIO_2_1 \
3258 IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0)
3259 #define _MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \
3260 IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0)
3261 #define _MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \
3262 IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0)
3264 #define _MX6Q_PAD_NANDF_D2__RAWNAND_D2 \
3265 IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0)
3266 #define _MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \
3267 IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0)
3268 #define _MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \
3269 IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0)
3270 #define _MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \
3271 IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0)
3272 #define _MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \
3273 IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0)
3274 #define _MX6Q_PAD_NANDF_D2__GPIO_2_2 \
3275 IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0)
3276 #define _MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \
3277 IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0)
3278 #define _MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \
3279 IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0)
3281 #define _MX6Q_PAD_NANDF_D3__RAWNAND_D3 \
3282 IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0)
3283 #define _MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \
3284 IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0)
3285 #define _MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \
3286 IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0)
3287 #define _MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \
3288 IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0)
3289 #define _MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \
3290 IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0)
3291 #define _MX6Q_PAD_NANDF_D3__GPIO_2_3 \
3292 IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0)
3293 #define _MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \
3294 IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0)
3295 #define _MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \
3296 IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0)
3298 #define _MX6Q_PAD_NANDF_D4__RAWNAND_D4 \
3299 IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0)
3300 #define _MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \
3301 IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0)
3302 #define _MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \
3303 IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0)
3304 #define _MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \
3305 IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0)
3306 #define _MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \
3307 IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0)
3308 #define _MX6Q_PAD_NANDF_D4__GPIO_2_4 \
3309 IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0)
3310 #define _MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \
3311 IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0)
3312 #define _MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \
3313 IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0)
3315 #define _MX6Q_PAD_NANDF_D5__RAWNAND_D5 \
3316 IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0)
3317 #define _MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \
3318 IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0)
3319 #define _MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \
3320 IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0)
3321 #define _MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \
3322 IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0)
3323 #define _MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \
3324 IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0)
3325 #define _MX6Q_PAD_NANDF_D5__GPIO_2_5 \
3326 IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0)
3327 #define _MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \
3328 IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0)
3329 #define _MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \
3330 IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0)
3332 #define _MX6Q_PAD_NANDF_D6__RAWNAND_D6 \
3333 IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0)
3334 #define _MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \
3335 IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0)
3336 #define _MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \
3337 IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0)
3338 #define _MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \
3339 IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0)
3340 #define _MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \
3341 IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0)
3342 #define _MX6Q_PAD_NANDF_D6__GPIO_2_6 \
3343 IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0)
3344 #define _MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \
3345 IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0)
3346 #define _MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \
3347 IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0)
3349 #define _MX6Q_PAD_NANDF_D7__RAWNAND_D7 \
3350 IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0)
3351 #define _MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \
3352 IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0)
3353 #define _MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \
3354 IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0)
3355 #define _MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \
3356 IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0)
3357 #define _MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \
3358 IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0)
3359 #define _MX6Q_PAD_NANDF_D7__GPIO_2_7 \
3360 IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0)
3361 #define _MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \
3362 IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0)
3363 #define _MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \
3364 IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0)
3366 #define _MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \
3367 IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0)
3368 #define _MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 \
3369 IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0)
3370 #define _MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \
3371 IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0)
3372 #define _MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \
3373 IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0)
3374 #define _MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \
3375 IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0)
3376 #define _MX6Q_PAD_SD4_DAT0__GPIO_2_8 \
3377 IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0)
3378 #define _MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \
3379 IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0)
3380 #define _MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \
3381 IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0)
3383 #define _MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \
3384 IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0)
3385 #define _MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 \
3386 IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0)
3387 #define _MX6Q_PAD_SD4_DAT1__PWM3_PWMO \
3388 IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0)
3389 #define _MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \
3390 IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0)
3391 #define _MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \
3392 IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0)
3393 #define _MX6Q_PAD_SD4_DAT1__GPIO_2_9 \
3394 IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0)
3395 #define _MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \
3396 IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0)
3397 #define _MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \
3398 IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0)
3400 #define _MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \
3401 IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0)
3402 #define _MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 \
3403 IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0)
3404 #define _MX6Q_PAD_SD4_DAT2__PWM4_PWMO \
3405 IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0)
3406 #define _MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \
3407 IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0)
3408 #define _MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \
3409 IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0)
3410 #define _MX6Q_PAD_SD4_DAT2__GPIO_2_10 \
3411 IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0)
3412 #define _MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \
3413 IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0)
3414 #define _MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \
3415 IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0)
3417 #define _MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \
3418 IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0)
3419 #define _MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 \
3420 IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0)
3421 #define _MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \
3422 IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0)
3423 #define _MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \
3424 IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0)
3425 #define _MX6Q_PAD_SD4_DAT3__GPIO_2_11 \
3426 IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0)
3427 #define _MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \
3428 IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0)
3429 #define _MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \
3430 IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0)
3432 #define _MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \
3433 IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0)
3434 #define _MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 \
3435 IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0)
3436 #define _MX6Q_PAD_SD4_DAT4__UART2_TXD \
3437 IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0)
3438 #define _MX6Q_PAD_SD4_DAT4__UART2_RXD \
3439 IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0)
3440 #define _MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \
3441 IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0)
3442 #define _MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \
3443 IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0)
3444 #define _MX6Q_PAD_SD4_DAT4__GPIO_2_12 \
3445 IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0)
3446 #define _MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \
3447 IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0)
3448 #define _MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \
3449 IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0)
3451 #define _MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \
3452 IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0)
3453 #define _MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 \
3454 IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0)
3455 #define _MX6Q_PAD_SD4_DAT5__UART2_CTS \
3456 IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0)
3457 #define _MX6Q_PAD_SD4_DAT5__UART2_RTS \
3458 IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0)
3459 #define _MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \
3460 IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0)
3461 #define _MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \
3462 IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0)
3463 #define _MX6Q_PAD_SD4_DAT5__GPIO_2_13 \
3464 IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0)
3465 #define _MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \
3466 IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0)
3467 #define _MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \
3468 IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0)
3470 #define _MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \
3471 IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0)
3472 #define _MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 \
3473 IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0)
3474 #define _MX6Q_PAD_SD4_DAT6__UART2_CTS \
3475 IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0)
3476 #define _MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \
3477 IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0)
3478 #define _MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \
3479 IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0)
3480 #define _MX6Q_PAD_SD4_DAT6__GPIO_2_14 \
3481 IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0)
3482 #define _MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \
3483 IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0)
3484 #define _MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \
3485 IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0)
3487 #define _MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \
3488 IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0)
3489 #define _MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 \
3490 IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0)
3491 #define _MX6Q_PAD_SD4_DAT7__UART2_TXD \
3492 IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0)
3493 #define _MX6Q_PAD_SD4_DAT7__UART2_RXD \
3494 IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0)
3495 #define _MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \
3496 IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0)
3497 #define _MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \
3498 IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0)
3499 #define _MX6Q_PAD_SD4_DAT7__GPIO_2_15 \
3500 IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0)
3501 #define _MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \
3502 IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0)
3503 #define _MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \
3504 IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0)
3506 #define _MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \
3507 IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0)
3508 #define _MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \
3509 IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0)
3510 #define _MX6Q_PAD_SD1_DAT1__PWM3_PWMO \
3511 IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0)
3512 #define _MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \
3513 IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0)
3514 #define _MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \
3515 IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0)
3516 #define _MX6Q_PAD_SD1_DAT1__GPIO_1_17 \
3517 IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0)
3518 #define _MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \
3519 IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0)
3520 #define _MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \
3521 IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0)
3523 #define _MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \
3524 IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0)
3525 #define _MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \
3526 IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0)
3527 #define _MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \
3528 IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0)
3529 #define _MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \
3530 IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0)
3531 #define _MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \
3532 IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0)
3533 #define _MX6Q_PAD_SD1_DAT0__GPIO_1_16 \
3534 IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0)
3535 #define _MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \
3536 IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0)
3537 #define _MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \
3538 IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0)
3540 #define _MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \
3541 IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0)
3542 #define _MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \
3543 IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0)
3544 #define _MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \
3545 IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0)
3546 #define _MX6Q_PAD_SD1_DAT3__PWM1_PWMO \
3547 IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0)
3548 #define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \
3549 IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0)
3550 #define _MX6Q_PAD_SD1_DAT3__GPIO_1_21 \
3551 IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0)
3552 #define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \
3553 IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0)
3554 #define _MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \
3555 IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0)
3557 #define _MX6Q_PAD_SD1_CMD__USDHC1_CMD \
3558 IOMUX_PAD(0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
3559 #define _MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \
3560 IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0)
3561 #define _MX6Q_PAD_SD1_CMD__PWM4_PWMO \
3562 IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0)
3563 #define _MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \
3564 IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0)
3565 #define _MX6Q_PAD_SD1_CMD__GPIO_1_18 \
3566 IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0)
3567 #define _MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \
3568 IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0)
3570 #define _MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \
3571 IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0)
3572 #define _MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \
3573 IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0)
3574 #define _MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \
3575 IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0)
3576 #define _MX6Q_PAD_SD1_DAT2__PWM2_PWMO \
3577 IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0)
3578 #define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \
3579 IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0)
3580 #define _MX6Q_PAD_SD1_DAT2__GPIO_1_19 \
3581 IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0)
3582 #define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \
3583 IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0)
3584 #define _MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \
3585 IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0)
3587 #define _MX6Q_PAD_SD1_CLK__USDHC1_CLK \
3588 IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0)
3589 #define _MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \
3590 IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0)
3591 #define _MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \
3592 IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0)
3593 #define _MX6Q_PAD_SD1_CLK__GPT_CLKIN \
3594 IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0)
3595 #define _MX6Q_PAD_SD1_CLK__GPIO_1_20 \
3596 IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0)
3597 #define _MX6Q_PAD_SD1_CLK__PHY_DTB_0 \
3598 IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0)
3599 #define _MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \
3600 IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0)
3602 #define _MX6Q_PAD_SD2_CLK__USDHC2_CLK \
3603 IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0)
3604 #define _MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \
3605 IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0)
3606 #define _MX6Q_PAD_SD2_CLK__KPP_COL_5 \
3607 IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0)
3608 #define _MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \
3609 IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0)
3610 #define _MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \
3611 IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0)
3612 #define _MX6Q_PAD_SD2_CLK__GPIO_1_10 \
3613 IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0)
3614 #define _MX6Q_PAD_SD2_CLK__PHY_DTB_1 \
3615 IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0)
3616 #define _MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \
3617 IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0)
3619 #define _MX6Q_PAD_SD2_CMD__USDHC2_CMD \
3620 IOMUX_PAD(0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
3621 #define _MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \
3622 IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0)
3623 #define _MX6Q_PAD_SD2_CMD__KPP_ROW_5 \
3624 IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0)
3625 #define _MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \
3626 IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0)
3627 #define _MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \
3628 IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0)
3629 #define _MX6Q_PAD_SD2_CMD__GPIO_1_11 \
3630 IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0)
3632 #define _MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \
3633 IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0)
3634 #define _MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \
3635 IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0)
3636 #define _MX6Q_PAD_SD2_DAT3__KPP_COL_6 \
3637 IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0)
3638 #define _MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \
3639 IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0)
3640 #define _MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \
3641 IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0)
3642 #define _MX6Q_PAD_SD2_DAT3__GPIO_1_12 \
3643 IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0)
3644 #define _MX6Q_PAD_SD2_DAT3__SJC_DONE \
3645 IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0)
3646 #define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \
3647 IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0)
3651 #define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
3652 (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
3653 #define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
3654 (_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3655 #define MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \
3656 (_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3657 #define MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \
3658 (_MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
3659 #define MX6Q_PAD_SD2_DAT1__KPP_COL_7 \
3660 (_MX6Q_PAD_SD2_DAT1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
3661 #define MX6Q_PAD_SD2_DAT1__GPIO_1_14 \
3662 (_MX6Q_PAD_SD2_DAT1__GPIO_1_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
3663 #define MX6Q_PAD_SD2_DAT1__CCM_WAIT \
3664 (_MX6Q_PAD_SD2_DAT1__CCM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
3665 #define MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \
3666 (_MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3668 #define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \
3669 (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
3670 #define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \
3671 (_MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3672 #define MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \
3673 (_MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
3674 #define MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \
3675 (_MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
3676 #define MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \
3677 (_MX6Q_PAD_SD2_DAT2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
3678 #define MX6Q_PAD_SD2_DAT2__GPIO_1_13 \
3679 (_MX6Q_PAD_SD2_DAT2__GPIO_1_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
3680 #define MX6Q_PAD_SD2_DAT2__CCM_STOP \
3681 (_MX6Q_PAD_SD2_DAT2__CCM_STOP | MUX_PAD_CTRL(NO_PAD_CTRL))
3682 #define MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \
3683 (_MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3685 #define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \
3686 (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
3687 #define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \
3688 (_MX6Q_PAD_SD2_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
3689 #define MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
3690 (_MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
3691 #define MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \
3692 (_MX6Q_PAD_SD2_DAT0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
3693 #define MX6Q_PAD_SD2_DAT0__GPIO_1_15 \
3694 (_MX6Q_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
3695 #define MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \
3696 (_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
3697 #define MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \
3698 (_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3701 #define MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \
3702 (_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
3703 #define MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \
3704 (_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3705 #define MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \
3706 (_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
3707 #define MX6Q_PAD_RGMII_TXC__GPIO_6_19 \
3708 (_MX6Q_PAD_RGMII_TXC__GPIO_6_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
3709 #define MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \
3710 (_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3711 #define MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \
3712 (_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
3715 #define MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \
3716 (_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
3717 #define MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \
3718 (_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3719 #define MX6Q_PAD_RGMII_TD0__GPIO_6_20 \
3720 (_MX6Q_PAD_RGMII_TD0__GPIO_6_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
3721 #define MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \
3722 (_MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3724 #define MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \
3725 (_MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
3726 #define MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \
3727 (_MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3728 #define MX6Q_PAD_RGMII_TD1__GPIO_6_21 \
3729 (_MX6Q_PAD_RGMII_TD1__GPIO_6_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
3730 #define MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \
3731 (_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3732 #define MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \
3733 (_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
3736 #define MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \
3737 (_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
3738 #define MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \
3739 (_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3740 #define MX6Q_PAD_RGMII_TD2__GPIO_6_22 \
3741 (_MX6Q_PAD_RGMII_TD2__GPIO_6_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
3742 #define MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \
3743 (_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
3744 #define MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \
3745 (_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
3748 #define MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \
3749 (_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
3750 #define MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \
3751 (_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3752 #define MX6Q_PAD_RGMII_TD3__GPIO_6_23 \
3753 (_MX6Q_PAD_RGMII_TD3__GPIO_6_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
3754 #define MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \
3755 (_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
3758 #define MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \
3759 (_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
3760 #define MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \
3761 (_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3762 #define MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \
3763 (_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
3764 #define MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \
3765 (_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
3768 #define MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \
3769 (_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
3770 #define MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \
3771 (_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3772 #define MX6Q_PAD_RGMII_RD0__GPIO_6_25 \
3773 (_MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
3774 #define MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \
3775 (_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
3778 #define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \
3779 (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | MUX_PAD_CTRL(NO_PAD_CTRL))
3780 #define MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \
3781 (_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3782 #define MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \
3783 (_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
3784 #define MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \
3785 (_MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
3786 #define MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \
3787 (_MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
3789 #define MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \
3790 (_MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
3791 #define MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \
3792 (_MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3793 #define MX6Q_PAD_RGMII_RD1__GPIO_6_27 \
3794 (_MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
3795 #define MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \
3796 (_MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
3797 #define MX6Q_PAD_RGMII_RD1__SJC_FAIL \
3798 (_MX6Q_PAD_RGMII_RD1__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL))
3800 #define MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \
3801 (_MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
3802 #define MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \
3803 (_MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3804 #define MX6Q_PAD_RGMII_RD2__GPIO_6_28 \
3805 (_MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
3806 #define MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \
3807 (_MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
3809 #define MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \
3810 (_MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
3811 #define MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \
3812 (_MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3813 #define MX6Q_PAD_RGMII_RD3__GPIO_6_29 \
3814 (_MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
3815 #define MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \
3816 (_MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
3818 #define MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \
3819 (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE | MUX_PAD_CTRL(NO_PAD_CTRL))
3820 #define MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \
3821 (_MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3822 #define MX6Q_PAD_RGMII_RXC__GPIO_6_30 \
3823 (_MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
3824 #define MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \
3825 (_MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
3827 #define MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \
3828 (_MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
3829 #define MX6Q_PAD_EIM_A25__ECSPI4_SS1 \
3830 (_MX6Q_PAD_EIM_A25__ECSPI4_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3831 #define MX6Q_PAD_EIM_A25__ECSPI2_RDY \
3832 (_MX6Q_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
3833 #define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \
3834 (_MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
3835 #define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \
3836 (_MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
3837 #define MX6Q_PAD_EIM_A25__GPIO_5_2 \
3838 (_MX6Q_PAD_EIM_A25__GPIO_5_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3839 #define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \
3840 (_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
3841 #define MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \
3842 (_MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3844 #define MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \
3845 (_MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3846 #define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \
3847 (_MX6Q_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3848 #define MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \
3849 (_MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
3850 #define MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \
3851 (_MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
3852 #define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \
3853 (_MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
3854 #define MX6Q_PAD_EIM_EB2__GPIO_2_30 \
3855 (_MX6Q_PAD_EIM_EB2__GPIO_2_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
3856 #define MX6Q_PAD_EIM_EB2__I2C2_SCL \
3857 (_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
3858 #define MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \
3859 (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
3861 #define MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \
3862 (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
3863 #define MX6Q_PAD_EIM_D16__ECSPI1_SCLK \
3864 (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
3865 #define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \
3866 (_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
3867 #define MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \
3868 (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
3869 #define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \
3870 (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
3871 #define MX6Q_PAD_EIM_D16__GPIO_3_16 \
3872 (_MX6Q_PAD_EIM_D16__GPIO_3_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
3873 #define MX6Q_PAD_EIM_D16__I2C2_SDA \
3874 (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
3876 #define MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \
3877 (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
3878 #define MX6Q_PAD_EIM_D17__ECSPI1_MISO \
3879 (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
3880 #define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \
3881 (_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
3882 #define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \
3883 (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
3884 #define MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \
3885 (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
3886 #define MX6Q_PAD_EIM_D17__GPIO_3_17 \
3887 (_MX6Q_PAD_EIM_D17__GPIO_3_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
3888 #define MX6Q_PAD_EIM_D17__I2C3_SCL \
3889 (_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
3890 #define MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \
3891 (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3893 #define MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \
3894 (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
3895 #define MX6Q_PAD_EIM_D18__ECSPI1_MOSI \
3896 (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
3897 #define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \
3898 (_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
3899 #define MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \
3900 (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
3901 #define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \
3902 (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
3903 #define MX6Q_PAD_EIM_D18__GPIO_3_18 \
3904 (_MX6Q_PAD_EIM_D18__GPIO_3_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
3905 #define MX6Q_PAD_EIM_D18__I2C3_SDA \
3906 (_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
3907 #define MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \
3908 (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3910 #define MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \
3911 (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
3912 #define MX6Q_PAD_EIM_D19__ECSPI1_SS1 \
3913 (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3914 #define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \
3915 (_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
3916 #define MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \
3917 (_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
3918 #define MX6Q_PAD_EIM_D19__UART1_CTS \
3919 (_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3920 #define MX6Q_PAD_EIM_D19__GPIO_3_19 \
3921 (_MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
3922 #define MX6Q_PAD_EIM_D19__EPIT1_EPITO \
3923 (_MX6Q_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
3924 #define MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \
3925 (_MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP | MUX_PAD_CTRL(NO_PAD_CTRL))
3927 #define MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \
3928 (_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
3929 #define MX6Q_PAD_EIM_D20__ECSPI4_SS0 \
3930 (_MX6Q_PAD_EIM_D20__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
3931 #define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \
3932 (_MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
3933 #define MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \
3934 (_MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
3935 #define MX6Q_PAD_EIM_D20__UART1_CTS \
3936 (_MX6Q_PAD_EIM_D20__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3937 #define MX6Q_PAD_EIM_D20__UART1_RTS \
3938 (_MX6Q_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3939 #define MX6Q_PAD_EIM_D20__GPIO_3_20 \
3940 (_MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
3941 #define MX6Q_PAD_EIM_D20__EPIT2_EPITO \
3942 (_MX6Q_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
3944 #define MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \
3945 (_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
3946 #define MX6Q_PAD_EIM_D21__ECSPI4_SCLK \
3947 (_MX6Q_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
3948 #define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \
3949 (_MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
3950 #define MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \
3951 (_MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
3952 #define MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \
3953 (_MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
3954 #define MX6Q_PAD_EIM_D21__GPIO_3_21 \
3955 (_MX6Q_PAD_EIM_D21__GPIO_3_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
3956 #define MX6Q_PAD_EIM_D21__I2C1_SCL \
3957 (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
3958 #define MX6Q_PAD_EIM_D21__SPDIF_IN1 \
3959 (_MX6Q_PAD_EIM_D21__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3961 #define MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \
3962 (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
3963 #define MX6Q_PAD_EIM_D22__ECSPI4_MISO \
3964 (_MX6Q_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
3965 #define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \
3966 (_MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3967 #define MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \
3968 (_MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
3969 #define MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \
3970 (_MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
3971 #define MX6Q_PAD_EIM_D22__GPIO_3_22 \
3972 (_MX6Q_PAD_EIM_D22__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
3973 #define MX6Q_PAD_EIM_D22__SPDIF_OUT1 \
3974 (_MX6Q_PAD_EIM_D22__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
3975 #define MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \
3976 (_MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
3978 #define MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \
3979 (_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
3980 #define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \
3981 (_MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
3982 #define MX6Q_PAD_EIM_D23__UART3_CTS \
3983 (_MX6Q_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3984 #define MX6Q_PAD_EIM_D23__UART1_DCD \
3985 (_MX6Q_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3986 #define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \
3987 (_MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
3988 #define MX6Q_PAD_EIM_D23__GPIO_3_23 \
3989 (_MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
3990 #define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \
3991 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
3992 #define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \
3993 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
3995 #define MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \
3996 (_MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
3997 #define MX6Q_PAD_EIM_EB3__ECSPI4_RDY \
3998 (_MX6Q_PAD_EIM_EB3__ECSPI4_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
3999 #define MX6Q_PAD_EIM_EB3__UART3_CTS \
4000 (_MX6Q_PAD_EIM_EB3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4001 #define MX6Q_PAD_EIM_EB3__UART3_RTS \
4002 (_MX6Q_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4003 #define MX6Q_PAD_EIM_EB3__UART1_RI \
4004 (_MX6Q_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4005 #define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \
4006 (_MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
4007 #define MX6Q_PAD_EIM_EB3__GPIO_2_31 \
4008 (_MX6Q_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4009 #define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \
4010 (_MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4011 #define MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \
4012 (_MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4014 #define MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \
4015 (_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4016 #define MX6Q_PAD_EIM_D24__ECSPI4_SS2 \
4017 (_MX6Q_PAD_EIM_D24__ECSPI4_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4018 #define MX6Q_PAD_EIM_D24__UART3_TXD \
4019 (_MX6Q_PAD_EIM_D24__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4020 #define MX6Q_PAD_EIM_D24__UART3_RXD \
4021 (_MX6Q_PAD_EIM_D24__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4022 #define MX6Q_PAD_EIM_D24__ECSPI1_SS2 \
4023 (_MX6Q_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4024 #define MX6Q_PAD_EIM_D24__ECSPI2_SS2 \
4025 (_MX6Q_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4026 #define MX6Q_PAD_EIM_D24__GPIO_3_24 \
4027 (_MX6Q_PAD_EIM_D24__GPIO_3_24 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
4028 #define MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \
4029 (_MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
4030 #define MX6Q_PAD_EIM_D24__UART1_DTR \
4031 (_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4033 #define MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \
4034 (_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4035 #define MX6Q_PAD_EIM_D25__ECSPI4_SS3 \
4036 (_MX6Q_PAD_EIM_D25__ECSPI4_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4037 #define MX6Q_PAD_EIM_D25__UART3_TXD \
4038 (_MX6Q_PAD_EIM_D25__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4039 #define MX6Q_PAD_EIM_D25__UART3_RXD \
4040 (_MX6Q_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4041 #define MX6Q_PAD_EIM_D25__ECSPI1_SS3 \
4042 (_MX6Q_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4043 #define MX6Q_PAD_EIM_D25__ECSPI2_SS3 \
4044 (_MX6Q_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4045 #define MX6Q_PAD_EIM_D25__GPIO_3_25 \
4046 (_MX6Q_PAD_EIM_D25__GPIO_3_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4047 #define MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \
4048 (_MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
4049 #define MX6Q_PAD_EIM_D25__UART1_DSR \
4050 (_MX6Q_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4052 #define MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \
4053 (_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4054 #define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \
4055 (_MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4056 #define MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \
4057 (_MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4058 #define MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \
4059 (_MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4060 #define MX6Q_PAD_EIM_D26__UART2_TXD \
4061 (_MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4062 #define MX6Q_PAD_EIM_D26__UART2_RXD \
4063 (_MX6Q_PAD_EIM_D26__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4064 #define MX6Q_PAD_EIM_D26__GPIO_3_26 \
4065 (_MX6Q_PAD_EIM_D26__GPIO_3_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4066 #define MX6Q_PAD_EIM_D26__IPU1_SISG_2 \
4067 (_MX6Q_PAD_EIM_D26__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4068 #define MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \
4069 (_MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4071 #define MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \
4072 (_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4073 #define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \
4074 (_MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4075 #define MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \
4076 (_MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4077 #define MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \
4078 (_MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4079 #define MX6Q_PAD_EIM_D27__UART2_TXD \
4080 (_MX6Q_PAD_EIM_D27__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4081 #define MX6Q_PAD_EIM_D27__UART2_RXD \
4082 (_MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4083 #define MX6Q_PAD_EIM_D27__GPIO_3_27 \
4084 (_MX6Q_PAD_EIM_D27__GPIO_3_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4085 #define MX6Q_PAD_EIM_D27__IPU1_SISG_3 \
4086 (_MX6Q_PAD_EIM_D27__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4087 #define MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \
4088 (_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4090 #define MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \
4091 (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4092 #define MX6Q_PAD_EIM_D28__I2C1_SDA \
4093 (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
4094 #define MX6Q_PAD_EIM_D28__ECSPI4_MOSI \
4095 (_MX6Q_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
4096 #define MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \
4097 (_MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4098 #define MX6Q_PAD_EIM_D28__UART2_CTS \
4099 (_MX6Q_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4100 #define MX6Q_PAD_EIM_D28__GPIO_3_28 \
4101 (_MX6Q_PAD_EIM_D28__GPIO_3_28 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
4102 #define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \
4103 (_MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
4104 #define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \
4105 (_MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4107 #define MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \
4108 (_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4109 #define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \
4110 (_MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4111 #define MX6Q_PAD_EIM_D29__ECSPI4_SS0 \
4112 (_MX6Q_PAD_EIM_D29__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4113 #define MX6Q_PAD_EIM_D29__UART2_CTS \
4114 (_MX6Q_PAD_EIM_D29__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4115 #define MX6Q_PAD_EIM_D29__UART2_RTS \
4116 (_MX6Q_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4117 #define MX6Q_PAD_EIM_D29__GPIO_3_29 \
4118 (_MX6Q_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4119 #define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \
4120 (_MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
4121 #define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \
4122 (_MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4124 #define MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \
4125 (_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
4126 #define MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
4127 (_MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4128 #define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \
4129 (_MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4130 #define MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \
4131 (_MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4132 #define MX6Q_PAD_EIM_D30__UART3_CTS \
4133 (_MX6Q_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4134 #define MX6Q_PAD_EIM_D30__GPIO_3_30 \
4135 (_MX6Q_PAD_EIM_D30__GPIO_3_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
4136 #define MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \
4137 (_MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
4138 #define MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \
4139 (_MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4141 #define MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \
4142 (_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4143 #define MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
4144 (_MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4145 #define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \
4146 (_MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4147 #define MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \
4148 (_MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4149 #define MX6Q_PAD_EIM_D31__UART3_CTS \
4150 (_MX6Q_PAD_EIM_D31__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4151 #define MX6Q_PAD_EIM_D31__UART3_RTS \
4152 (_MX6Q_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4153 #define MX6Q_PAD_EIM_D31__GPIO_3_31 \
4154 (_MX6Q_PAD_EIM_D31__GPIO_3_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4155 #define MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \
4156 (_MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
4157 #define MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \
4158 (_MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4160 #define MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \
4161 (_MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4162 #define MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \
4163 (_MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4164 #define MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \
4165 (_MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4166 #define MX6Q_PAD_EIM_A24__IPU2_SISG_2 \
4167 (_MX6Q_PAD_EIM_A24__IPU2_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4168 #define MX6Q_PAD_EIM_A24__IPU1_SISG_2 \
4169 (_MX6Q_PAD_EIM_A24__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4170 #define MX6Q_PAD_EIM_A24__GPIO_5_4 \
4171 (_MX6Q_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4172 #define MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \
4173 (_MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4174 #define MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \
4175 (_MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4177 #define MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \
4178 (_MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4179 #define MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \
4180 (_MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4181 #define MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \
4182 (_MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4183 #define MX6Q_PAD_EIM_A23__IPU2_SISG_3 \
4184 (_MX6Q_PAD_EIM_A23__IPU2_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4185 #define MX6Q_PAD_EIM_A23__IPU1_SISG_3 \
4186 (_MX6Q_PAD_EIM_A23__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4187 #define MX6Q_PAD_EIM_A23__GPIO_6_6 \
4188 (_MX6Q_PAD_EIM_A23__GPIO_6_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4189 #define MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \
4190 (_MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4191 #define MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \
4192 (_MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4194 #define MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \
4195 (_MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4196 #define MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \
4197 (_MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4198 #define MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \
4199 (_MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4200 #define MX6Q_PAD_EIM_A22__GPIO_2_16 \
4201 (_MX6Q_PAD_EIM_A22__GPIO_2_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4202 #define MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \
4203 (_MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4204 #define MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \
4205 (_MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4207 #define MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \
4208 (_MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4209 #define MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \
4210 (_MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4211 #define MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \
4212 (_MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4213 #define MX6Q_PAD_EIM_A21__RESERVED_RESERVED \
4214 (_MX6Q_PAD_EIM_A21__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4215 #define MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \
4216 (_MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4217 #define MX6Q_PAD_EIM_A21__GPIO_2_17 \
4218 (_MX6Q_PAD_EIM_A21__GPIO_2_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4219 #define MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \
4220 (_MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4221 #define MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \
4222 (_MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4224 #define MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \
4225 (_MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4226 #define MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \
4227 (_MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4228 #define MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \
4229 (_MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4230 #define MX6Q_PAD_EIM_A20__RESERVED_RESERVED \
4231 (_MX6Q_PAD_EIM_A20__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4232 #define MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \
4233 (_MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4234 #define MX6Q_PAD_EIM_A20__GPIO_2_18 \
4235 (_MX6Q_PAD_EIM_A20__GPIO_2_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4236 #define MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \
4237 (_MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4238 #define MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \
4239 (_MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4241 #define MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \
4242 (_MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4243 #define MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \
4244 (_MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4245 #define MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \
4246 (_MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4247 #define MX6Q_PAD_EIM_A19__RESERVED_RESERVED \
4248 (_MX6Q_PAD_EIM_A19__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4249 #define MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \
4250 (_MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4251 #define MX6Q_PAD_EIM_A19__GPIO_2_19 \
4252 (_MX6Q_PAD_EIM_A19__GPIO_2_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4253 #define MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \
4254 (_MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4255 #define MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \
4256 (_MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4258 #define MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \
4259 (_MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4260 #define MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \
4261 (_MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4262 #define MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \
4263 (_MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4264 #define MX6Q_PAD_EIM_A18__RESERVED_RESERVED \
4265 (_MX6Q_PAD_EIM_A18__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4266 #define MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \
4267 (_MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4268 #define MX6Q_PAD_EIM_A18__GPIO_2_20 \
4269 (_MX6Q_PAD_EIM_A18__GPIO_2_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4270 #define MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \
4271 (_MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4272 #define MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \
4273 (_MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4275 #define MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \
4276 (_MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4277 #define MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \
4278 (_MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4279 #define MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \
4280 (_MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4281 #define MX6Q_PAD_EIM_A17__RESERVED_RESERVED \
4282 (_MX6Q_PAD_EIM_A17__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4283 #define MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \
4284 (_MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4285 #define MX6Q_PAD_EIM_A17__GPIO_2_21 \
4286 (_MX6Q_PAD_EIM_A17__GPIO_2_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4287 #define MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \
4288 (_MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4289 #define MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \
4290 (_MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4292 #define MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \
4293 (_MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4294 #define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \
4295 (_MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4296 #define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \
4297 (_MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4298 #define MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \
4299 (_MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4300 #define MX6Q_PAD_EIM_A16__GPIO_2_22 \
4301 (_MX6Q_PAD_EIM_A16__GPIO_2_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4302 #define MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \
4303 (_MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4304 #define MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \
4305 (_MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4307 #define MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \
4308 (_MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4309 #define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \
4310 (_MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4311 #define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \
4312 (_MX6Q_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4313 #define MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \
4314 (_MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4315 #define MX6Q_PAD_EIM_CS0__GPIO_2_23 \
4316 (_MX6Q_PAD_EIM_CS0__GPIO_2_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4317 #define MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \
4318 (_MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4320 #define MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \
4321 (_MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4322 #define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \
4323 (_MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4324 #define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \
4325 (_MX6Q_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
4326 #define MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \
4327 (_MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4328 #define MX6Q_PAD_EIM_CS1__GPIO_2_24 \
4329 (_MX6Q_PAD_EIM_CS1__GPIO_2_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4330 #define MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \
4331 (_MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4333 #define MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \
4334 (_MX6Q_PAD_EIM_OE__WEIM_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
4335 #define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \
4336 (_MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4337 #define MX6Q_PAD_EIM_OE__ECSPI2_MISO \
4338 (_MX6Q_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
4339 #define MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \
4340 (_MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4341 #define MX6Q_PAD_EIM_OE__GPIO_2_25 \
4342 (_MX6Q_PAD_EIM_OE__GPIO_2_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4343 #define MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \
4344 (_MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4346 #define MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \
4347 (_MX6Q_PAD_EIM_RW__WEIM_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL))
4348 #define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \
4349 (_MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4350 #define MX6Q_PAD_EIM_RW__ECSPI2_SS0 \
4351 (_MX6Q_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4352 #define MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \
4353 (_MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4354 #define MX6Q_PAD_EIM_RW__GPIO_2_26 \
4355 (_MX6Q_PAD_EIM_RW__GPIO_2_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4356 #define MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \
4357 (_MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4358 #define MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \
4359 (_MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4361 #define MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \
4362 (_MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
4363 #define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \
4364 (_MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4365 #define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \
4366 (_MX6Q_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4367 #define MX6Q_PAD_EIM_LBA__GPIO_2_27 \
4368 (_MX6Q_PAD_EIM_LBA__GPIO_2_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4369 #define MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \
4370 (_MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4371 #define MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \
4372 (_MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4374 #define MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \
4375 (_MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4376 #define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \
4377 (_MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4378 #define MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \
4379 (_MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4380 #define MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \
4381 (_MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4382 #define MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \
4383 (_MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
4384 #define MX6Q_PAD_EIM_EB0__GPIO_2_28 \
4385 (_MX6Q_PAD_EIM_EB0__GPIO_2_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4386 #define MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \
4387 (_MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4388 #define MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \
4389 (_MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4391 #define MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \
4392 (_MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4393 #define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \
4394 (_MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4395 #define MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \
4396 (_MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4397 #define MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \
4398 (_MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4399 #define MX6Q_PAD_EIM_EB1__GPIO_2_29 \
4400 (_MX6Q_PAD_EIM_EB1__GPIO_2_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4401 #define MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \
4402 (_MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4403 #define MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \
4404 (_MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4406 #define MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \
4407 (_MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4408 #define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \
4409 (_MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4410 #define MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \
4411 (_MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4412 #define MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \
4413 (_MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4414 #define MX6Q_PAD_EIM_DA0__GPIO_3_0 \
4415 (_MX6Q_PAD_EIM_DA0__GPIO_3_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4416 #define MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \
4417 (_MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4418 #define MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \
4419 (_MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4421 #define MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \
4422 (_MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4423 #define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \
4424 (_MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4425 #define MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \
4426 (_MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4427 #define MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \
4428 (_MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4429 #define MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \
4430 (_MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
4431 #define MX6Q_PAD_EIM_DA1__GPIO_3_1 \
4432 (_MX6Q_PAD_EIM_DA1__GPIO_3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4433 #define MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \
4434 (_MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4435 #define MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \
4436 (_MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4438 #define MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \
4439 (_MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4440 #define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \
4441 (_MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4442 #define MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \
4443 (_MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4444 #define MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \
4445 (_MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4446 #define MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \
4447 (_MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
4448 #define MX6Q_PAD_EIM_DA2__GPIO_3_2 \
4449 (_MX6Q_PAD_EIM_DA2__GPIO_3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4450 #define MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \
4451 (_MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4452 #define MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \
4453 (_MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4455 #define MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \
4456 (_MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4457 #define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \
4458 (_MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4459 #define MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \
4460 (_MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4461 #define MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \
4462 (_MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4463 #define MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \
4464 (_MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ | MUX_PAD_CTRL(NO_PAD_CTRL))
4465 #define MX6Q_PAD_EIM_DA3__GPIO_3_3 \
4466 (_MX6Q_PAD_EIM_DA3__GPIO_3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4467 #define MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \
4468 (_MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4469 #define MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \
4470 (_MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4472 #define MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \
4473 (_MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4474 #define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \
4475 (_MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4476 #define MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \
4477 (_MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4478 #define MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \
4479 (_MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4480 #define MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \
4481 (_MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
4482 #define MX6Q_PAD_EIM_DA4__GPIO_3_4 \
4483 (_MX6Q_PAD_EIM_DA4__GPIO_3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4484 #define MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \
4485 (_MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4486 #define MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \
4487 (_MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4489 #define MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \
4490 (_MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4491 #define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \
4492 (_MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4493 #define MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \
4494 (_MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4495 #define MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \
4496 (_MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4497 #define MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \
4498 (_MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
4499 #define MX6Q_PAD_EIM_DA5__GPIO_3_5 \
4500 (_MX6Q_PAD_EIM_DA5__GPIO_3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4501 #define MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \
4502 (_MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4503 #define MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \
4504 (_MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4506 #define MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \
4507 (_MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4508 #define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \
4509 (_MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4510 #define MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \
4511 (_MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4512 #define MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \
4513 (_MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4514 #define MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \
4515 (_MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN | MUX_PAD_CTRL(NO_PAD_CTRL))
4516 #define MX6Q_PAD_EIM_DA6__GPIO_3_6 \
4517 (_MX6Q_PAD_EIM_DA6__GPIO_3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4518 #define MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \
4519 (_MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4520 #define MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \
4521 (_MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4523 #define MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \
4524 (_MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4525 #define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \
4526 (_MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4527 #define MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \
4528 (_MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4529 #define MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \
4530 (_MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4531 #define MX6Q_PAD_EIM_DA7__GPIO_3_7 \
4532 (_MX6Q_PAD_EIM_DA7__GPIO_3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4533 #define MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \
4534 (_MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4535 #define MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \
4536 (_MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4538 #define MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \
4539 (_MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4540 #define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \
4541 (_MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4542 #define MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \
4543 (_MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4544 #define MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \
4545 (_MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4546 #define MX6Q_PAD_EIM_DA8__GPIO_3_8 \
4547 (_MX6Q_PAD_EIM_DA8__GPIO_3_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4548 #define MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \
4549 (_MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4550 #define MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \
4551 (_MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4553 #define MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \
4554 (_MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4555 #define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \
4556 (_MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4557 #define MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \
4558 (_MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4559 #define MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \
4560 (_MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4561 #define MX6Q_PAD_EIM_DA9__GPIO_3_9 \
4562 (_MX6Q_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4563 #define MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \
4564 (_MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4565 #define MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \
4566 (_MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4568 #define MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \
4569 (_MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4570 #define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \
4571 (_MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4572 #define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \
4573 (_MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
4574 #define MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \
4575 (_MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4576 #define MX6Q_PAD_EIM_DA10__GPIO_3_10 \
4577 (_MX6Q_PAD_EIM_DA10__GPIO_3_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4578 #define MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \
4579 (_MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4580 #define MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \
4581 (_MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4583 #define MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \
4584 (_MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4585 #define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \
4586 (_MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4587 #define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \
4588 (_MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
4589 #define MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \
4590 (_MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4591 #define MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \
4592 (_MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4593 #define MX6Q_PAD_EIM_DA11__GPIO_3_11 \
4594 (_MX6Q_PAD_EIM_DA11__GPIO_3_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4595 #define MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \
4596 (_MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4597 #define MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \
4598 (_MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4600 #define MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \
4601 (_MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4602 #define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \
4603 (_MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4604 #define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \
4605 (_MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
4606 #define MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \
4607 (_MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4608 #define MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \
4609 (_MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4610 #define MX6Q_PAD_EIM_DA12__GPIO_3_12 \
4611 (_MX6Q_PAD_EIM_DA12__GPIO_3_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4612 #define MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \
4613 (_MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4614 #define MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \
4615 (_MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4617 #define MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \
4618 (_MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4619 #define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \
4620 (_MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
4621 #define MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \
4622 (_MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4623 #define MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \
4624 (_MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4625 #define MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \
4626 (_MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4627 #define MX6Q_PAD_EIM_DA13__GPIO_3_13 \
4628 (_MX6Q_PAD_EIM_DA13__GPIO_3_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4629 #define MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \
4630 (_MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4631 #define MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \
4632 (_MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4634 #define MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \
4635 (_MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4636 #define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \
4637 (_MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
4638 #define MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \
4639 (_MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4640 #define MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \
4641 (_MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4642 #define MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \
4643 (_MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4644 #define MX6Q_PAD_EIM_DA14__GPIO_3_14 \
4645 (_MX6Q_PAD_EIM_DA14__GPIO_3_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4646 #define MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \
4647 (_MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4648 #define MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \
4649 (_MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4651 #define MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \
4652 (_MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4653 #define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \
4654 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4655 #define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \
4656 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4657 #define MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \
4658 (_MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4659 #define MX6Q_PAD_EIM_DA15__GPIO_3_15 \
4660 (_MX6Q_PAD_EIM_DA15__GPIO_3_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4661 #define MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \
4662 (_MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4663 #define MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \
4664 (_MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4666 #define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \
4667 (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
4668 #define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \
4669 (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL))
4670 #define MX6Q_PAD_EIM_WAIT__GPIO_5_0 \
4671 (_MX6Q_PAD_EIM_WAIT__GPIO_5_0 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
4672 #define MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \
4673 (_MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
4674 #define MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \
4675 (_MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4677 #define MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \
4678 (_MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4679 #define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \
4680 (_MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4681 #define MX6Q_PAD_EIM_BCLK__GPIO_6_31 \
4682 (_MX6Q_PAD_EIM_BCLK__GPIO_6_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4683 #define MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \
4684 (_MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4686 #define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \
4687 (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4688 #define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \
4689 (_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4690 #define MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \
4691 (_MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4692 #define MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \
4693 (_MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4694 #define MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \
4695 (_MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4696 #define MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \
4697 (_MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4699 #define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \
4700 (_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4701 #define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \
4702 (_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4703 #define MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \
4704 (_MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
4705 #define MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \
4706 (_MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4707 #define MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \
4708 (_MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4709 #define MX6Q_PAD_DI0_PIN15__GPIO_4_17 \
4710 (_MX6Q_PAD_DI0_PIN15__GPIO_4_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4711 #define MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \
4712 (_MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4714 #define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \
4715 (_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4716 #define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \
4717 (_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4718 #define MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \
4719 (_MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
4720 #define MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \
4721 (_MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
4722 #define MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \
4723 (_MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4724 #define MX6Q_PAD_DI0_PIN2__GPIO_4_18 \
4725 (_MX6Q_PAD_DI0_PIN2__GPIO_4_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4726 #define MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \
4727 (_MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4728 #define MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \
4729 (_MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4731 #define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \
4732 (_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4733 #define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \
4734 (_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4735 #define MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \
4736 (_MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
4737 #define MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \
4738 (_MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4739 #define MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \
4740 (_MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4741 #define MX6Q_PAD_DI0_PIN3__GPIO_4_19 \
4742 (_MX6Q_PAD_DI0_PIN3__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4743 #define MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \
4744 (_MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4745 #define MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \
4746 (_MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4748 #define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \
4749 (_MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4750 #define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \
4751 (_MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4752 #define MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \
4753 (_MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
4754 #define MX6Q_PAD_DI0_PIN4__USDHC1_WP \
4755 (_MX6Q_PAD_DI0_PIN4__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4756 #define MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \
4757 (_MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL))
4758 #define MX6Q_PAD_DI0_PIN4__GPIO_4_20 \
4759 (_MX6Q_PAD_DI0_PIN4__GPIO_4_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4760 #define MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \
4761 (_MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4762 #define MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \
4763 (_MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4765 #define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \
4766 (_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4767 #define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \
4768 (_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4769 #define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \
4770 (_MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
4771 #define MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \
4772 (_MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4773 #define MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \
4774 (_MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL))
4775 #define MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \
4776 (_MX6Q_PAD_DISP0_DAT0__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4777 #define MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \
4778 (_MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4780 #define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \
4781 (_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4782 #define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \
4783 (_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4784 #define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \
4785 (_MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
4786 #define MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \
4787 (_MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4788 #define MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
4789 (_MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
4790 #define MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \
4791 (_MX6Q_PAD_DISP0_DAT1__GPIO_4_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4792 #define MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \
4793 (_MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4794 #define MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \
4795 (_MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4797 #define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \
4798 (_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4799 #define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \
4800 (_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4801 #define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \
4802 (_MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
4803 #define MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \
4804 (_MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4805 #define MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \
4806 (_MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
4807 #define MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \
4808 (_MX6Q_PAD_DISP0_DAT2__GPIO_4_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4809 #define MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \
4810 (_MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4811 #define MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \
4812 (_MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4814 #define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \
4815 (_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4816 #define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \
4817 (_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4818 #define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \
4819 (_MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4820 #define MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \
4821 (_MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4822 #define MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \
4823 (_MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
4824 #define MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \
4825 (_MX6Q_PAD_DISP0_DAT3__GPIO_4_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4826 #define MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \
4827 (_MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
4828 #define MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \
4829 (_MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4831 #define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \
4832 (_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4833 #define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \
4834 (_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4835 #define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \
4836 (_MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4837 #define MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \
4838 (_MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4839 #define MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \
4840 (_MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL))
4841 #define MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \
4842 (_MX6Q_PAD_DISP0_DAT4__GPIO_4_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
4843 #define MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \
4844 (_MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
4845 #define MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \
4846 (_MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4848 #define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \
4849 (_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4850 #define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \
4851 (_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4852 #define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \
4853 (_MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4854 #define MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \
4855 (_MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
4856 #define MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \
4857 (_MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL))
4858 #define MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \
4859 (_MX6Q_PAD_DISP0_DAT5__GPIO_4_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
4860 #define MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \
4861 (_MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
4862 #define MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \
4863 (_MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4865 #define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \
4866 (_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4867 #define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \
4868 (_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4869 #define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \
4870 (_MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4871 #define MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \
4872 (_MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
4873 #define MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \
4874 (_MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
4875 #define MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \
4876 (_MX6Q_PAD_DISP0_DAT6__GPIO_4_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
4877 #define MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \
4878 (_MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
4879 #define MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \
4880 (_MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4882 #define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \
4883 (_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4884 #define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \
4885 (_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4886 #define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \
4887 (_MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
4888 #define MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \
4889 (_MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4890 #define MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \
4891 (_MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4892 #define MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \
4893 (_MX6Q_PAD_DISP0_DAT7__GPIO_4_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
4894 #define MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \
4895 (_MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
4896 #define MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \
4897 (_MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4899 #define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \
4900 (_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4901 #define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \
4902 (_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4903 #define MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \
4904 (_MX6Q_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
4905 #define MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \
4906 (_MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
4907 #define MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \
4908 (_MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
4909 #define MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \
4910 (_MX6Q_PAD_DISP0_DAT8__GPIO_4_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
4911 #define MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \
4912 (_MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
4913 #define MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \
4914 (_MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
4916 #define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \
4917 (_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4918 #define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \
4919 (_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4920 #define MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \
4921 (_MX6Q_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
4922 #define MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \
4923 (_MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
4924 #define MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \
4925 (_MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
4926 #define MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \
4927 (_MX6Q_PAD_DISP0_DAT9__GPIO_4_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
4928 #define MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \
4929 (_MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
4930 #define MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \
4931 (_MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
4933 #define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \
4934 (_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4935 #define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \
4936 (_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4937 #define MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \
4938 (_MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4939 #define MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
4940 (_MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
4941 #define MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \
4942 (_MX6Q_PAD_DISP0_DAT10__GPIO_4_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
4943 #define MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \
4944 (_MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
4945 #define MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \
4946 (_MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
4948 #define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \
4949 (_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4950 #define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \
4951 (_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4952 #define MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \
4953 (_MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4954 #define MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
4955 (_MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
4956 #define MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \
4957 (_MX6Q_PAD_DISP0_DAT11__GPIO_5_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4958 #define MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \
4959 (_MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
4960 #define MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \
4961 (_MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
4963 #define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \
4964 (_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4965 #define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \
4966 (_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4967 #define MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED \
4968 (_MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
4969 #define MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
4970 (_MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
4971 #define MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \
4972 (_MX6Q_PAD_DISP0_DAT12__GPIO_5_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
4973 #define MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \
4974 (_MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
4975 #define MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \
4976 (_MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
4978 #define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \
4979 (_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4980 #define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \
4981 (_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4982 #define MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \
4983 (_MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
4984 #define MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
4985 (_MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
4986 #define MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \
4987 (_MX6Q_PAD_DISP0_DAT13__GPIO_5_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
4988 #define MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \
4989 (_MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
4990 #define MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \
4991 (_MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
4993 #define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \
4994 (_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4995 #define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \
4996 (_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
4997 #define MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \
4998 (_MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
4999 #define MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
5000 (_MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5001 #define MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \
5002 (_MX6Q_PAD_DISP0_DAT14__GPIO_5_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5003 #define MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \
5004 (_MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
5006 #define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \
5007 (_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5008 #define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \
5009 (_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5010 #define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \
5011 (_MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5012 #define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \
5013 (_MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5014 #define MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
5015 (_MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5016 #define MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \
5017 (_MX6Q_PAD_DISP0_DAT15__GPIO_5_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
5018 #define MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \
5019 (_MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
5020 #define MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \
5021 (_MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
5023 #define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \
5024 (_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5025 #define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \
5026 (_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5027 #define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \
5028 (_MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
5029 #define MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \
5030 (_MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
5031 #define MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \
5032 (_MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5033 #define MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \
5034 (_MX6Q_PAD_DISP0_DAT16__GPIO_5_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
5035 #define MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \
5036 (_MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
5037 #define MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \
5038 (_MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
5040 #define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \
5041 (_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5042 #define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \
5043 (_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5044 #define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \
5045 (_MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
5046 #define MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \
5047 (_MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5048 #define MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \
5049 (_MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5050 #define MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \
5051 (_MX6Q_PAD_DISP0_DAT17__GPIO_5_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
5052 #define MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \
5053 (_MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
5054 #define MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \
5055 (_MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
5057 #define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \
5058 (_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5059 #define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \
5060 (_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5061 #define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \
5062 (_MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5063 #define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \
5064 (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
5065 #define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \
5066 (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
5067 #define MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \
5068 (_MX6Q_PAD_DISP0_DAT18__GPIO_5_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
5069 #define MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \
5070 (_MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
5071 #define MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \
5072 (_MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5074 #define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \
5075 (_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5076 #define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \
5077 (_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5078 #define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \
5079 (_MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5080 #define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \
5081 (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5082 #define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \
5083 (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
5084 #define MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \
5085 (_MX6Q_PAD_DISP0_DAT19__GPIO_5_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
5086 #define MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \
5087 (_MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
5088 #define MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \
5089 (_MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5091 #define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \
5092 (_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5093 #define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \
5094 (_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5095 #define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \
5096 (_MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5097 #define MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \
5098 (_MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
5099 #define MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
5100 (_MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5101 #define MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \
5102 (_MX6Q_PAD_DISP0_DAT20__GPIO_5_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
5103 #define MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \
5104 (_MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
5105 #define MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \
5106 (_MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
5108 #define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \
5109 (_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5110 #define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \
5111 (_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5112 #define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \
5113 (_MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
5114 #define MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \
5115 (_MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5116 #define MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \
5117 (_MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5118 #define MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \
5119 (_MX6Q_PAD_DISP0_DAT21__GPIO_5_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
5120 #define MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \
5121 (_MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
5122 #define MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \
5123 (_MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
5125 #define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \
5126 (_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5127 #define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \
5128 (_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5129 #define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \
5130 (_MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
5131 #define MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \
5132 (_MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
5133 #define MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \
5134 (_MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5135 #define MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \
5136 (_MX6Q_PAD_DISP0_DAT22__GPIO_5_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
5137 #define MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \
5138 (_MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
5139 #define MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \
5140 (_MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
5142 #define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \
5143 (_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5144 #define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \
5145 (_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
5146 #define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \
5147 (_MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5148 #define MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \
5149 (_MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5150 #define MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \
5151 (_MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5152 #define MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \
5153 (_MX6Q_PAD_DISP0_DAT23__GPIO_5_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
5154 #define MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \
5155 (_MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
5156 #define MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \
5157 (_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
5159 #define MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED \
5160 (_MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5161 #define MX6Q_PAD_ENET_MDIO__ENET_MDIO \
5162 (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
5163 #define MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \
5164 (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
5165 #define MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \
5166 (_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5167 #define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \
5168 (_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5169 #define MX6Q_PAD_ENET_MDIO__GPIO_1_22 \
5170 (_MX6Q_PAD_ENET_MDIO__GPIO_1_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
5171 #define MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \
5172 (_MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
5174 #define MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED \
5175 (_MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5176 #define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \
5177 (_MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
5178 #define MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \
5179 (_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
5180 #define MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \
5181 (_MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5182 #define MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \
5183 (_MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
5184 #define MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \
5185 (_MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5186 #define MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \
5187 (_MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))
5189 #define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \
5190 (_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
5191 #define MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \
5192 (_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
5193 #define MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \
5194 (_MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5195 #define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \
5196 (_MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5197 #define MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \
5198 (_MX6Q_PAD_ENET_RX_ER__GPIO_1_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
5199 #define MX6Q_PAD_ENET_RX_ER__PHY_TDI \
5200 (_MX6Q_PAD_ENET_RX_ER__PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
5201 #define MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \
5202 (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5204 #define MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED \
5205 (_MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5206 #define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \
5207 (_MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
5208 #define MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \
5209 (_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
5210 #define MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \
5211 (_MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5212 #define MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \
5213 (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
5214 #define MX6Q_PAD_ENET_CRS_DV__PHY_TDO \
5215 (_MX6Q_PAD_ENET_CRS_DV__PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
5216 #define MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \
5217 (_MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5219 #define MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \
5220 (_MX6Q_PAD_ENET_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
5221 #define MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \
5222 (_MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5223 #define MX6Q_PAD_ENET_RXD1__ESAI1_FST \
5224 (_MX6Q_PAD_ENET_RXD1__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
5225 #define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \
5226 (_MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5227 #define MX6Q_PAD_ENET_RXD1__GPIO_1_26 \
5228 (_MX6Q_PAD_ENET_RXD1__GPIO_1_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
5229 #define MX6Q_PAD_ENET_RXD1__PHY_TCK \
5230 (_MX6Q_PAD_ENET_RXD1__PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
5231 #define MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \
5232 (_MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))
5234 #define MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \
5235 (_MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5236 #define MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \
5237 (_MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5238 #define MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \
5239 (_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
5240 #define MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \
5241 (_MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5242 #define MX6Q_PAD_ENET_RXD0__GPIO_1_27 \
5243 (_MX6Q_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
5244 #define MX6Q_PAD_ENET_RXD0__PHY_TMS \
5245 (_MX6Q_PAD_ENET_RXD0__PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
5246 #define MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \
5247 (_MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))
5249 #define MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED \
5250 (_MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5251 #define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \
5252 (_MX6Q_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
5253 #define MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \
5254 (_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5255 #define MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \
5256 (_MX6Q_PAD_ENET_TX_EN__GPIO_1_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
5257 #define MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \
5258 (_MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
5259 #define MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \
5260 (_MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))
5262 #define MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \
5263 (_MX6Q_PAD_ENET_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5264 #define MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \
5265 (_MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5266 #define MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \
5267 (_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5268 #define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \
5269 (_MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
5270 #define MX6Q_PAD_ENET_TXD1__GPIO_1_29 \
5271 (_MX6Q_PAD_ENET_TXD1__GPIO_1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
5272 #define MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \
5273 (_MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
5274 #define MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \
5275 (_MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5277 #define MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED \
5278 (_MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
5279 #define MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \
5280 (_MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5281 #define MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \
5282 (_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5283 #define MX6Q_PAD_ENET_TXD0__GPIO_1_30 \
5284 (_MX6Q_PAD_ENET_TXD0__GPIO_1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
5285 #define MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \
5286 (_MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
5287 #define MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \
5288 (_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5290 #define MX6Q_PAD_ENET_MDC__MLB_MLBDAT \
5291 (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
5292 #define MX6Q_PAD_ENET_MDC__ENET_MDC \
5293 (_MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
5294 #define MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \
5295 (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5296 #define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \
5297 (_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
5298 #define MX6Q_PAD_ENET_MDC__GPIO_1_31 \
5299 (_MX6Q_PAD_ENET_MDC__GPIO_1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
5300 #define MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \
5301 (_MX6Q_PAD_ENET_MDC__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
5302 #define MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \
5303 (_MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))
5305 #define MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \
5306 (_MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
5308 #define MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \
5309 (_MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
5311 #define MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \
5312 (_MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
5314 #define MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \
5315 (_MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
5317 #define MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \
5318 (_MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
5320 #define MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \
5321 (_MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
5323 #define MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \
5324 (_MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
5326 #define MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \
5327 (_MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
5329 #define MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \
5330 (_MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5332 #define MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \
5333 (_MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5335 #define MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \
5336 (_MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
5338 #define MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \
5339 (_MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
5341 #define MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \
5342 (_MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
5344 #define MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \
5345 (_MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
5347 #define MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \
5348 (_MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
5350 #define MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \
5351 (_MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
5353 #define MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \
5354 (_MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
5356 #define MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \
5357 (_MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
5359 #define MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \
5360 (_MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5362 #define MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \
5363 (_MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5365 #define MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \
5366 (_MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
5368 #define MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \
5369 (_MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
5371 #define MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \
5372 (_MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
5374 #define MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \
5375 (_MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
5377 #define MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \
5378 (_MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
5380 #define MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \
5381 (_MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
5383 #define MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \
5384 (_MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5386 #define MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \
5387 (_MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
5389 #define MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \
5390 (_MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
5392 #define MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \
5393 (_MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5395 #define MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \
5396 (_MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
5398 #define MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \
5399 (_MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
5401 #define MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \
5402 (_MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
5404 #define MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \
5405 (_MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
5407 #define MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \
5408 (_MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
5410 #define MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \
5411 (_MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
5413 #define MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \
5414 (_MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
5416 #define MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \
5417 (_MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5419 #define MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \
5420 (_MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
5422 #define MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \
5423 (_MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5425 #define MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \
5426 (_MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5428 #define MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \
5429 (_MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5431 #define MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \
5432 (_MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5434 #define MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \
5435 (_MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5437 #define MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \
5438 (_MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5440 #define MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \
5441 (_MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5443 #define MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \
5444 (_MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5446 #define MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \
5447 (_MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5449 #define MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \
5450 (_MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5452 #define MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \
5453 (_MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
5455 #define MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \
5456 (_MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
5458 #define MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \
5459 (_MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
5461 #define MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \
5462 (_MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
5464 #define MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \
5465 (_MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
5467 #define MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \
5468 (_MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
5470 #define MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \
5471 (_MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
5473 #define MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \
5474 (_MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS | MUX_PAD_CTRL(NO_PAD_CTRL))
5476 #define MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \
5477 (_MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5479 #define MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \
5480 (_MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5482 #define MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \
5483 (_MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS | MUX_PAD_CTRL(NO_PAD_CTRL))
5485 #define MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \
5486 (_MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET | MUX_PAD_CTRL(NO_PAD_CTRL))
5488 #define MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \
5489 (_MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5491 #define MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \
5492 (_MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5494 #define MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \
5495 (_MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5497 #define MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \
5498 (_MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5500 #define MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \
5501 (_MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5503 #define MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \
5504 (_MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5506 #define MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \
5507 (_MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5509 #define MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \
5510 (_MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5512 #define MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \
5513 (_MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5515 #define MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \
5516 (_MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE | MUX_PAD_CTRL(NO_PAD_CTRL))
5518 #define MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \
5519 (_MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5521 #define MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \
5522 (_MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5524 #define MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \
5525 (_MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5527 #define MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \
5528 (_MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5530 #define MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \
5531 (_MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5533 #define MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \
5534 (_MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5536 #define MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \
5537 (_MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5539 #define MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \
5540 (_MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5542 #define MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \
5543 (_MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5545 #define MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \
5546 (_MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5548 #define MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \
5549 (_MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5551 #define MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \
5552 (_MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
5554 #define MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \
5555 (_MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
5557 #define MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \
5558 (_MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
5560 #define MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \
5561 (_MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
5563 #define MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \
5564 (_MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
5566 #define MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \
5567 (_MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
5569 #define MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \
5570 (_MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5572 #define MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \
5573 (_MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
5575 #define MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \
5576 (_MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5578 #define MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \
5579 (_MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
5581 #define MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \
5582 (_MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
5584 #define MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \
5585 (_MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
5587 #define MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \
5588 (_MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 | MUX_PAD_CTRL(NO_PAD_CTRL))
5590 #define MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \
5591 (_MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 | MUX_PAD_CTRL(NO_PAD_CTRL))
5593 #define MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \
5594 (_MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 | MUX_PAD_CTRL(NO_PAD_CTRL))
5596 #define MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \
5597 (_MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 | MUX_PAD_CTRL(NO_PAD_CTRL))
5599 #define MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \
5600 (_MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 | MUX_PAD_CTRL(NO_PAD_CTRL))
5602 #define MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \
5603 (_MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5605 #define MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \
5606 (_MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5608 #define MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \
5609 (_MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 | MUX_PAD_CTRL(NO_PAD_CTRL))
5611 #define MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \
5612 (_MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5614 #define MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \
5615 (_MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 | MUX_PAD_CTRL(NO_PAD_CTRL))
5617 #define MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \
5618 (_MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 | MUX_PAD_CTRL(NO_PAD_CTRL))
5620 #define MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \
5621 (_MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 | MUX_PAD_CTRL(NO_PAD_CTRL))
5623 #define MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \
5624 (_MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 | MUX_PAD_CTRL(NO_PAD_CTRL))
5626 #define MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \
5627 (_MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5629 #define MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \
5630 (_MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 | MUX_PAD_CTRL(NO_PAD_CTRL))
5632 #define MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \
5633 (_MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 | MUX_PAD_CTRL(NO_PAD_CTRL))
5635 #define MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \
5636 (_MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 | MUX_PAD_CTRL(NO_PAD_CTRL))
5638 #define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \
5639 (_MX6Q_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5640 #define MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \
5641 (_MX6Q_PAD_KEY_COL0__ENET_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5642 #define MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \
5643 (_MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
5644 #define MX6Q_PAD_KEY_COL0__KPP_COL_0 \
5645 (_MX6Q_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5646 #define MX6Q_PAD_KEY_COL0__UART4_TXD \
5647 (_MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5648 #define MX6Q_PAD_KEY_COL0__UART4_RXD \
5649 (_MX6Q_PAD_KEY_COL0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5650 #define MX6Q_PAD_KEY_COL0__GPIO_4_6 \
5651 (_MX6Q_PAD_KEY_COL0__GPIO_4_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5652 #define MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \
5653 (_MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5654 #define MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \
5655 (_MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
5657 #define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \
5658 (_MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
5659 #define MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \
5660 (_MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5661 #define MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \
5662 (_MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5663 #define MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \
5664 (_MX6Q_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5665 #define MX6Q_PAD_KEY_ROW0__UART4_TXD \
5666 (_MX6Q_PAD_KEY_ROW0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5667 #define MX6Q_PAD_KEY_ROW0__UART4_RXD \
5668 (_MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5669 #define MX6Q_PAD_KEY_ROW0__GPIO_4_7 \
5670 (_MX6Q_PAD_KEY_ROW0__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5671 #define MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \
5672 (_MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5673 #define MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \
5674 (_MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5676 #define MX6Q_PAD_KEY_COL1__ECSPI1_MISO \
5677 (_MX6Q_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
5678 #define MX6Q_PAD_KEY_COL1__ENET_MDIO \
5679 (_MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
5680 #define MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \
5681 (_MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
5682 #define MX6Q_PAD_KEY_COL1__KPP_COL_1 \
5683 (_MX6Q_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5684 #define MX6Q_PAD_KEY_COL1__UART5_TXD \
5685 (_MX6Q_PAD_KEY_COL1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5686 #define MX6Q_PAD_KEY_COL1__UART5_RXD \
5687 (_MX6Q_PAD_KEY_COL1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5688 #define MX6Q_PAD_KEY_COL1__GPIO_4_8 \
5689 (_MX6Q_PAD_KEY_COL1__GPIO_4_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5690 #define MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \
5691 (_MX6Q_PAD_KEY_COL1__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5692 #define MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \
5693 (_MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5695 #define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \
5696 (_MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5697 #define MX6Q_PAD_KEY_ROW1__ENET_COL \
5698 (_MX6Q_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
5699 #define MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \
5700 (_MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
5701 #define MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \
5702 (_MX6Q_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5703 #define MX6Q_PAD_KEY_ROW1__UART5_TXD \
5704 (_MX6Q_PAD_KEY_ROW1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5705 #define MX6Q_PAD_KEY_ROW1__UART5_RXD \
5706 (_MX6Q_PAD_KEY_ROW1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5707 #define MX6Q_PAD_KEY_ROW1__GPIO_4_9 \
5708 (_MX6Q_PAD_KEY_ROW1__GPIO_4_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
5709 #define MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \
5710 (_MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5711 #define MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \
5712 (_MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5714 #define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \
5715 (_MX6Q_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5716 #define MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \
5717 (_MX6Q_PAD_KEY_COL2__ENET_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5718 #define MX6Q_PAD_KEY_COL2__CAN1_TXCAN \
5719 (_MX6Q_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5720 #define MX6Q_PAD_KEY_COL2__KPP_COL_2 \
5721 (_MX6Q_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5722 #define MX6Q_PAD_KEY_COL2__ENET_MDC \
5723 (_MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
5724 #define MX6Q_PAD_KEY_COL2__GPIO_4_10 \
5725 (_MX6Q_PAD_KEY_COL2__GPIO_4_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
5726 #define MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \
5727 (_MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))
5728 #define MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \
5729 (_MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5731 #define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \
5732 (_MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5733 #define MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \
5734 (_MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5735 #define MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \
5736 (_MX6Q_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5737 #define MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \
5738 (_MX6Q_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5739 #define MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \
5740 (_MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5741 #define MX6Q_PAD_KEY_ROW2__GPIO_4_11 \
5742 (_MX6Q_PAD_KEY_ROW2__GPIO_4_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
5743 #define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \
5744 (_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
5745 #define MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \
5746 (_MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5748 #define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \
5749 (_MX6Q_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5750 #define MX6Q_PAD_KEY_COL3__ENET_CRS \
5751 (_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
5752 #define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \
5753 (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
5754 #define MX6Q_PAD_KEY_COL3__KPP_COL_3 \
5755 (_MX6Q_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5756 #define MX6Q_PAD_KEY_COL3__I2C2_SCL \
5757 (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
5758 #define MX6Q_PAD_KEY_COL3__GPIO_4_12 \
5759 (_MX6Q_PAD_KEY_COL3__GPIO_4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
5760 #define MX6Q_PAD_KEY_COL3__SPDIF_IN1 \
5761 (_MX6Q_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5762 #define MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \
5763 (_MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5765 #define MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \
5766 (_MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5767 #define MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \
5768 (_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5769 #define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \
5770 (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
5771 #define MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \
5772 (_MX6Q_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5773 #define MX6Q_PAD_KEY_ROW3__I2C2_SDA \
5774 (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
5775 #define MX6Q_PAD_KEY_ROW3__GPIO_4_13 \
5776 (_MX6Q_PAD_KEY_ROW3__GPIO_4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
5777 #define MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \
5778 (_MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5779 #define MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \
5780 (_MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5782 #define MX6Q_PAD_KEY_COL4__CAN2_TXCAN \
5783 (_MX6Q_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5784 #define MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \
5785 (_MX6Q_PAD_KEY_COL4__IPU1_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5786 #define MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \
5787 (_MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
5788 #define MX6Q_PAD_KEY_COL4__KPP_COL_4 \
5789 (_MX6Q_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5790 #define MX6Q_PAD_KEY_COL4__UART5_CTS \
5791 (_MX6Q_PAD_KEY_COL4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5792 #define MX6Q_PAD_KEY_COL4__UART5_RTS \
5793 (_MX6Q_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5794 #define MX6Q_PAD_KEY_COL4__GPIO_4_14 \
5795 (_MX6Q_PAD_KEY_COL4__GPIO_4_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
5796 #define MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \
5797 (_MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
5798 #define MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \
5799 (_MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5801 #define MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \
5802 (_MX6Q_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5803 #define MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \
5804 (_MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5805 #define MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \
5806 (_MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
5807 #define MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \
5808 (_MX6Q_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5809 #define MX6Q_PAD_KEY_ROW4__UART5_CTS \
5810 (_MX6Q_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5811 #define MX6Q_PAD_KEY_ROW4__GPIO_4_15 \
5812 (_MX6Q_PAD_KEY_ROW4__GPIO_4_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
5813 #define MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \
5814 (_MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
5815 #define MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \
5816 (_MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5818 #define MX6Q_PAD_GPIO_0__CCM_CLKO \
5819 (_MX6Q_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
5820 #define MX6Q_PAD_GPIO_0__KPP_COL_5 \
5821 (_MX6Q_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5822 #define MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \
5823 (_MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5824 #define MX6Q_PAD_GPIO_0__EPIT1_EPITO \
5825 (_MX6Q_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
5826 #define MX6Q_PAD_GPIO_0__GPIO_1_0 \
5827 (_MX6Q_PAD_GPIO_0__GPIO_1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5828 #define MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \
5829 (_MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
5830 #define MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \
5831 (_MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5833 #define MX6Q_PAD_GPIO_1__ESAI1_SCKR \
5834 (_MX6Q_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
5835 #define MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \
5836 (_MX6Q_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
5837 #define MX6Q_PAD_GPIO_1__KPP_ROW_5 \
5838 (_MX6Q_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5839 #define MX6Q_PAD_GPIO_1__PWM2_PWMO \
5840 (_MX6Q_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
5841 #define MX6Q_PAD_GPIO_1__GPIO_1_1 \
5842 (_MX6Q_PAD_GPIO_1__GPIO_1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5843 #define MX6Q_PAD_GPIO_1__USDHC1_CD \
5844 (_MX6Q_PAD_GPIO_1__USDHC1_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5845 #define MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \
5846 (_MX6Q_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL))
5848 #define MX6Q_PAD_GPIO_9__ESAI1_FSR \
5849 (_MX6Q_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
5850 #define MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \
5851 (_MX6Q_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
5852 #define MX6Q_PAD_GPIO_9__KPP_COL_6 \
5853 (_MX6Q_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5854 #define MX6Q_PAD_GPIO_9__CCM_REF_EN_B \
5855 (_MX6Q_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
5856 #define MX6Q_PAD_GPIO_9__PWM1_PWMO \
5857 (_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
5858 #define MX6Q_PAD_GPIO_9__GPIO_1_9 \
5859 (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
5860 #define MX6Q_PAD_GPIO_9__USDHC1_WP \
5861 (_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5862 #define MX6Q_PAD_GPIO_9__SRC_EARLY_RST \
5863 (_MX6Q_PAD_GPIO_9__SRC_EARLY_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
5865 #define MX6Q_PAD_GPIO_3__ESAI1_HCKR \
5866 (_MX6Q_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
5867 #define MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \
5868 (_MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5869 #define MX6Q_PAD_GPIO_3__I2C3_SCL \
5870 (_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
5871 #define MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \
5872 (_MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5873 #define MX6Q_PAD_GPIO_3__CCM_CLKO2 \
5874 (_MX6Q_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5875 #define MX6Q_PAD_GPIO_3__GPIO_1_3 \
5876 (_MX6Q_PAD_GPIO_3__GPIO_1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5877 #define MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \
5878 (_MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
5879 #define MX6Q_PAD_GPIO_3__MLB_MLBCLK \
5880 (_MX6Q_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5882 #define MX6Q_PAD_GPIO_6__ESAI1_SCKT \
5883 (_MX6Q_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
5884 #define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
5885 (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5886 #define MX6Q_PAD_GPIO_6__I2C3_SDA \
5887 (_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
5888 #define MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \
5889 (_MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5890 #define MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \
5891 (_MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
5892 #define MX6Q_PAD_GPIO_6__GPIO_1_6 \
5893 (_MX6Q_PAD_GPIO_6__GPIO_1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5894 #define MX6Q_PAD_GPIO_6__USDHC2_LCTL \
5895 (_MX6Q_PAD_GPIO_6__USDHC2_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5896 #define MX6Q_PAD_GPIO_6__MLB_MLBSIG \
5897 (_MX6Q_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
5899 #define MX6Q_PAD_GPIO_2__ESAI1_FST \
5900 (_MX6Q_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
5901 #define MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \
5902 (_MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5903 #define MX6Q_PAD_GPIO_2__KPP_ROW_6 \
5904 (_MX6Q_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
5905 #define MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \
5906 (_MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5907 #define MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \
5908 (_MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5909 #define MX6Q_PAD_GPIO_2__GPIO_1_2 \
5910 (_MX6Q_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5911 #define MX6Q_PAD_GPIO_2__USDHC2_WP \
5912 (_MX6Q_PAD_GPIO_2__USDHC2_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5913 #define MX6Q_PAD_GPIO_2__MLB_MLBDAT \
5914 (_MX6Q_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
5916 #define MX6Q_PAD_GPIO_4__ESAI1_HCKT \
5917 (_MX6Q_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
5918 #define MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \
5919 (_MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5920 #define MX6Q_PAD_GPIO_4__KPP_COL_7 \
5921 (_MX6Q_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5922 #define MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \
5923 (_MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5924 #define MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \
5925 (_MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5926 #define MX6Q_PAD_GPIO_4__GPIO_1_4 \
5927 (_MX6Q_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5928 #define MX6Q_PAD_GPIO_4__USDHC2_CD \
5929 (_MX6Q_PAD_GPIO_4__USDHC2_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5930 #define MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \
5931 (_MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED | MUX_PAD_CTRL(NO_PAD_CTRL))
5933 #define MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \
5934 (_MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
5935 #define MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \
5936 (_MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
5937 #define MX6Q_PAD_GPIO_5__KPP_ROW_7 \
5938 (_MX6Q_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5939 #define MX6Q_PAD_GPIO_5__CCM_CLKO \
5940 (_MX6Q_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
5941 #define MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \
5942 (_MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5943 #define MX6Q_PAD_GPIO_5__GPIO_1_5 \
5944 (_MX6Q_PAD_GPIO_5__GPIO_1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
5945 #define MX6Q_PAD_GPIO_5__I2C3_SCL \
5946 (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
5947 #define MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \
5948 (_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI | MUX_PAD_CTRL(NO_PAD_CTRL))
5950 #define MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \
5951 (_MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5952 #define MX6Q_PAD_GPIO_7__ECSPI5_RDY \
5953 (_MX6Q_PAD_GPIO_7__ECSPI5_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
5954 #define MX6Q_PAD_GPIO_7__EPIT1_EPITO \
5955 (_MX6Q_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
5956 #define MX6Q_PAD_GPIO_7__CAN1_TXCAN \
5957 (_MX6Q_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5958 #define MX6Q_PAD_GPIO_7__UART2_TXD \
5959 (_MX6Q_PAD_GPIO_7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5960 #define MX6Q_PAD_GPIO_7__UART2_RXD \
5961 (_MX6Q_PAD_GPIO_7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5962 #define MX6Q_PAD_GPIO_7__GPIO_1_7 \
5963 (_MX6Q_PAD_GPIO_7__GPIO_1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
5964 #define MX6Q_PAD_GPIO_7__SPDIF_PLOCK \
5965 (_MX6Q_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
5966 #define MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \
5967 (_MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
5969 #define MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \
5970 (_MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
5971 #define MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \
5972 (_MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5973 #define MX6Q_PAD_GPIO_8__EPIT2_EPITO \
5974 (_MX6Q_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
5975 #define MX6Q_PAD_GPIO_8__CAN1_RXCAN \
5976 (_MX6Q_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
5977 #define MX6Q_PAD_GPIO_8__UART2_TXD \
5978 (_MX6Q_PAD_GPIO_8__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5979 #define MX6Q_PAD_GPIO_8__UART2_RXD \
5980 (_MX6Q_PAD_GPIO_8__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5981 #define MX6Q_PAD_GPIO_8__GPIO_1_8 \
5982 (_MX6Q_PAD_GPIO_8__GPIO_1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
5983 #define MX6Q_PAD_GPIO_8__SPDIF_SRCLK \
5984 (_MX6Q_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
5985 #define MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \
5986 (_MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))
5988 #define MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \
5989 (_MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
5990 #define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \
5991 (_MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
5992 #define MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
5993 (_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
5994 #define MX6Q_PAD_GPIO_16__USDHC1_LCTL \
5995 (_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5996 #define MX6Q_PAD_GPIO_16__SPDIF_IN1 \
5997 (_MX6Q_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
5998 #define MX6Q_PAD_GPIO_16__GPIO_7_11 \
5999 (_MX6Q_PAD_GPIO_16__GPIO_7_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6000 #define MX6Q_PAD_GPIO_16__I2C3_SDA \
6001 (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
6002 #define MX6Q_PAD_GPIO_16__SJC_DE_B \
6003 (_MX6Q_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
6005 #define MX6Q_PAD_GPIO_17__ESAI1_TX0 \
6006 (_MX6Q_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6007 #define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \
6008 (_MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
6009 #define MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \
6010 (_MX6Q_PAD_GPIO_17__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
6011 #define MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \
6012 (_MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6013 #define MX6Q_PAD_GPIO_17__SPDIF_OUT1 \
6014 (_MX6Q_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6015 #define MX6Q_PAD_GPIO_17__GPIO_7_12 \
6016 (_MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6017 #define MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \
6018 (_MX6Q_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL))
6020 #define MX6Q_PAD_GPIO_18__ESAI1_TX1 \
6021 (_MX6Q_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6022 #define MX6Q_PAD_GPIO_18__ENET_RX_CLK \
6023 (_MX6Q_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6024 #define MX6Q_PAD_GPIO_18__USDHC3_VSELECT \
6025 (_MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6026 #define MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \
6027 (_MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6028 #define MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \
6029 (_MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6030 #define MX6Q_PAD_GPIO_18__GPIO_7_13 \
6031 (_MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6032 #define MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \
6033 (_MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL | MUX_PAD_CTRL(NO_PAD_CTRL))
6034 #define MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \
6035 (_MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
6037 #define MX6Q_PAD_GPIO_19__KPP_COL_5 \
6038 (_MX6Q_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6039 #define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \
6040 (_MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
6041 #define MX6Q_PAD_GPIO_19__SPDIF_OUT1 \
6042 (_MX6Q_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6043 #define MX6Q_PAD_GPIO_19__CCM_CLKO \
6044 (_MX6Q_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
6045 #define MX6Q_PAD_GPIO_19__ECSPI1_RDY \
6046 (_MX6Q_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
6047 #define MX6Q_PAD_GPIO_19__GPIO_4_5 \
6048 (_MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6049 #define MX6Q_PAD_GPIO_19__ENET_TX_ER \
6050 (_MX6Q_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
6051 #define MX6Q_PAD_GPIO_19__SRC_INT_BOOT \
6052 (_MX6Q_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL))
6054 #define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \
6055 (_MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6056 #define MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \
6057 (_MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6058 #define MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \
6059 (_MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6060 #define MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \
6061 (_MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6062 #define MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \
6063 (_MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
6064 #define MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \
6065 (_MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO | MUX_PAD_CTRL(NO_PAD_CTRL))
6067 #define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \
6068 (_MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
6069 #define MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \
6070 (_MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6071 #define MX6Q_PAD_CSI0_MCLK__CCM_CLKO \
6072 (_MX6Q_PAD_CSI0_MCLK__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
6073 #define MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \
6074 (_MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6075 #define MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \
6076 (_MX6Q_PAD_CSI0_MCLK__GPIO_5_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6077 #define MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \
6078 (_MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
6079 #define MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \
6080 (_MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
6082 #define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \
6083 (_MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
6084 #define MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \
6085 (_MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6086 #define MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \
6087 (_MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6088 #define MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \
6089 (_MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6090 #define MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \
6091 (_MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
6092 #define MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \
6093 (_MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
6094 #define MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \
6095 (_MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6097 #define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \
6098 (_MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
6099 #define MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \
6100 (_MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6101 #define MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \
6102 (_MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6103 #define MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \
6104 (_MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6105 #define MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \
6106 (_MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
6107 #define MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \
6108 (_MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
6109 #define MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \
6110 (_MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6112 #define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \
6113 (_MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6114 #define MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \
6115 (_MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6116 #define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \
6117 (_MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6118 #define MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \
6119 (_MX6Q_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6120 #define MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \
6121 (_MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
6122 #define MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \
6123 (_MX6Q_PAD_CSI0_DAT4__GPIO_5_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
6124 #define MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \
6125 (_MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
6126 #define MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \
6127 (_MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6129 #define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \
6130 (_MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6131 #define MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \
6132 (_MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6133 #define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \
6134 (_MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
6135 #define MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \
6136 (_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6137 #define MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \
6138 (_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
6139 #define MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \
6140 (_MX6Q_PAD_CSI0_DAT5__GPIO_5_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
6141 #define MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \
6142 (_MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
6143 #define MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \
6144 (_MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6146 #define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \
6147 (_MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6148 #define MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \
6149 (_MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6150 #define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \
6151 (_MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
6152 #define MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \
6153 (_MX6Q_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6154 #define MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \
6155 (_MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
6156 #define MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \
6157 (_MX6Q_PAD_CSI0_DAT6__GPIO_5_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
6158 #define MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \
6159 (_MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
6160 #define MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \
6161 (_MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6163 #define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \
6164 (_MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6165 #define MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \
6166 (_MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6167 #define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \
6168 (_MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6169 #define MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \
6170 (_MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6171 #define MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \
6172 (_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
6173 #define MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \
6174 (_MX6Q_PAD_CSI0_DAT7__GPIO_5_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
6175 #define MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \
6176 (_MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
6177 #define MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \
6178 (_MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6180 #define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \
6181 (_MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6182 #define MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \
6183 (_MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6184 #define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \
6185 (_MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6186 #define MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \
6187 (_MX6Q_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6188 #define MX6Q_PAD_CSI0_DAT8__I2C1_SDA \
6189 (_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
6190 #define MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \
6191 (_MX6Q_PAD_CSI0_DAT8__GPIO_5_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
6192 #define MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \
6193 (_MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
6194 #define MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \
6195 (_MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6197 #define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \
6198 (_MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6199 #define MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \
6200 (_MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6201 #define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \
6202 (_MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
6203 #define MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \
6204 (_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6205 #define MX6Q_PAD_CSI0_DAT9__I2C1_SCL \
6206 (_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
6207 #define MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \
6208 (_MX6Q_PAD_CSI0_DAT9__GPIO_5_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
6209 #define MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \
6210 (_MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
6211 #define MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \
6212 (_MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6214 #define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \
6215 (_MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6216 #define MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \
6217 (_MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
6218 #define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \
6219 (_MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
6220 #define MX6Q_PAD_CSI0_DAT10__UART1_TXD \
6221 (_MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6222 #define MX6Q_PAD_CSI0_DAT10__UART1_RXD \
6223 (_MX6Q_PAD_CSI0_DAT10__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6224 #define MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \
6225 (_MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6226 #define MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \
6227 (_MX6Q_PAD_CSI0_DAT10__GPIO_5_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
6228 #define MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \
6229 (_MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
6230 #define MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \
6231 (_MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6233 #define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \
6234 (_MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6235 #define MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \
6236 (_MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
6237 #define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \
6238 (_MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6239 #define MX6Q_PAD_CSI0_DAT11__UART1_TXD \
6240 (_MX6Q_PAD_CSI0_DAT11__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6241 #define MX6Q_PAD_CSI0_DAT11__UART1_RXD \
6242 (_MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6243 #define MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \
6244 (_MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6245 #define MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \
6246 (_MX6Q_PAD_CSI0_DAT11__GPIO_5_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
6247 #define MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \
6248 (_MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
6249 #define MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \
6250 (_MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6252 #define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \
6253 (_MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6254 #define MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \
6255 (_MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6256 #define MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \
6257 (_MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6258 #define MX6Q_PAD_CSI0_DAT12__UART4_TXD \
6259 (_MX6Q_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6260 #define MX6Q_PAD_CSI0_DAT12__UART4_RXD \
6261 (_MX6Q_PAD_CSI0_DAT12__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6262 #define MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \
6263 (_MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6264 #define MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \
6265 (_MX6Q_PAD_CSI0_DAT12__GPIO_5_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
6266 #define MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \
6267 (_MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
6268 #define MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \
6269 (_MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6271 #define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \
6272 (_MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6273 #define MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \
6274 (_MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6275 #define MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \
6276 (_MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6277 #define MX6Q_PAD_CSI0_DAT13__UART4_TXD \
6278 (_MX6Q_PAD_CSI0_DAT13__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6279 #define MX6Q_PAD_CSI0_DAT13__UART4_RXD \
6280 (_MX6Q_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6281 #define MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \
6282 (_MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6283 #define MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \
6284 (_MX6Q_PAD_CSI0_DAT13__GPIO_5_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
6285 #define MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \
6286 (_MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
6287 #define MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \
6288 (_MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6290 #define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \
6291 (_MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6292 #define MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \
6293 (_MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6294 #define MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \
6295 (_MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6296 #define MX6Q_PAD_CSI0_DAT14__UART5_TXD \
6297 (_MX6Q_PAD_CSI0_DAT14__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6298 #define MX6Q_PAD_CSI0_DAT14__UART5_RXD \
6299 (_MX6Q_PAD_CSI0_DAT14__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6300 #define MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \
6301 (_MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6302 #define MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \
6303 (_MX6Q_PAD_CSI0_DAT14__GPIO_6_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6304 #define MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \
6305 (_MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
6306 #define MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \
6307 (_MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6309 #define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \
6310 (_MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6311 #define MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \
6312 (_MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6313 #define MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \
6314 (_MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6315 #define MX6Q_PAD_CSI0_DAT15__UART5_TXD \
6316 (_MX6Q_PAD_CSI0_DAT15__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6317 #define MX6Q_PAD_CSI0_DAT15__UART5_RXD \
6318 (_MX6Q_PAD_CSI0_DAT15__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6319 #define MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \
6320 (_MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6321 #define MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \
6322 (_MX6Q_PAD_CSI0_DAT15__GPIO_6_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6323 #define MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \
6324 (_MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
6325 #define MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \
6326 (_MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6328 #define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \
6329 (_MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6330 #define MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \
6331 (_MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6332 #define MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \
6333 (_MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
6334 #define MX6Q_PAD_CSI0_DAT16__UART4_CTS \
6335 (_MX6Q_PAD_CSI0_DAT16__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6336 #define MX6Q_PAD_CSI0_DAT16__UART4_RTS \
6337 (_MX6Q_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6338 #define MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \
6339 (_MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6340 #define MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \
6341 (_MX6Q_PAD_CSI0_DAT16__GPIO_6_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6342 #define MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \
6343 (_MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
6344 #define MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \
6345 (_MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6347 #define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \
6348 (_MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6349 #define MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \
6350 (_MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6351 #define MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \
6352 (_MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
6353 #define MX6Q_PAD_CSI0_DAT17__UART4_CTS \
6354 (_MX6Q_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6355 #define MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \
6356 (_MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6357 #define MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \
6358 (_MX6Q_PAD_CSI0_DAT17__GPIO_6_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6359 #define MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \
6360 (_MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
6361 #define MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \
6362 (_MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6364 #define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \
6365 (_MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6366 #define MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \
6367 (_MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6368 #define MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \
6369 (_MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
6370 #define MX6Q_PAD_CSI0_DAT18__UART5_CTS \
6371 (_MX6Q_PAD_CSI0_DAT18__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6372 #define MX6Q_PAD_CSI0_DAT18__UART5_RTS \
6373 (_MX6Q_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6374 #define MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \
6375 (_MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6376 #define MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \
6377 (_MX6Q_PAD_CSI0_DAT18__GPIO_6_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6378 #define MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \
6379 (_MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
6380 #define MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \
6381 (_MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6383 #define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \
6384 (_MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6385 #define MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \
6386 (_MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6387 #define MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \
6388 (_MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
6389 #define MX6Q_PAD_CSI0_DAT19__UART5_CTS \
6390 (_MX6Q_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6391 #define MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \
6392 (_MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6393 #define MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \
6394 (_MX6Q_PAD_CSI0_DAT19__GPIO_6_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6395 #define MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \
6396 (_MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
6397 #define MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \
6398 (_MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6400 #define MX6Q_PAD_JTAG_TMS__SJC_TMS \
6401 (_MX6Q_PAD_JTAG_TMS__SJC_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
6403 #define MX6Q_PAD_JTAG_MOD__SJC_MOD \
6404 (_MX6Q_PAD_JTAG_MOD__SJC_MOD | MUX_PAD_CTRL(NO_PAD_CTRL))
6406 #define MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \
6407 (_MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB | MUX_PAD_CTRL(NO_PAD_CTRL))
6409 #define MX6Q_PAD_JTAG_TDI__SJC_TDI \
6410 (_MX6Q_PAD_JTAG_TDI__SJC_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
6412 #define MX6Q_PAD_JTAG_TCK__SJC_TCK \
6413 (_MX6Q_PAD_JTAG_TCK__SJC_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
6415 #define MX6Q_PAD_JTAG_TDO__SJC_TDO \
6416 (_MX6Q_PAD_JTAG_TDO__SJC_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
6418 #define MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \
6419 (_MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6421 #define MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \
6422 (_MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6424 #define MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \
6425 (_MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6427 #define MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \
6428 (_MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6430 #define MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \
6431 (_MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6433 #define MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \
6434 (_MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6436 #define MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \
6437 (_MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6439 #define MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \
6440 (_MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6442 #define MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \
6443 (_MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6445 #define MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \
6446 (_MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6448 #define MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \
6449 (_MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6451 #define MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \
6452 (_MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM | MUX_PAD_CTRL(NO_PAD_CTRL))
6454 #define MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \
6455 (_MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ | MUX_PAD_CTRL(NO_PAD_CTRL))
6457 #define MX6Q_PAD_POR_B__SRC_POR_B \
6458 (_MX6Q_PAD_POR_B__SRC_POR_B | MUX_PAD_CTRL(NO_PAD_CTRL))
6460 #define MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \
6461 (_MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6463 #define MX6Q_PAD_RESET_IN_B__SRC_RESET_B \
6464 (_MX6Q_PAD_RESET_IN_B__SRC_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
6466 #define MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \
6467 (_MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6469 #define MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \
6470 (_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
6472 #define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 \
6473 (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6474 #define MX6Q_PAD_SD3_DAT7__UART1_TXD \
6475 (_MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6476 #define MX6Q_PAD_SD3_DAT7__UART1_RXD \
6477 (_MX6Q_PAD_SD3_DAT7__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6478 #define MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \
6479 (_MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
6480 #define MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \
6481 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6482 #define MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \
6483 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6484 #define MX6Q_PAD_SD3_DAT7__GPIO_6_17 \
6485 (_MX6Q_PAD_SD3_DAT7__GPIO_6_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6486 #define MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \
6487 (_MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6488 #define MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \
6489 (_MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))
6491 #define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 \
6492 (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6493 #define MX6Q_PAD_SD3_DAT6__UART1_TXD \
6494 (_MX6Q_PAD_SD3_DAT6__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6495 #define MX6Q_PAD_SD3_DAT6__UART1_RXD \
6496 (_MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6497 #define MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \
6498 (_MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
6499 #define MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \
6500 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6501 #define MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \
6502 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6503 #define MX6Q_PAD_SD3_DAT6__GPIO_6_18 \
6504 (_MX6Q_PAD_SD3_DAT6__GPIO_6_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6505 #define MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \
6506 (_MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6507 #define MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \
6508 (_MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6510 #define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 \
6511 (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6512 #define MX6Q_PAD_SD3_DAT5__UART2_TXD \
6513 (_MX6Q_PAD_SD3_DAT5__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6514 #define MX6Q_PAD_SD3_DAT5__UART2_RXD \
6515 (_MX6Q_PAD_SD3_DAT5__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6516 #define MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \
6517 (_MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
6518 #define MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \
6519 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6520 #define MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \
6521 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6522 #define MX6Q_PAD_SD3_DAT5__GPIO_7_0 \
6523 (_MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6524 #define MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \
6525 (_MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6526 #define MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \
6527 (_MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6529 #define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 \
6530 (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6531 #define MX6Q_PAD_SD3_DAT4__UART2_TXD \
6532 (_MX6Q_PAD_SD3_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6533 #define MX6Q_PAD_SD3_DAT4__UART2_RXD \
6534 (_MX6Q_PAD_SD3_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6535 #define MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \
6536 (_MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
6537 #define MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \
6538 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6539 #define MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \
6540 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6541 #define MX6Q_PAD_SD3_DAT4__GPIO_7_1 \
6542 (_MX6Q_PAD_SD3_DAT4__GPIO_7_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6543 #define MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \
6544 (_MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6545 #define MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \
6546 (_MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6548 #define MX6Q_PAD_SD3_CMD__USDHC3_CMD \
6549 (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6550 #define MX6Q_PAD_SD3_CMD__UART2_CTS \
6551 (_MX6Q_PAD_SD3_CMD__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6552 #define MX6Q_PAD_SD3_CMD__CAN1_TXCAN \
6553 (_MX6Q_PAD_SD3_CMD__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
6554 #define MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \
6555 (_MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6556 #define MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \
6557 (_MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6558 #define MX6Q_PAD_SD3_CMD__GPIO_7_2 \
6559 (_MX6Q_PAD_SD3_CMD__GPIO_7_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6560 #define MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \
6561 (_MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6562 #define MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \
6563 (_MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6565 #define MX6Q_PAD_SD3_CLK__USDHC3_CLK \
6566 (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6567 #define MX6Q_PAD_SD3_CLK__UART2_CTS \
6568 (_MX6Q_PAD_SD3_CLK__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6569 #define MX6Q_PAD_SD3_CLK__UART2_RTS \
6570 (_MX6Q_PAD_SD3_CLK__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6571 #define MX6Q_PAD_SD3_CLK__CAN1_RXCAN \
6572 (_MX6Q_PAD_SD3_CLK__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
6573 #define MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \
6574 (_MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6575 #define MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \
6576 (_MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6577 #define MX6Q_PAD_SD3_CLK__GPIO_7_3 \
6578 (_MX6Q_PAD_SD3_CLK__GPIO_7_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6579 #define MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \
6580 (_MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6581 #define MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \
6582 (_MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6584 #define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 \
6585 (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6586 #define MX6Q_PAD_SD3_DAT0__UART1_CTS \
6587 (_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6588 #define MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \
6589 (_MX6Q_PAD_SD3_DAT0__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
6590 #define MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
6591 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6592 #define MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \
6593 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6594 #define MX6Q_PAD_SD3_DAT0__GPIO_7_4 \
6595 (_MX6Q_PAD_SD3_DAT0__GPIO_7_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6596 #define MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \
6597 (_MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6598 #define MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \
6599 (_MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6601 #define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 \
6602 (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6603 #define MX6Q_PAD_SD3_DAT1__UART1_CTS \
6604 (_MX6Q_PAD_SD3_DAT1__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6605 #define MX6Q_PAD_SD3_DAT1__UART1_RTS \
6606 (_MX6Q_PAD_SD3_DAT1__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6607 #define MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \
6608 (_MX6Q_PAD_SD3_DAT1__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
6609 #define MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \
6610 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6611 #define MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \
6612 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6613 #define MX6Q_PAD_SD3_DAT1__GPIO_7_5 \
6614 (_MX6Q_PAD_SD3_DAT1__GPIO_7_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6615 #define MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \
6616 (_MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6617 #define MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \
6618 (_MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6620 #define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 \
6621 (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6622 #define MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \
6623 (_MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
6624 #define MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \
6625 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6626 #define MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \
6627 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6628 #define MX6Q_PAD_SD3_DAT2__GPIO_7_6 \
6629 (_MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6630 #define MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \
6631 (_MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
6632 #define MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \
6633 (_MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6635 #define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 \
6636 (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6637 #define MX6Q_PAD_SD3_DAT3__UART3_CTS \
6638 (_MX6Q_PAD_SD3_DAT3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6639 #define MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \
6640 (_MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
6641 #define MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \
6642 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6643 #define MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \
6644 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6645 #define MX6Q_PAD_SD3_DAT3__GPIO_7_7 \
6646 (_MX6Q_PAD_SD3_DAT3__GPIO_7_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6647 #define MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \
6648 (_MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
6649 #define MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \
6650 (_MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6652 #define MX6Q_PAD_SD3_RST__USDHC3_RST \
6653 (_MX6Q_PAD_SD3_RST__USDHC3_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6654 #define MX6Q_PAD_SD3_RST__UART3_CTS \
6655 (_MX6Q_PAD_SD3_RST__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6656 #define MX6Q_PAD_SD3_RST__UART3_RTS \
6657 (_MX6Q_PAD_SD3_RST__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6658 #define MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \
6659 (_MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
6660 #define MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \
6661 (_MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6662 #define MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \
6663 (_MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6664 #define MX6Q_PAD_SD3_RST__GPIO_7_8 \
6665 (_MX6Q_PAD_SD3_RST__GPIO_7_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6666 #define MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \
6667 (_MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
6668 #define MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \
6669 (_MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6671 #define MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \
6672 (_MX6Q_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL))
6673 #define MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \
6674 (_MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6675 #define MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \
6676 (_MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
6677 #define MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \
6678 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6679 #define MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \
6680 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
6681 #define MX6Q_PAD_NANDF_CLE__GPIO_6_7 \
6682 (_MX6Q_PAD_NANDF_CLE__GPIO_6_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6683 #define MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \
6684 (_MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
6685 #define MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \
6686 (_MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6688 #define MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \
6689 (_MX6Q_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
6690 #define MX6Q_PAD_NANDF_ALE__USDHC4_RST \
6691 (_MX6Q_PAD_NANDF_ALE__USDHC4_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6692 #define MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \
6693 (_MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6694 #define MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \
6695 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6696 #define MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \
6697 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
6698 #define MX6Q_PAD_NANDF_ALE__GPIO_6_8 \
6699 (_MX6Q_PAD_NANDF_ALE__GPIO_6_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6700 #define MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \
6701 (_MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
6702 #define MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \
6703 (_MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6705 #define MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \
6706 (_MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(NO_PAD_CTRL))
6707 #define MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \
6708 (_MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6709 #define MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \
6710 (_MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6711 #define MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \
6712 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6713 #define MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \
6714 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
6715 #define MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \
6716 (_MX6Q_PAD_NANDF_WP_B__GPIO_6_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6717 #define MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \
6718 (_MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
6719 #define MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \
6720 (_MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6722 #define MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \
6723 (_MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6724 #define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \
6725 (_MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6726 #define MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \
6727 (_MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6728 #define MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \
6729 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6730 #define MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \
6731 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
6732 #define MX6Q_PAD_NANDF_RB0__GPIO_6_10 \
6733 (_MX6Q_PAD_NANDF_RB0__GPIO_6_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6734 #define MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \
6735 (_MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
6736 #define MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \
6737 (_MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6739 #define MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \
6740 (_MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(NO_PAD_CTRL))
6741 #define MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \
6742 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6743 #define MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \
6744 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6745 #define MX6Q_PAD_NANDF_CS0__GPIO_6_11 \
6746 (_MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6747 #define MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \
6748 (_MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6750 #define MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \
6751 (_MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(NO_PAD_CTRL))
6752 #define MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \
6753 (_MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6754 #define MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \
6755 (_MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6756 #define MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \
6757 (_MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6758 #define MX6Q_PAD_NANDF_CS1__GPIO_6_14 \
6759 (_MX6Q_PAD_NANDF_CS1__GPIO_6_14 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6760 #define MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \
6761 (_MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT | MUX_PAD_CTRL(NO_PAD_CTRL))
6763 #define MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \
6764 (_MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(NO_PAD_CTRL))
6765 #define MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \
6766 (_MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6767 #define MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \
6768 (_MX6Q_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6769 #define MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \
6770 (_MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
6771 #define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \
6772 (_MX6Q_PAD_NANDF_CS2__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6773 #define MX6Q_PAD_NANDF_CS2__GPIO_6_15 \
6774 (_MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
6775 #define MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \
6776 (_MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6778 #define MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \
6779 (_MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(NO_PAD_CTRL))
6780 #define MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \
6781 (_MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6782 #define MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \
6783 (_MX6Q_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6784 #define MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \
6785 (_MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
6786 #define MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \
6787 (_MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6788 #define MX6Q_PAD_NANDF_CS3__GPIO_6_16 \
6789 (_MX6Q_PAD_NANDF_CS3__GPIO_6_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6790 #define MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \
6791 (_MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6792 #define MX6Q_PAD_NANDF_CS3__TPSMP_CLK \
6793 (_MX6Q_PAD_NANDF_CS3__TPSMP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
6795 #define MX6Q_PAD_SD4_CMD__USDHC4_CMD \
6796 (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6797 #define MX6Q_PAD_SD4_CMD__RAWNAND_RDN \
6798 (_MX6Q_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(NO_PAD_CTRL))
6799 #define MX6Q_PAD_SD4_CMD__UART3_TXD \
6800 (_MX6Q_PAD_SD4_CMD__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6801 #define MX6Q_PAD_SD4_CMD__UART3_RXD \
6802 (_MX6Q_PAD_SD4_CMD__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6803 #define MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \
6804 (_MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6805 #define MX6Q_PAD_SD4_CMD__GPIO_7_9 \
6806 (_MX6Q_PAD_SD4_CMD__GPIO_7_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6807 #define MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \
6808 (_MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
6810 #define MX6Q_PAD_SD4_CLK__USDHC4_CLK \
6811 (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6812 #define MX6Q_PAD_SD4_CLK__RAWNAND_WRN \
6813 (_MX6Q_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(NO_PAD_CTRL))
6814 #define MX6Q_PAD_SD4_CLK__UART3_TXD \
6815 (_MX6Q_PAD_SD4_CLK__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6816 #define MX6Q_PAD_SD4_CLK__UART3_RXD \
6817 (_MX6Q_PAD_SD4_CLK__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
6818 #define MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \
6819 (_MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6820 #define MX6Q_PAD_SD4_CLK__GPIO_7_10 \
6821 (_MX6Q_PAD_SD4_CLK__GPIO_7_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6823 #define MX6Q_PAD_NANDF_D0__RAWNAND_D0 \
6824 (_MX6Q_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6825 #define MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \
6826 (_MX6Q_PAD_NANDF_D0__USDHC1_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6827 #define MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \
6828 (_MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6829 #define MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \
6830 (_MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6831 #define MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \
6832 (_MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
6833 #define MX6Q_PAD_NANDF_D0__GPIO_2_0 \
6834 (_MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6835 #define MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \
6836 (_MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6837 #define MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \
6838 (_MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
6840 #define MX6Q_PAD_NANDF_D1__RAWNAND_D1 \
6841 (_MX6Q_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6842 #define MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \
6843 (_MX6Q_PAD_NANDF_D1__USDHC1_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6844 #define MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \
6845 (_MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6846 #define MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \
6847 (_MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6848 #define MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \
6849 (_MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
6850 #define MX6Q_PAD_NANDF_D1__GPIO_2_1 \
6851 (_MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6852 #define MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \
6853 (_MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6854 #define MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \
6855 (_MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
6857 #define MX6Q_PAD_NANDF_D2__RAWNAND_D2 \
6858 (_MX6Q_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6859 #define MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \
6860 (_MX6Q_PAD_NANDF_D2__USDHC1_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6861 #define MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \
6862 (_MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6863 #define MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \
6864 (_MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6865 #define MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \
6866 (_MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
6867 #define MX6Q_PAD_NANDF_D2__GPIO_2_2 \
6868 (_MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6869 #define MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \
6870 (_MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6871 #define MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \
6872 (_MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
6874 #define MX6Q_PAD_NANDF_D3__RAWNAND_D3 \
6875 (_MX6Q_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6876 #define MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \
6877 (_MX6Q_PAD_NANDF_D3__USDHC1_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6878 #define MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \
6879 (_MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6880 #define MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \
6881 (_MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6882 #define MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \
6883 (_MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
6884 #define MX6Q_PAD_NANDF_D3__GPIO_2_3 \
6885 (_MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6886 #define MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \
6887 (_MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6888 #define MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \
6889 (_MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
6891 #define MX6Q_PAD_NANDF_D4__RAWNAND_D4 \
6892 (_MX6Q_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6893 #define MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \
6894 (_MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6895 #define MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \
6896 (_MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6897 #define MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \
6898 (_MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
6899 #define MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \
6900 (_MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
6901 #define MX6Q_PAD_NANDF_D4__GPIO_2_4 \
6902 (_MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6903 #define MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \
6904 (_MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6905 #define MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \
6906 (_MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
6908 #define MX6Q_PAD_NANDF_D5__RAWNAND_D5 \
6909 (_MX6Q_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6910 #define MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \
6911 (_MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6912 #define MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \
6913 (_MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6914 #define MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \
6915 (_MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
6916 #define MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \
6917 (_MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
6918 #define MX6Q_PAD_NANDF_D5__GPIO_2_5 \
6919 (_MX6Q_PAD_NANDF_D5__GPIO_2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6920 #define MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \
6921 (_MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6922 #define MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \
6923 (_MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
6925 #define MX6Q_PAD_NANDF_D6__RAWNAND_D6 \
6926 (_MX6Q_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6927 #define MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \
6928 (_MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6929 #define MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \
6930 (_MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6931 #define MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \
6932 (_MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
6933 #define MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \
6934 (_MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
6935 #define MX6Q_PAD_NANDF_D6__GPIO_2_6 \
6936 (_MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6937 #define MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \
6938 (_MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6939 #define MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \
6940 (_MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
6942 #define MX6Q_PAD_NANDF_D7__RAWNAND_D7 \
6943 (_MX6Q_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6944 #define MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \
6945 (_MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6946 #define MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \
6947 (_MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6948 #define MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \
6949 (_MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
6950 #define MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \
6951 (_MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
6952 #define MX6Q_PAD_NANDF_D7__GPIO_2_7 \
6953 (_MX6Q_PAD_NANDF_D7__GPIO_2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6954 #define MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \
6955 (_MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6956 #define MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \
6957 (_MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
6959 #define MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \
6960 (_MX6Q_PAD_SD4_DAT0__RAWNAND_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6961 #define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 \
6962 (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6963 #define MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \
6964 (_MX6Q_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL))
6965 #define MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \
6966 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
6967 #define MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \
6968 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
6969 #define MX6Q_PAD_SD4_DAT0__GPIO_2_8 \
6970 (_MX6Q_PAD_SD4_DAT0__GPIO_2_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6971 #define MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \
6972 (_MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6973 #define MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \
6974 (_MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
6976 #define MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \
6977 (_MX6Q_PAD_SD4_DAT1__RAWNAND_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6978 #define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 \
6979 (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6980 #define MX6Q_PAD_SD4_DAT1__PWM3_PWMO \
6981 (_MX6Q_PAD_SD4_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
6982 #define MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \
6983 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
6984 #define MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \
6985 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
6986 #define MX6Q_PAD_SD4_DAT1__GPIO_2_9 \
6987 (_MX6Q_PAD_SD4_DAT1__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6988 #define MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \
6989 (_MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6990 #define MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \
6991 (_MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
6993 #define MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \
6994 (_MX6Q_PAD_SD4_DAT2__RAWNAND_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
6995 #define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 \
6996 (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
6997 #define MX6Q_PAD_SD4_DAT2__PWM4_PWMO \
6998 (_MX6Q_PAD_SD4_DAT2__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
6999 #define MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \
7000 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
7001 #define MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \
7002 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
7003 #define MX6Q_PAD_SD4_DAT2__GPIO_2_10 \
7004 (_MX6Q_PAD_SD4_DAT2__GPIO_2_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7005 #define MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \
7006 (_MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7007 #define MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \
7008 (_MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7010 #define MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \
7011 (_MX6Q_PAD_SD4_DAT3__RAWNAND_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7012 #define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 \
7013 (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7014 #define MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \
7015 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
7016 #define MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \
7017 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
7018 #define MX6Q_PAD_SD4_DAT3__GPIO_2_11 \
7019 (_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7020 #define MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \
7021 (_MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7022 #define MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \
7023 (_MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7025 #define MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \
7026 (_MX6Q_PAD_SD4_DAT4__RAWNAND_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
7027 #define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 \
7028 (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7029 #define MX6Q_PAD_SD4_DAT4__UART2_TXD \
7030 (_MX6Q_PAD_SD4_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7031 #define MX6Q_PAD_SD4_DAT4__UART2_RXD \
7032 (_MX6Q_PAD_SD4_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7033 #define MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \
7034 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
7035 #define MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \
7036 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
7037 #define MX6Q_PAD_SD4_DAT4__GPIO_2_12 \
7038 (_MX6Q_PAD_SD4_DAT4__GPIO_2_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
7039 #define MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \
7040 (_MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
7041 #define MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \
7042 (_MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
7044 #define MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \
7045 (_MX6Q_PAD_SD4_DAT5__RAWNAND_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
7046 #define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 \
7047 (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7048 #define MX6Q_PAD_SD4_DAT5__UART2_CTS \
7049 (_MX6Q_PAD_SD4_DAT5__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7050 #define MX6Q_PAD_SD4_DAT5__UART2_RTS \
7051 (_MX6Q_PAD_SD4_DAT5__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7052 #define MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \
7053 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
7054 #define MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \
7055 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
7056 #define MX6Q_PAD_SD4_DAT5__GPIO_2_13 \
7057 (_MX6Q_PAD_SD4_DAT5__GPIO_2_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
7058 #define MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \
7059 (_MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
7060 #define MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \
7061 (_MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
7063 #define MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \
7064 (_MX6Q_PAD_SD4_DAT6__RAWNAND_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
7065 #define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 \
7066 (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7067 #define MX6Q_PAD_SD4_DAT6__UART2_CTS \
7068 (_MX6Q_PAD_SD4_DAT6__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7069 #define MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \
7070 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
7071 #define MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \
7072 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
7073 #define MX6Q_PAD_SD4_DAT6__GPIO_2_14 \
7074 (_MX6Q_PAD_SD4_DAT6__GPIO_2_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
7075 #define MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \
7076 (_MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
7077 #define MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \
7078 (_MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
7080 #define MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \
7081 (_MX6Q_PAD_SD4_DAT7__RAWNAND_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
7082 #define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 \
7083 (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7084 #define MX6Q_PAD_SD4_DAT7__UART2_TXD \
7085 (_MX6Q_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7086 #define MX6Q_PAD_SD4_DAT7__UART2_RXD \
7087 (_MX6Q_PAD_SD4_DAT7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
7088 #define MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \
7089 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
7090 #define MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \
7091 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
7092 #define MX6Q_PAD_SD4_DAT7__GPIO_2_15 \
7093 (_MX6Q_PAD_SD4_DAT7__GPIO_2_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
7094 #define MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \
7095 (_MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
7096 #define MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \
7097 (_MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
7099 #define MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \
7100 (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7101 #define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \
7102 (_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
7103 #define MX6Q_PAD_SD1_DAT1__PWM3_PWMO \
7104 (_MX6Q_PAD_SD1_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7105 #define MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \
7106 (_MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
7107 #define MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \
7108 (_MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
7109 #define MX6Q_PAD_SD1_DAT1__GPIO_1_17 \
7110 (_MX6Q_PAD_SD1_DAT1__GPIO_1_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
7111 #define MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \
7112 (_MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
7113 #define MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \
7114 (_MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
7116 #define MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \
7117 (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7118 #define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \
7119 (_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
7120 #define MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \
7121 (_MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS | MUX_PAD_CTRL(NO_PAD_CTRL))
7122 #define MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \
7123 (_MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7124 #define MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \
7125 (_MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
7126 #define MX6Q_PAD_SD1_DAT0__GPIO_1_16 \
7127 (_MX6Q_PAD_SD1_DAT0__GPIO_1_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
7128 #define MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \
7129 (_MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7130 #define MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \
7131 (_MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
7133 #define MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \
7134 (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7135 #define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \
7136 (_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
7137 #define MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \
7138 (_MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
7139 #define MX6Q_PAD_SD1_DAT3__PWM1_PWMO \
7140 (_MX6Q_PAD_SD1_DAT3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7141 #define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \
7142 (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
7143 #define MX6Q_PAD_SD1_DAT3__GPIO_1_21 \
7144 (_MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
7145 #define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \
7146 (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
7147 #define MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \
7148 (_MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
7150 #define MX6Q_PAD_SD1_CMD__USDHC1_CMD \
7151 (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7152 #define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \
7153 (_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
7154 #define MX6Q_PAD_SD1_CMD__PWM4_PWMO \
7155 (_MX6Q_PAD_SD1_CMD__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7156 #define MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \
7157 (_MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7158 #define MX6Q_PAD_SD1_CMD__GPIO_1_18 \
7159 (_MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
7160 #define MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \
7161 (_MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
7163 #define MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \
7164 (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7165 #define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \
7166 (_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7167 #define MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \
7168 (_MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
7169 #define MX6Q_PAD_SD1_DAT2__PWM2_PWMO \
7170 (_MX6Q_PAD_SD1_DAT2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
7171 #define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \
7172 (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
7173 #define MX6Q_PAD_SD1_DAT2__GPIO_1_19 \
7174 (_MX6Q_PAD_SD1_DAT2__GPIO_1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
7175 #define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \
7176 (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
7177 #define MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \
7178 (_MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
7180 #define MX6Q_PAD_SD1_CLK__USDHC1_CLK \
7181 (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7182 #define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \
7183 (_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
7184 #define MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \
7185 (_MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
7186 #define MX6Q_PAD_SD1_CLK__GPT_CLKIN \
7187 (_MX6Q_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL))
7188 #define MX6Q_PAD_SD1_CLK__GPIO_1_20 \
7189 (_MX6Q_PAD_SD1_CLK__GPIO_1_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
7190 #define MX6Q_PAD_SD1_CLK__PHY_DTB_0 \
7191 (_MX6Q_PAD_SD1_CLK__PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
7192 #define MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \
7193 (_MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
7195 #define MX6Q_PAD_SD2_CLK__USDHC2_CLK \
7196 (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7197 #define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \
7198 (_MX6Q_PAD_SD2_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
7199 #define MX6Q_PAD_SD2_CLK__KPP_COL_5 \
7200 (_MX6Q_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
7201 #define MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \
7202 (_MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
7203 #define MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \
7204 (_MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
7205 #define MX6Q_PAD_SD2_CLK__GPIO_1_10 \
7206 (_MX6Q_PAD_SD2_CLK__GPIO_1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7207 #define MX6Q_PAD_SD2_CLK__PHY_DTB_1 \
7208 (_MX6Q_PAD_SD2_CLK__PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7209 #define MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \
7210 (_MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
7212 #define MX6Q_PAD_SD2_CMD__USDHC2_CMD \
7213 (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7214 #define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \
7215 (_MX6Q_PAD_SD2_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
7216 #define MX6Q_PAD_SD2_CMD__KPP_ROW_5 \
7217 (_MX6Q_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
7218 #define MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \
7219 (_MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
7220 #define MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \
7221 (_MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
7222 #define MX6Q_PAD_SD2_CMD__GPIO_1_11 \
7223 (_MX6Q_PAD_SD2_CMD__GPIO_1_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7225 #define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \
7226 (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
7227 #define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \
7228 (_MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
7229 #define MX6Q_PAD_SD2_DAT3__KPP_COL_6 \
7230 (_MX6Q_PAD_SD2_DAT3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
7231 #define MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \
7232 (_MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
7233 #define MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \
7234 (_MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
7235 #define MX6Q_PAD_SD2_DAT3__GPIO_1_12 \
7236 (_MX6Q_PAD_SD2_DAT3__GPIO_1_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
7237 #define MX6Q_PAD_SD2_DAT3__SJC_DONE \
7238 (_MX6Q_PAD_SD2_DAT3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL))
7239 #define MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \
7240 (_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 | MUX_PAD_CTRL(NO_PAD_CTRL))