1 #ifndef __MACH_MX25_H__
2 #define __MACH_MX25_H__
4 #define MX25_AIPS1_BASE_ADDR 0x43f00000
5 #define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000
6 #define MX25_AIPS1_SIZE SZ_1M
7 #define MX25_AIPS2_BASE_ADDR 0x53f00000
8 #define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000
9 #define MX25_AIPS2_SIZE SZ_1M
10 #define MX25_AVIC_BASE_ADDR 0x68000000
11 #define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000
12 #define MX25_AVIC_SIZE SZ_1M
14 #define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
15 #define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
16 #define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
17 #define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
18 #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
20 #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
21 #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
22 #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
24 #define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000)
25 #define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000)
26 #define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
27 #define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
29 #define MX25_IO_ADDRESS(x) ( \
30 IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \
31 IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \
32 IMX_IO_ADDRESS(x, MX25_AVIC))
34 #define MX25_AIPS1_IO_ADDRESS(x) \
35 (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
37 #define MX25_UART1_BASE_ADDR 0x43f90000
38 #define MX25_UART2_BASE_ADDR 0x43f94000
39 #define MX25_AUDMUX_BASE_ADDR 0x43fb0000
40 #define MX25_UART3_BASE_ADDR 0x5000c000
41 #define MX25_UART4_BASE_ADDR 0x50008000
42 #define MX25_UART5_BASE_ADDR 0x5002c000
44 #define MX25_CSPI3_BASE_ADDR 0x50004000
45 #define MX25_CSPI2_BASE_ADDR 0x50010000
46 #define MX25_FEC_BASE_ADDR 0x50038000
47 #define MX25_SSI2_BASE_ADDR 0x50014000
48 #define MX25_SSI1_BASE_ADDR 0x50034000
49 #define MX25_NFC_BASE_ADDR 0xbb000000
50 #define MX25_DRYICE_BASE_ADDR 0x53ffc000
51 #define MX25_LCDC_BASE_ADDR 0x53fbc000
52 #define MX25_KPP_BASE_ADDR 0x43fa8000
53 #define MX25_OTG_BASE_ADDR 0x53ff4000
54 #define MX25_CSI_BASE_ADDR 0x53ff8000
56 #define MX25_INT_CSPI3 0
57 #define MX25_INT_I2C1 3
58 #define MX25_INT_I2C2 4
59 #define MX25_INT_UART4 5
60 #define MX25_INT_I2C3 10
61 #define MX25_INT_SSI2 11
62 #define MX25_INT_SSI1 12
63 #define MX25_INT_CSPI2 13
64 #define MX25_INT_CSPI1 14
65 #define MX25_INT_CSI 17
66 #define MX25_INT_UART3 18
67 #define MX25_INT_KPP 24
68 #define MX25_INT_DRYICE 25
69 #define MX25_INT_UART2 32
70 #define MX25_INT_NANDFC 33
71 #define MX25_INT_LCDC 39
72 #define MX25_INT_UART5 40
73 #define MX25_INT_UART1 45
74 #define MX25_INT_FEC 57
76 #endif /* ifndef __MACH_MX25_H__ */