2 * Copyright 2004-2007, 2011 Freescale Semiconductor, Inc.
3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #ifndef __ASM_ARCH_MXC_H__
21 #define __ASM_ARCH_MXC_H__
23 #include <linux/types.h>
25 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
26 #error "Do not include directly."
30 #define MXC_CPU_MX21 21
31 #define MXC_CPU_MX25 25
32 #define MXC_CPU_MX27 27
33 #define MXC_CPU_MX31 31
34 #define MXC_CPU_MX35 35
35 #define MXC_CPU_MX37 37
36 #define MXC_CPU_MX50 50
37 #define MXC_CPU_MX51 51
38 #define MXC_CPU_MX53 53
40 #define IMX_CHIP_REVISION_1_0 0x10
41 #define IMX_CHIP_REVISION_1_1 0x11
42 #define IMX_CHIP_REVISION_1_2 0x12
43 #define IMX_CHIP_REVISION_1_3 0x13
44 #define IMX_CHIP_REVISION_2_0 0x20
45 #define IMX_CHIP_REVISION_2_1 0x21
46 #define IMX_CHIP_REVISION_2_2 0x22
47 #define IMX_CHIP_REVISION_2_3 0x23
48 #define IMX_CHIP_REVISION_3_0 0x30
49 #define IMX_CHIP_REVISION_3_1 0x31
50 #define IMX_CHIP_REVISION_3_2 0x32
51 #define IMX_CHIP_REVISION_3_3 0x33
52 #define IMX_CHIP_REVISION_UNKNOWN 0xff
54 #define IMX_CHIP_REVISION_1_0_STRING "1.0"
55 #define IMX_CHIP_REVISION_1_1_STRING "1.1"
56 #define IMX_CHIP_REVISION_1_2_STRING "1.2"
57 #define IMX_CHIP_REVISION_1_3_STRING "1.3"
58 #define IMX_CHIP_REVISION_2_0_STRING "2.0"
59 #define IMX_CHIP_REVISION_2_1_STRING "2.1"
60 #define IMX_CHIP_REVISION_2_2_STRING "2.2"
61 #define IMX_CHIP_REVISION_2_3_STRING "2.3"
62 #define IMX_CHIP_REVISION_3_0_STRING "3.0"
63 #define IMX_CHIP_REVISION_3_1_STRING "3.1"
64 #define IMX_CHIP_REVISION_3_2_STRING "3.2"
65 #define IMX_CHIP_REVISION_3_3_STRING "3.3"
66 #define IMX_CHIP_REVISION_UNKNOWN_STRING "unknown"
67 #define IMX_BOARD_REV_1 0x000
68 #define IMX_BOARD_REV_2 0x100
69 #define IMX_BOARD_REV_3 0x200
70 #define IMX_BOARD_REV_4 0x300
73 extern unsigned int system_rev;
74 #define board_is_rev(rev) (((system_rev & 0x0F00) == rev) ? 1 : 0)
75 #define imx_cpu_ver() (system_rev & 0xFF)
78 #ifdef CONFIG_ARCH_MX5
79 #define board_is_mx53_loco_mc34708() (cpu_is_mx53() && \
80 (board_is_rev(IMX_BOARD_REV_2) || board_is_rev(IMX_BOARD_REV_4)))
81 #define board_is_mx53_arm2() (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_2))
82 #define board_is_mx53_evk_a() (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_1))
83 #define board_is_mx53_evk_b() (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_3))
86 #ifdef CONFIG_SOC_IMX6Q
87 #define board_is_mx6q_arm2() (cpu_is_mx6q() && \
88 board_is_rev(IMX_BOARD_REV_1))
89 #define board_is_mx6q_sabre_lite() (cpu_is_mx6q() && \
90 board_is_rev(IMX_BOARD_REV_2))
91 #define board_is_mx6q_sabre_auto() (cpu_is_mx6q() && \
92 board_is_rev(IMX_BOARD_REV_3))
96 extern unsigned int __mxc_cpu_type;
99 #ifdef CONFIG_ARCH_MX1
102 # define mxc_cpu_type __mxc_cpu_type
104 # define mxc_cpu_type MXC_CPU_MX1
106 # define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1)
108 # define cpu_is_mx1() (0)
111 #ifdef CONFIG_MACH_MX21
114 # define mxc_cpu_type __mxc_cpu_type
116 # define mxc_cpu_type MXC_CPU_MX21
118 # define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21)
120 # define cpu_is_mx21() (0)
123 #ifdef CONFIG_ARCH_MX25
126 # define mxc_cpu_type __mxc_cpu_type
128 # define mxc_cpu_type MXC_CPU_MX25
130 # define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25)
132 # define cpu_is_mx25() (0)
135 #ifdef CONFIG_MACH_MX27
138 # define mxc_cpu_type __mxc_cpu_type
140 # define mxc_cpu_type MXC_CPU_MX27
142 # define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27)
144 # define cpu_is_mx27() (0)
147 #ifdef CONFIG_SOC_IMX31
150 # define mxc_cpu_type __mxc_cpu_type
152 # define mxc_cpu_type MXC_CPU_MX31
154 # define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31)
156 # define cpu_is_mx31() (0)
159 # define cpu_is_mx32() (0)
161 #ifdef CONFIG_SOC_IMX35
164 # define mxc_cpu_type __mxc_cpu_type
166 # define mxc_cpu_type MXC_CPU_MX35
168 # define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35)
170 # define cpu_is_mx35() (0)
173 #ifdef CONFIG_SOC_IMX37
176 # define mxc_cpu_type __mxc_cpu_type
178 # define mxc_cpu_type MXC_CPU_MX37
180 # define cpu_is_mx37() (mxc_cpu_type == MXC_CPU_MX37)
182 # define cpu_is_mx37() (0)
185 #ifdef CONFIG_SOC_IMX50
188 # define mxc_cpu_type __mxc_cpu_type
190 # define mxc_cpu_type MXC_CPU_MX50
192 # define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50)
194 # define cpu_is_mx50() (0)
197 #ifdef CONFIG_SOC_IMX51
200 # define mxc_cpu_type __mxc_cpu_type
202 # define mxc_cpu_type MXC_CPU_MX51
204 # define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
206 # define cpu_is_mx51() (0)
209 #ifdef CONFIG_SOC_IMX53
212 # define mxc_cpu_type __mxc_cpu_type
214 # define mxc_cpu_type MXC_CPU_MX53
216 # define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53)
218 # define cpu_is_mx53() (0)
223 #ifdef CONFIG_SOC_IMX6Q
224 #define cpu_is_mx6q() (1)
226 #define cpu_is_mx6q() (0)
242 enum mxc_cpu_pwr_mode {
243 WAIT_CLOCKED, /* wfi only */
244 WAIT_UNCLOCKED, /* WAIT */
245 WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
246 STOP_POWER_ON, /* just STOP */
247 STOP_POWER_OFF, /* STOP + SRPG */
248 ARM_POWER_OFF, /* STOP + SRPG + ARM power off */
251 int tzic_enable_wake(int is_idle);
253 extern void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
254 extern int tzic_enable_wake(int is_idle);
257 #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
258 /* These are deprecated, use mx[23][157]_setup_weimcs instead. */
259 #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10))
260 #define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4))
261 #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8))
264 #define cpu_is_mx5() (cpu_is_mx51() || cpu_is_mx53() || cpu_is_mx50())
265 #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
266 #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
268 #define MXC_PGCR_PCR 1
269 #define MXC_SRPGCR_PCR 1
270 #define MXC_EMPGCR_PCR 1
271 #define MXC_PGSR_PSR 1
272 #endif /* __ASM_ARCH_MXC_H__ */