2 * linux/arch/arm/plat-nomadik/timer.c
4 * Copyright (C) 2008 STMicroelectronics
5 * Copyright (C) 2010 Alessandro Rubini
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2, as
9 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
15 #include <linux/clockchips.h>
16 #include <linux/clk.h>
17 #include <linux/jiffies.h>
18 #include <linux/err.h>
19 #include <asm/mach/time.h>
23 void __iomem *mtu_base; /* ssigned by machine code */
26 * Kernel assumes that sched_clock can be called early
27 * but the MTU may not yet be initialized.
29 static cycle_t nmdk_read_timer_dummy(struct clocksource *cs)
34 /* clocksource: MTU decrements, so we negate the value being read. */
35 static cycle_t nmdk_read_timer(struct clocksource *cs)
37 return -readl(mtu_base + MTU_VAL(0));
40 static struct clocksource nmdk_clksrc = {
43 .read = nmdk_read_timer_dummy,
44 .mask = CLOCKSOURCE_MASK(32),
45 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
49 * Override the global weak sched_clock symbol with this
50 * local implementation which uses the clocksource to get some
51 * better resolution when scheduling the kernel. We accept that
52 * this wraps around for now, since it is just a relative time
53 * stamp. (Inspired by OMAP implementation.)
55 unsigned long long notrace sched_clock(void)
57 return clocksource_cyc2ns(nmdk_clksrc.read(
63 /* Clockevent device: use one-shot mode */
64 static void nmdk_clkevt_mode(enum clock_event_mode mode,
65 struct clock_event_device *dev)
70 case CLOCK_EVT_MODE_PERIODIC:
71 pr_err("%s: periodic mode not supported\n", __func__);
73 case CLOCK_EVT_MODE_ONESHOT:
74 /* Load highest value, enable device, enable interrupts */
75 cr = readl(mtu_base + MTU_CR(1));
76 writel(0, mtu_base + MTU_LR(1));
77 writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1));
78 writel(1 << 1, mtu_base + MTU_IMSC);
80 case CLOCK_EVT_MODE_SHUTDOWN:
81 case CLOCK_EVT_MODE_UNUSED:
83 writel(0, mtu_base + MTU_IMSC);
85 cr = readl(mtu_base + MTU_CR(1));
87 writel(cr, mtu_base + MTU_CR(1));
88 /* load some high default value */
89 writel(0xffffffff, mtu_base + MTU_LR(1));
91 case CLOCK_EVT_MODE_RESUME:
96 static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
98 /* writing the value has immediate effect */
99 writel(evt, mtu_base + MTU_LR(1));
103 static struct clock_event_device nmdk_clkevt = {
105 .features = CLOCK_EVT_FEAT_ONESHOT,
107 .set_mode = nmdk_clkevt_mode,
108 .set_next_event = nmdk_clkevt_next,
112 * IRQ Handler for timer 1 of the MTU block.
114 static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
116 struct clock_event_device *evdev = dev_id;
118 writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
119 evdev->event_handler(evdev);
123 static struct irqaction nmdk_timer_irq = {
124 .name = "Nomadik Timer Tick",
125 .flags = IRQF_DISABLED | IRQF_TIMER,
126 .handler = nmdk_timer_interrupt,
127 .dev_id = &nmdk_clkevt,
130 void __init nmdk_timer_init(void)
134 u32 cr = MTU_CRn_32BITS;
136 clk0 = clk_get_sys("mtu0", NULL);
137 BUG_ON(IS_ERR(clk0));
142 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
144 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
145 * At 32 MHz, the timer (with 32 bit counter) can be programmed
146 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
147 * with 16 gives too low timer resolution.
149 rate = clk_get_rate(clk0);
150 if (rate > 32000000) {
152 cr |= MTU_CRn_PRESCALE_16;
154 cr |= MTU_CRn_PRESCALE_1;
156 clocksource_calc_mult_shift(&nmdk_clksrc, rate, MTU_MIN_RANGE);
158 /* Timer 0 is the free running clocksource */
159 writel(cr, mtu_base + MTU_CR(0));
160 writel(0, mtu_base + MTU_LR(0));
161 writel(0, mtu_base + MTU_BGLR(0));
162 writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
164 /* Now the scheduling clock is ready */
165 nmdk_clksrc.read = nmdk_read_timer;
167 if (clocksource_register(&nmdk_clksrc))
168 pr_err("timer: failed to initialize clock source %s\n",
171 /* Timer 1 is used for events */
173 clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
175 writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
177 nmdk_clkevt.max_delta_ns =
178 clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
179 nmdk_clkevt.min_delta_ns =
180 clockevent_delta2ns(0x00000002, &nmdk_clkevt);
181 nmdk_clkevt.cpumask = cpumask_of(0);
183 /* Register irq and clockevents */
184 setup_irq(IRQ_MTU0, &nmdk_timer_irq);
185 clockevents_register_device(&nmdk_clkevt);