2 * linux/arch/arm/plat-nomadik/timer.c
4 * Copyright (C) 2008 STMicroelectronics
5 * Copyright (C) 2010 Alessandro Rubini
6 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2, as
10 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
16 #include <linux/clockchips.h>
17 #include <linux/clk.h>
18 #include <linux/jiffies.h>
19 #include <linux/err.h>
20 #include <linux/cnt32_to_63.h>
21 #include <linux/timer.h>
22 #include <linux/sched.h>
23 #include <asm/mach/time.h>
27 void __iomem *mtu_base; /* Assigned by machine code */
30 * Kernel assumes that sched_clock can be called early
31 * but the MTU may not yet be initialized.
33 static cycle_t nmdk_read_timer_dummy(struct clocksource *cs)
38 /* clocksource: MTU decrements, so we negate the value being read. */
39 static cycle_t nmdk_read_timer(struct clocksource *cs)
41 return -readl(mtu_base + MTU_VAL(0));
44 static struct clocksource nmdk_clksrc = {
47 .read = nmdk_read_timer_dummy,
48 .mask = CLOCKSOURCE_MASK(32),
49 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
53 * Override the global weak sched_clock symbol with this
54 * local implementation which uses the clocksource to get some
55 * better resolution when scheduling the kernel.
57 * Because the hardware timer period may be quite short
58 * (32.3 secs on the 133 MHz MTU timer selection on ux500)
59 * and because cnt32_to_63() needs to be called at least once per
60 * half period to work properly, a kernel keepwarm() timer is set up
61 * to ensure this requirement is always met.
63 * Also the sched_clock timer will wrap around at some point,
64 * here we set it to run continously for a year.
66 #define SCHED_CLOCK_MIN_WRAP 3600*24*365
67 static struct timer_list cnt32_to_63_keepwarm_timer;
68 static u32 sched_mult;
69 static u32 sched_shift;
71 unsigned long long notrace sched_clock(void)
75 if (unlikely(!mtu_base))
78 cycles = cnt32_to_63(-readl(mtu_base + MTU_VAL(0)));
80 * sched_mult is guaranteed to be even so will
83 return (cycles * sched_mult) >> sched_shift;
86 /* Just kick sched_clock every so often */
87 static void cnt32_to_63_keepwarm(unsigned long data)
89 mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data));
94 * Set up a timer to keep sched_clock():s 32_to_63 algorithm warm
95 * once in half a 32bit timer wrap interval.
97 static void __init nmdk_sched_clock_init(unsigned long rate)
103 /* Find the apropriate mult and shift factors */
104 clocks_calc_mult_shift(&sched_mult, &sched_shift,
105 rate, NSEC_PER_SEC, SCHED_CLOCK_MIN_WRAP);
106 /* We need to multiply by an even number to get rid of bit 63 */
110 /* Let's see what we get, take max counter and scale it */
111 days = (0xFFFFFFFFFFFFFFFFLLU * sched_mult) >> sched_shift;
112 do_div(days, NSEC_PER_SEC);
113 do_div(days, (3600*24));
115 pr_info("sched_clock: using %d bits @ %lu Hz wrap in %lu days\n",
116 (64 - sched_shift), rate, (unsigned long) days);
119 * Program a timer to kick us at half 32bit wraparound
120 * Formula: seconds per wrap = (2^32) / f
122 v = 0xFFFFFFFFUL / rate;
123 /* We want half of the wrap time to keep cnt32_to_63 warm */
125 pr_debug("sched_clock: prescaled timer rate: %lu Hz, "
126 "initialize keepwarm timer every %d seconds\n", rate, v);
127 /* Convert seconds to jiffies */
128 delta = msecs_to_jiffies(v*1000);
129 setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, delta);
130 mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + delta));
133 /* Clockevent device: use one-shot mode */
134 static void nmdk_clkevt_mode(enum clock_event_mode mode,
135 struct clock_event_device *dev)
140 case CLOCK_EVT_MODE_PERIODIC:
141 pr_err("%s: periodic mode not supported\n", __func__);
143 case CLOCK_EVT_MODE_ONESHOT:
144 /* Load highest value, enable device, enable interrupts */
145 cr = readl(mtu_base + MTU_CR(1));
146 writel(0, mtu_base + MTU_LR(1));
147 writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1));
148 writel(1 << 1, mtu_base + MTU_IMSC);
150 case CLOCK_EVT_MODE_SHUTDOWN:
151 case CLOCK_EVT_MODE_UNUSED:
153 writel(0, mtu_base + MTU_IMSC);
155 cr = readl(mtu_base + MTU_CR(1));
157 writel(cr, mtu_base + MTU_CR(1));
158 /* load some high default value */
159 writel(0xffffffff, mtu_base + MTU_LR(1));
161 case CLOCK_EVT_MODE_RESUME:
166 static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
168 /* writing the value has immediate effect */
169 writel(evt, mtu_base + MTU_LR(1));
173 static struct clock_event_device nmdk_clkevt = {
175 .features = CLOCK_EVT_FEAT_ONESHOT,
177 .set_mode = nmdk_clkevt_mode,
178 .set_next_event = nmdk_clkevt_next,
182 * IRQ Handler for timer 1 of the MTU block.
184 static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
186 struct clock_event_device *evdev = dev_id;
188 writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
189 evdev->event_handler(evdev);
193 static struct irqaction nmdk_timer_irq = {
194 .name = "Nomadik Timer Tick",
195 .flags = IRQF_DISABLED | IRQF_TIMER,
196 .handler = nmdk_timer_interrupt,
197 .dev_id = &nmdk_clkevt,
200 void __init nmdk_timer_init(void)
204 u32 cr = MTU_CRn_32BITS;
206 clk0 = clk_get_sys("mtu0", NULL);
207 BUG_ON(IS_ERR(clk0));
212 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
214 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
215 * At 32 MHz, the timer (with 32 bit counter) can be programmed
216 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
217 * with 16 gives too low timer resolution.
219 rate = clk_get_rate(clk0);
220 if (rate > 32000000) {
222 cr |= MTU_CRn_PRESCALE_16;
224 cr |= MTU_CRn_PRESCALE_1;
227 /* Timer 0 is the free running clocksource */
228 writel(cr, mtu_base + MTU_CR(0));
229 writel(0, mtu_base + MTU_LR(0));
230 writel(0, mtu_base + MTU_BGLR(0));
231 writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
233 /* Now the clock source is ready */
234 nmdk_clksrc.read = nmdk_read_timer;
236 if (clocksource_register_hz(&nmdk_clksrc, rate))
237 pr_err("timer: failed to initialize clock source %s\n",
240 nmdk_sched_clock_init(rate);
242 /* Timer 1 is used for events */
244 clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
246 writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
248 nmdk_clkevt.max_delta_ns =
249 clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
250 nmdk_clkevt.min_delta_ns =
251 clockevent_delta2ns(0x00000002, &nmdk_clkevt);
252 nmdk_clkevt.cpumask = cpumask_of(0);
254 /* Register irq and clockevents */
255 setup_irq(IRQ_MTU0, &nmdk_timer_irq);
256 clockevents_register_device(&nmdk_clkevt);