2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Support functions for the OMAP internal DMA channels.
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <linux/omap-dma.h>
42 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
43 * channels that an instance of the SDMA IP block can support. Used
44 * to size arrays. (The actual maximum on a particular SoC may be less
45 * than this -- for example, OMAP1 SDMA instances only support 17 logical
48 #define MAX_LOGICAL_DMA_CH_COUNT 32
52 #ifndef CONFIG_ARCH_OMAP1
53 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
54 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
57 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
60 #define OMAP_DMA_ACTIVE 0x01
61 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
63 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
65 static struct omap_system_dma_plat_info *p;
66 static struct omap_dma_dev_attr *d;
68 static int enable_1510_mode;
71 static struct omap_dma_global_context_registers {
73 u32 dma_ocp_sysconfig;
75 } omap_dma_global_context;
77 struct dma_link_info {
79 int no_of_lchs_linked;
90 static struct dma_link_info *dma_linked_lch;
92 #ifndef CONFIG_ARCH_OMAP1
94 /* Chain handling macros */
95 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
97 dma_linked_lch[chain_id].q_head = \
98 dma_linked_lch[chain_id].q_tail = \
99 dma_linked_lch[chain_id].q_count = 0; \
101 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
102 (dma_linked_lch[chain_id].no_of_lchs_linked == \
103 dma_linked_lch[chain_id].q_count)
104 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
106 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
107 dma_linked_lch[chain_id].q_count) \
109 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
110 (0 == dma_linked_lch[chain_id].q_count)
111 #define __OMAP_DMA_CHAIN_INCQ(end) \
112 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
113 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
115 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
116 dma_linked_lch[chain_id].q_count--; \
119 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
121 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
122 dma_linked_lch[chain_id].q_count++; \
126 static int dma_lch_count;
127 static int dma_chan_count;
128 static int omap_dma_reserve_channels;
130 static spinlock_t dma_chan_lock;
131 static struct omap_dma_lch *dma_chan;
133 static inline void disable_lnk(int lch);
134 static void omap_disable_channel_irq(int lch);
135 static inline void omap_enable_channel_irq(int lch);
137 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
140 #ifdef CONFIG_ARCH_OMAP15XX
141 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
142 static int omap_dma_in_1510_mode(void)
144 return enable_1510_mode;
147 #define omap_dma_in_1510_mode() 0
150 #ifdef CONFIG_ARCH_OMAP1
151 static inline int get_gdma_dev(int req)
153 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
154 int shift = ((req - 1) % 5) * 6;
156 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
159 static inline void set_gdma_dev(int req, int dev)
161 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
162 int shift = ((req - 1) % 5) * 6;
166 l &= ~(0x3f << shift);
167 l |= (dev - 1) << shift;
171 #define set_gdma_dev(req, dev) do {} while (0)
172 #define omap_readl(reg) 0
173 #define omap_writel(val, reg) do {} while (0)
176 #ifdef CONFIG_ARCH_OMAP1
177 void omap_set_dma_priority(int lch, int dst_port, int priority)
184 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
185 reg = OMAP_TC_OCPT1_PRIOR;
187 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
188 reg = OMAP_TC_OCPT2_PRIOR;
190 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
191 reg = OMAP_TC_EMIFF_PRIOR;
193 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
194 reg = OMAP_TC_EMIFS_PRIOR;
202 l |= (priority & 0xf) << 8;
208 #ifdef CONFIG_ARCH_OMAP2PLUS
209 void omap_set_dma_priority(int lch, int dst_port, int priority)
213 ccr = p->dma_read(CCR, lch);
218 p->dma_write(ccr, CCR, lch);
221 EXPORT_SYMBOL(omap_set_dma_priority);
223 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
224 int frame_count, int sync_mode,
225 int dma_trigger, int src_or_dst_synch)
229 l = p->dma_read(CSDP, lch);
232 p->dma_write(l, CSDP, lch);
237 ccr = p->dma_read(CCR, lch);
239 if (sync_mode == OMAP_DMA_SYNC_FRAME)
241 p->dma_write(ccr, CCR, lch);
243 ccr = p->dma_read(CCR2, lch);
245 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
247 p->dma_write(ccr, CCR2, lch);
250 if (dma_omap2plus() && dma_trigger) {
253 val = p->dma_read(CCR, lch);
255 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
256 val &= ~((1 << 23) | (3 << 19) | 0x1f);
257 val |= (dma_trigger & ~0x1f) << 14;
258 val |= dma_trigger & 0x1f;
260 if (sync_mode & OMAP_DMA_SYNC_FRAME)
265 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
270 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
271 val &= ~(1 << 24); /* dest synch */
272 val |= (1 << 23); /* Prefetch */
273 } else if (src_or_dst_synch) {
274 val |= 1 << 24; /* source synch */
276 val &= ~(1 << 24); /* dest synch */
278 p->dma_write(val, CCR, lch);
281 p->dma_write(elem_count, CEN, lch);
282 p->dma_write(frame_count, CFN, lch);
284 EXPORT_SYMBOL(omap_set_dma_transfer_params);
286 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
288 BUG_ON(omap_dma_in_1510_mode());
293 w = p->dma_read(CCR2, lch);
297 case OMAP_DMA_CONSTANT_FILL:
300 case OMAP_DMA_TRANSPARENT_COPY:
303 case OMAP_DMA_COLOR_DIS:
308 p->dma_write(w, CCR2, lch);
310 w = p->dma_read(LCH_CTRL, lch);
312 /* Default is channel type 2D */
314 p->dma_write(color, COLOR, lch);
315 w |= 1; /* Channel type G */
317 p->dma_write(w, LCH_CTRL, lch);
320 if (dma_omap2plus()) {
323 val = p->dma_read(CCR, lch);
324 val &= ~((1 << 17) | (1 << 16));
327 case OMAP_DMA_CONSTANT_FILL:
330 case OMAP_DMA_TRANSPARENT_COPY:
333 case OMAP_DMA_COLOR_DIS:
338 p->dma_write(val, CCR, lch);
341 p->dma_write(color, COLOR, lch);
344 EXPORT_SYMBOL(omap_set_dma_color_mode);
346 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
348 if (dma_omap2plus()) {
351 csdp = p->dma_read(CSDP, lch);
352 csdp &= ~(0x3 << 16);
353 csdp |= (mode << 16);
354 p->dma_write(csdp, CSDP, lch);
357 EXPORT_SYMBOL(omap_set_dma_write_mode);
359 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
361 if (dma_omap1() && !dma_omap15xx()) {
364 l = p->dma_read(LCH_CTRL, lch);
367 p->dma_write(l, LCH_CTRL, lch);
370 EXPORT_SYMBOL(omap_set_dma_channel_mode);
372 /* Note that src_port is only for omap1 */
373 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
374 unsigned long src_start,
375 int src_ei, int src_fi)
382 w = p->dma_read(CSDP, lch);
385 p->dma_write(w, CSDP, lch);
388 l = p->dma_read(CCR, lch);
390 l |= src_amode << 12;
391 p->dma_write(l, CCR, lch);
393 p->dma_write(src_start, CSSA, lch);
395 p->dma_write(src_ei, CSEI, lch);
396 p->dma_write(src_fi, CSFI, lch);
398 EXPORT_SYMBOL(omap_set_dma_src_params);
400 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
402 omap_set_dma_transfer_params(lch, params->data_type,
403 params->elem_count, params->frame_count,
404 params->sync_mode, params->trigger,
405 params->src_or_dst_synch);
406 omap_set_dma_src_params(lch, params->src_port,
407 params->src_amode, params->src_start,
408 params->src_ei, params->src_fi);
410 omap_set_dma_dest_params(lch, params->dst_port,
411 params->dst_amode, params->dst_start,
412 params->dst_ei, params->dst_fi);
413 if (params->read_prio || params->write_prio)
414 omap_dma_set_prio_lch(lch, params->read_prio,
417 EXPORT_SYMBOL(omap_set_dma_params);
419 void omap_set_dma_src_index(int lch, int eidx, int fidx)
424 p->dma_write(eidx, CSEI, lch);
425 p->dma_write(fidx, CSFI, lch);
427 EXPORT_SYMBOL(omap_set_dma_src_index);
429 void omap_set_dma_src_data_pack(int lch, int enable)
433 l = p->dma_read(CSDP, lch);
437 p->dma_write(l, CSDP, lch);
439 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
441 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
443 unsigned int burst = 0;
446 l = p->dma_read(CSDP, lch);
449 switch (burst_mode) {
450 case OMAP_DMA_DATA_BURST_DIS:
452 case OMAP_DMA_DATA_BURST_4:
458 case OMAP_DMA_DATA_BURST_8:
459 if (dma_omap2plus()) {
464 * not supported by current hardware on OMAP1
468 case OMAP_DMA_DATA_BURST_16:
469 if (dma_omap2plus()) {
474 * OMAP1 don't support burst 16
482 p->dma_write(l, CSDP, lch);
484 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
486 /* Note that dest_port is only for OMAP1 */
487 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
488 unsigned long dest_start,
489 int dst_ei, int dst_fi)
494 l = p->dma_read(CSDP, lch);
497 p->dma_write(l, CSDP, lch);
500 l = p->dma_read(CCR, lch);
502 l |= dest_amode << 14;
503 p->dma_write(l, CCR, lch);
505 p->dma_write(dest_start, CDSA, lch);
507 p->dma_write(dst_ei, CDEI, lch);
508 p->dma_write(dst_fi, CDFI, lch);
510 EXPORT_SYMBOL(omap_set_dma_dest_params);
512 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
517 p->dma_write(eidx, CDEI, lch);
518 p->dma_write(fidx, CDFI, lch);
520 EXPORT_SYMBOL(omap_set_dma_dest_index);
522 void omap_set_dma_dest_data_pack(int lch, int enable)
526 l = p->dma_read(CSDP, lch);
530 p->dma_write(l, CSDP, lch);
532 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
534 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
536 unsigned int burst = 0;
539 l = p->dma_read(CSDP, lch);
542 switch (burst_mode) {
543 case OMAP_DMA_DATA_BURST_DIS:
545 case OMAP_DMA_DATA_BURST_4:
551 case OMAP_DMA_DATA_BURST_8:
557 case OMAP_DMA_DATA_BURST_16:
558 if (dma_omap2plus()) {
563 * OMAP1 don't support burst 16
567 printk(KERN_ERR "Invalid DMA burst mode\n");
572 p->dma_write(l, CSDP, lch);
574 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
576 static inline void omap_enable_channel_irq(int lch)
580 p->dma_read(CSR, lch);
582 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
584 /* Enable some nice interrupts. */
585 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
588 static inline void omap_disable_channel_irq(int lch)
590 /* disable channel interrupts */
591 p->dma_write(0, CICR, lch);
594 p->dma_read(CSR, lch);
596 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
599 void omap_enable_dma_irq(int lch, u16 bits)
601 dma_chan[lch].enabled_irqs |= bits;
603 EXPORT_SYMBOL(omap_enable_dma_irq);
605 void omap_disable_dma_irq(int lch, u16 bits)
607 dma_chan[lch].enabled_irqs &= ~bits;
609 EXPORT_SYMBOL(omap_disable_dma_irq);
611 static inline void enable_lnk(int lch)
615 l = p->dma_read(CLNK_CTRL, lch);
620 /* Set the ENABLE_LNK bits */
621 if (dma_chan[lch].next_lch != -1)
622 l = dma_chan[lch].next_lch | (1 << 15);
624 #ifndef CONFIG_ARCH_OMAP1
626 if (dma_chan[lch].next_linked_ch != -1)
627 l = dma_chan[lch].next_linked_ch | (1 << 15);
630 p->dma_write(l, CLNK_CTRL, lch);
633 static inline void disable_lnk(int lch)
637 l = p->dma_read(CLNK_CTRL, lch);
639 /* Disable interrupts */
640 omap_disable_channel_irq(lch);
643 /* Set the STOP_LNK bit */
647 if (dma_omap2plus()) {
648 /* Clear the ENABLE_LNK bit */
652 p->dma_write(l, CLNK_CTRL, lch);
653 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
656 static inline void omap2_enable_irq_lch(int lch)
664 spin_lock_irqsave(&dma_chan_lock, flags);
665 /* clear IRQ STATUS */
666 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
667 /* Enable interrupt */
668 val = p->dma_read(IRQENABLE_L0, lch);
670 p->dma_write(val, IRQENABLE_L0, lch);
671 spin_unlock_irqrestore(&dma_chan_lock, flags);
674 static inline void omap2_disable_irq_lch(int lch)
682 spin_lock_irqsave(&dma_chan_lock, flags);
683 /* Disable interrupt */
684 val = p->dma_read(IRQENABLE_L0, lch);
686 p->dma_write(val, IRQENABLE_L0, lch);
687 /* clear IRQ STATUS */
688 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
689 spin_unlock_irqrestore(&dma_chan_lock, flags);
692 int omap_request_dma(int dev_id, const char *dev_name,
693 void (*callback)(int lch, u16 ch_status, void *data),
694 void *data, int *dma_ch_out)
696 int ch, free_ch = -1;
698 struct omap_dma_lch *chan;
700 spin_lock_irqsave(&dma_chan_lock, flags);
701 for (ch = 0; ch < dma_chan_count; ch++) {
702 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
709 spin_unlock_irqrestore(&dma_chan_lock, flags);
712 chan = dma_chan + free_ch;
713 chan->dev_id = dev_id;
715 if (p->clear_lch_regs)
716 p->clear_lch_regs(free_ch);
719 omap_clear_dma(free_ch);
721 spin_unlock_irqrestore(&dma_chan_lock, flags);
723 chan->dev_name = dev_name;
724 chan->callback = callback;
728 #ifndef CONFIG_ARCH_OMAP1
729 if (dma_omap2plus()) {
731 chan->next_linked_ch = -1;
735 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
738 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
739 else if (dma_omap2plus())
740 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
741 OMAP2_DMA_TRANS_ERR_IRQ;
743 if (dma_omap16xx()) {
744 /* If the sync device is set, configure it dynamically. */
746 set_gdma_dev(free_ch + 1, dev_id);
747 dev_id = free_ch + 1;
750 * Disable the 1510 compatibility mode and set the sync device
753 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
754 } else if (dma_omap1()) {
755 p->dma_write(dev_id, CCR, free_ch);
758 if (dma_omap2plus()) {
759 omap_enable_channel_irq(free_ch);
760 omap2_enable_irq_lch(free_ch);
763 *dma_ch_out = free_ch;
767 EXPORT_SYMBOL(omap_request_dma);
769 void omap_free_dma(int lch)
773 if (dma_chan[lch].dev_id == -1) {
774 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
779 /* Disable interrupt for logical channel */
781 omap2_disable_irq_lch(lch);
783 /* Disable all DMA interrupts for the channel. */
784 omap_disable_channel_irq(lch);
786 /* Make sure the DMA transfer is stopped. */
787 p->dma_write(0, CCR, lch);
789 /* Clear registers */
793 spin_lock_irqsave(&dma_chan_lock, flags);
794 dma_chan[lch].dev_id = -1;
795 dma_chan[lch].next_lch = -1;
796 dma_chan[lch].callback = NULL;
797 spin_unlock_irqrestore(&dma_chan_lock, flags);
799 EXPORT_SYMBOL(omap_free_dma);
802 * @brief omap_dma_set_global_params : Set global priority settings for dma
805 * @param max_fifo_depth
806 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
807 * DMA_THREAD_RESERVE_ONET
808 * DMA_THREAD_RESERVE_TWOT
809 * DMA_THREAD_RESERVE_THREET
812 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
817 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
821 if (max_fifo_depth == 0)
826 reg = 0xff & max_fifo_depth;
827 reg |= (0x3 & tparams) << 12;
828 reg |= (arb_rate & 0xff) << 16;
830 p->dma_write(reg, GCR, 0);
832 EXPORT_SYMBOL(omap_dma_set_global_params);
835 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
838 * @param read_prio - Read priority
839 * @param write_prio - Write priority
840 * Both of the above can be set with one of the following values :
841 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
844 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
845 unsigned char write_prio)
849 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
850 printk(KERN_ERR "Invalid channel id\n");
853 l = p->dma_read(CCR, lch);
854 l &= ~((1 << 6) | (1 << 26));
855 if (d->dev_caps & IS_RW_PRIORITY)
856 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
858 l |= ((read_prio & 0x1) << 6);
860 p->dma_write(l, CCR, lch);
864 EXPORT_SYMBOL(omap_dma_set_prio_lch);
867 * Clears any DMA state so the DMA engine is ready to restart with new buffers
868 * through omap_start_dma(). Any buffers in flight are discarded.
870 void omap_clear_dma(int lch)
874 local_irq_save(flags);
876 local_irq_restore(flags);
878 EXPORT_SYMBOL(omap_clear_dma);
880 void omap_start_dma(int lch)
885 * The CPC/CDAC register needs to be initialized to zero
886 * before starting dma transfer.
889 p->dma_write(0, CPC, lch);
891 p->dma_write(0, CDAC, lch);
893 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
894 int next_lch, cur_lch;
895 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
897 dma_chan_link_map[lch] = 1;
898 /* Set the link register of the first channel */
901 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
902 cur_lch = dma_chan[lch].next_lch;
904 next_lch = dma_chan[cur_lch].next_lch;
906 /* The loop case: we've been here already */
907 if (dma_chan_link_map[cur_lch])
909 /* Mark the current channel */
910 dma_chan_link_map[cur_lch] = 1;
913 omap_enable_channel_irq(cur_lch);
916 } while (next_lch != -1);
917 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
918 p->dma_write(lch, CLNK_CTRL, lch);
920 omap_enable_channel_irq(lch);
922 l = p->dma_read(CCR, lch);
924 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
925 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
926 l |= OMAP_DMA_CCR_EN;
929 * As dma_write() uses IO accessors which are weakly ordered, there
930 * is no guarantee that data in coherent DMA memory will be visible
931 * to the DMA device. Add a memory barrier here to ensure that any
932 * such data is visible prior to enabling DMA.
935 p->dma_write(l, CCR, lch);
937 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
939 EXPORT_SYMBOL(omap_start_dma);
941 void omap_stop_dma(int lch)
945 /* Disable all interrupts on the channel */
946 omap_disable_channel_irq(lch);
948 l = p->dma_read(CCR, lch);
949 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
950 (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
954 /* Configure No-Standby */
955 l = p->dma_read(OCP_SYSCONFIG, lch);
957 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
958 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
959 p->dma_write(l , OCP_SYSCONFIG, 0);
961 l = p->dma_read(CCR, lch);
962 l &= ~OMAP_DMA_CCR_EN;
963 p->dma_write(l, CCR, lch);
965 /* Wait for sDMA FIFO drain */
966 l = p->dma_read(CCR, lch);
967 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
968 OMAP_DMA_CCR_WR_ACTIVE))) {
971 l = p->dma_read(CCR, lch);
974 pr_err("DMA drain did not complete on lch %d\n", lch);
975 /* Restore OCP_SYSCONFIG */
976 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
978 l &= ~OMAP_DMA_CCR_EN;
979 p->dma_write(l, CCR, lch);
983 * Ensure that data transferred by DMA is visible to any access
984 * after DMA has been disabled. This is important for coherent
989 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
990 int next_lch, cur_lch = lch;
991 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
993 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
995 /* The loop case: we've been here already */
996 if (dma_chan_link_map[cur_lch])
998 /* Mark the current channel */
999 dma_chan_link_map[cur_lch] = 1;
1001 disable_lnk(cur_lch);
1003 next_lch = dma_chan[cur_lch].next_lch;
1005 } while (next_lch != -1);
1008 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1010 EXPORT_SYMBOL(omap_stop_dma);
1013 * Allows changing the DMA callback function or data. This may be needed if
1014 * the driver shares a single DMA channel for multiple dma triggers.
1016 int omap_set_dma_callback(int lch,
1017 void (*callback)(int lch, u16 ch_status, void *data),
1020 unsigned long flags;
1025 spin_lock_irqsave(&dma_chan_lock, flags);
1026 if (dma_chan[lch].dev_id == -1) {
1027 printk(KERN_ERR "DMA callback for not set for free channel\n");
1028 spin_unlock_irqrestore(&dma_chan_lock, flags);
1031 dma_chan[lch].callback = callback;
1032 dma_chan[lch].data = data;
1033 spin_unlock_irqrestore(&dma_chan_lock, flags);
1037 EXPORT_SYMBOL(omap_set_dma_callback);
1040 * Returns current physical source address for the given DMA channel.
1041 * If the channel is running the caller must disable interrupts prior calling
1042 * this function and process the returned value before re-enabling interrupt to
1043 * prevent races with the interrupt handler. Note that in continuous mode there
1044 * is a chance for CSSA_L register overflow between the two reads resulting
1045 * in incorrect return value.
1047 dma_addr_t omap_get_dma_src_pos(int lch)
1049 dma_addr_t offset = 0;
1052 offset = p->dma_read(CPC, lch);
1054 offset = p->dma_read(CSAC, lch);
1056 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1057 offset = p->dma_read(CSAC, lch);
1059 if (!dma_omap15xx()) {
1061 * CDAC == 0 indicates that the DMA transfer on the channel has
1062 * not been started (no data has been transferred so far).
1063 * Return the programmed source start address in this case.
1065 if (likely(p->dma_read(CDAC, lch)))
1066 offset = p->dma_read(CSAC, lch);
1068 offset = p->dma_read(CSSA, lch);
1072 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1076 EXPORT_SYMBOL(omap_get_dma_src_pos);
1079 * Returns current physical destination address for the given DMA channel.
1080 * If the channel is running the caller must disable interrupts prior calling
1081 * this function and process the returned value before re-enabling interrupt to
1082 * prevent races with the interrupt handler. Note that in continuous mode there
1083 * is a chance for CDSA_L register overflow between the two reads resulting
1084 * in incorrect return value.
1086 dma_addr_t omap_get_dma_dst_pos(int lch)
1088 dma_addr_t offset = 0;
1091 offset = p->dma_read(CPC, lch);
1093 offset = p->dma_read(CDAC, lch);
1096 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1097 * read before the DMA controller finished disabling the channel.
1099 if (!dma_omap15xx() && offset == 0) {
1100 offset = p->dma_read(CDAC, lch);
1102 * CDAC == 0 indicates that the DMA transfer on the channel has
1103 * not been started (no data has been transferred so far).
1104 * Return the programmed destination start address in this case.
1106 if (unlikely(!offset))
1107 offset = p->dma_read(CDSA, lch);
1111 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1115 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1117 int omap_get_dma_active_status(int lch)
1119 return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1121 EXPORT_SYMBOL(omap_get_dma_active_status);
1123 int omap_dma_running(void)
1128 if (omap_lcd_dma_running())
1131 for (lch = 0; lch < dma_chan_count; lch++)
1132 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1139 * lch_queue DMA will start right after lch_head one is finished.
1140 * For this DMA link to start, you still need to start (see omap_start_dma)
1141 * the first one. That will fire up the entire queue.
1143 void omap_dma_link_lch(int lch_head, int lch_queue)
1145 if (omap_dma_in_1510_mode()) {
1146 if (lch_head == lch_queue) {
1147 p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1151 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1156 if ((dma_chan[lch_head].dev_id == -1) ||
1157 (dma_chan[lch_queue].dev_id == -1)) {
1158 pr_err("omap_dma: trying to link non requested channels\n");
1162 dma_chan[lch_head].next_lch = lch_queue;
1164 EXPORT_SYMBOL(omap_dma_link_lch);
1167 * Once the DMA queue is stopped, we can destroy it.
1169 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1171 if (omap_dma_in_1510_mode()) {
1172 if (lch_head == lch_queue) {
1173 p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1177 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1182 if (dma_chan[lch_head].next_lch != lch_queue ||
1183 dma_chan[lch_head].next_lch == -1) {
1184 pr_err("omap_dma: trying to unlink non linked channels\n");
1188 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1189 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1190 pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
1194 dma_chan[lch_head].next_lch = -1;
1196 EXPORT_SYMBOL(omap_dma_unlink_lch);
1198 #ifndef CONFIG_ARCH_OMAP1
1199 /* Create chain of DMA channesls */
1200 static void create_dma_lch_chain(int lch_head, int lch_queue)
1204 /* Check if this is the first link in chain */
1205 if (dma_chan[lch_head].next_linked_ch == -1) {
1206 dma_chan[lch_head].next_linked_ch = lch_queue;
1207 dma_chan[lch_head].prev_linked_ch = lch_queue;
1208 dma_chan[lch_queue].next_linked_ch = lch_head;
1209 dma_chan[lch_queue].prev_linked_ch = lch_head;
1212 /* a link exists, link the new channel in circular chain */
1214 dma_chan[lch_queue].next_linked_ch =
1215 dma_chan[lch_head].next_linked_ch;
1216 dma_chan[lch_queue].prev_linked_ch = lch_head;
1217 dma_chan[lch_head].next_linked_ch = lch_queue;
1218 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1222 l = p->dma_read(CLNK_CTRL, lch_head);
1225 p->dma_write(l, CLNK_CTRL, lch_head);
1227 l = p->dma_read(CLNK_CTRL, lch_queue);
1229 l |= (dma_chan[lch_queue].next_linked_ch);
1230 p->dma_write(l, CLNK_CTRL, lch_queue);
1234 * @brief omap_request_dma_chain : Request a chain of DMA channels
1236 * @param dev_id - Device id using the dma channel
1237 * @param dev_name - Device name
1238 * @param callback - Call back function
1240 * @no_of_chans - Number of channels requested
1241 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1242 * OMAP_DMA_DYNAMIC_CHAIN
1243 * @params - Channel parameters
1245 * @return - Success : 0
1246 * Failure: -EINVAL/-ENOMEM
1248 int omap_request_dma_chain(int dev_id, const char *dev_name,
1249 void (*callback) (int lch, u16 ch_status,
1251 int *chain_id, int no_of_chans, int chain_mode,
1252 struct omap_dma_channel_params params)
1257 /* Is the chain mode valid ? */
1258 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1259 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1260 printk(KERN_ERR "Invalid chain mode requested\n");
1264 if (unlikely((no_of_chans < 1
1265 || no_of_chans > dma_lch_count))) {
1266 printk(KERN_ERR "Invalid Number of channels requested\n");
1271 * Allocate a queue to maintain the status of the channels
1274 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1275 if (channels == NULL) {
1276 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1280 /* request and reserve DMA channels for the chain */
1281 for (i = 0; i < no_of_chans; i++) {
1282 err = omap_request_dma(dev_id, dev_name,
1283 callback, NULL, &channels[i]);
1286 for (j = 0; j < i; j++)
1287 omap_free_dma(channels[j]);
1289 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1292 dma_chan[channels[i]].prev_linked_ch = -1;
1293 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1296 * Allowing client drivers to set common parameters now,
1297 * so that later only relevant (src_start, dest_start
1298 * and element count) can be set
1300 omap_set_dma_params(channels[i], ¶ms);
1303 *chain_id = channels[0];
1304 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1305 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1306 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1307 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1309 for (i = 0; i < no_of_chans; i++)
1310 dma_chan[channels[i]].chain_id = *chain_id;
1312 /* Reset the Queue pointers */
1313 OMAP_DMA_CHAIN_QINIT(*chain_id);
1315 /* Set up the chain */
1316 if (no_of_chans == 1)
1317 create_dma_lch_chain(channels[0], channels[0]);
1319 for (i = 0; i < (no_of_chans - 1); i++)
1320 create_dma_lch_chain(channels[i], channels[i + 1]);
1325 EXPORT_SYMBOL(omap_request_dma_chain);
1328 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1329 * params after setting it. Dont do this while dma is running!!
1331 * @param chain_id - Chained logical channel id.
1334 * @return - Success : 0
1337 int omap_modify_dma_chain_params(int chain_id,
1338 struct omap_dma_channel_params params)
1343 /* Check for input params */
1344 if (unlikely((chain_id < 0
1345 || chain_id >= dma_lch_count))) {
1346 printk(KERN_ERR "Invalid chain id\n");
1350 /* Check if the chain exists */
1351 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1352 printk(KERN_ERR "Chain doesn't exists\n");
1355 channels = dma_linked_lch[chain_id].linked_dmach_q;
1357 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1359 * Allowing client drivers to set common parameters now,
1360 * so that later only relevant (src_start, dest_start
1361 * and element count) can be set
1363 omap_set_dma_params(channels[i], ¶ms);
1368 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1371 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1375 * @return - Success : 0
1378 int omap_free_dma_chain(int chain_id)
1383 /* Check for input params */
1384 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1385 printk(KERN_ERR "Invalid chain id\n");
1389 /* Check if the chain exists */
1390 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1391 printk(KERN_ERR "Chain doesn't exists\n");
1395 channels = dma_linked_lch[chain_id].linked_dmach_q;
1396 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1397 dma_chan[channels[i]].next_linked_ch = -1;
1398 dma_chan[channels[i]].prev_linked_ch = -1;
1399 dma_chan[channels[i]].chain_id = -1;
1400 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1401 omap_free_dma(channels[i]);
1406 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1407 dma_linked_lch[chain_id].chain_mode = -1;
1408 dma_linked_lch[chain_id].chain_state = -1;
1412 EXPORT_SYMBOL(omap_free_dma_chain);
1415 * @brief omap_dma_chain_status - Check if the chain is in
1416 * active / inactive state.
1419 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1422 int omap_dma_chain_status(int chain_id)
1424 /* Check for input params */
1425 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1426 printk(KERN_ERR "Invalid chain id\n");
1430 /* Check if the chain exists */
1431 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1432 printk(KERN_ERR "Chain doesn't exists\n");
1435 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1436 dma_linked_lch[chain_id].q_count);
1438 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1439 return OMAP_DMA_CHAIN_INACTIVE;
1441 return OMAP_DMA_CHAIN_ACTIVE;
1443 EXPORT_SYMBOL(omap_dma_chain_status);
1446 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1447 * set the params and start the transfer.
1450 * @param src_start - buffer start address
1451 * @param dest_start - Dest address
1453 * @param frame_count
1454 * @param callbk_data - channel callback parameter data.
1456 * @return - Success : 0
1457 * Failure: -EINVAL/-EBUSY
1459 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1460 int elem_count, int frame_count, void *callbk_data)
1467 * if buffer size is less than 1 then there is
1468 * no use of starting the chain
1470 if (elem_count < 1) {
1471 printk(KERN_ERR "Invalid buffer size\n");
1475 /* Check for input params */
1476 if (unlikely((chain_id < 0
1477 || chain_id >= dma_lch_count))) {
1478 printk(KERN_ERR "Invalid chain id\n");
1482 /* Check if the chain exists */
1483 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1484 printk(KERN_ERR "Chain doesn't exist\n");
1488 /* Check if all the channels in chain are in use */
1489 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1492 /* Frame count may be negative in case of indexed transfers */
1493 channels = dma_linked_lch[chain_id].linked_dmach_q;
1495 /* Get a free channel */
1496 lch = channels[dma_linked_lch[chain_id].q_tail];
1498 /* Store the callback data */
1499 dma_chan[lch].data = callbk_data;
1501 /* Increment the q_tail */
1502 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1504 /* Set the params to the free channel */
1506 p->dma_write(src_start, CSSA, lch);
1507 if (dest_start != 0)
1508 p->dma_write(dest_start, CDSA, lch);
1510 /* Write the buffer size */
1511 p->dma_write(elem_count, CEN, lch);
1512 p->dma_write(frame_count, CFN, lch);
1515 * If the chain is dynamically linked,
1516 * then we may have to start the chain if its not active
1518 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1521 * In Dynamic chain, if the chain is not started,
1524 if (dma_linked_lch[chain_id].chain_state ==
1525 DMA_CHAIN_NOTSTARTED) {
1526 /* Enable the link in previous channel */
1527 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1529 enable_lnk(dma_chan[lch].prev_linked_ch);
1530 dma_chan[lch].state = DMA_CH_QUEUED;
1534 * Chain is already started, make sure its active,
1535 * if not then start the chain
1540 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1542 enable_lnk(dma_chan[lch].prev_linked_ch);
1543 dma_chan[lch].state = DMA_CH_QUEUED;
1545 if (0 == ((1 << 7) & p->dma_read(
1546 CCR, dma_chan[lch].prev_linked_ch))) {
1547 disable_lnk(dma_chan[lch].
1549 pr_debug("\n prev ch is stopped\n");
1554 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1556 enable_lnk(dma_chan[lch].prev_linked_ch);
1557 dma_chan[lch].state = DMA_CH_QUEUED;
1560 omap_enable_channel_irq(lch);
1562 l = p->dma_read(CCR, lch);
1564 if ((0 == (l & (1 << 24))))
1568 if (start_dma == 1) {
1569 if (0 == (l & (1 << 7))) {
1571 dma_chan[lch].state = DMA_CH_STARTED;
1572 pr_debug("starting %d\n", lch);
1573 p->dma_write(l, CCR, lch);
1577 if (0 == (l & (1 << 7)))
1578 p->dma_write(l, CCR, lch);
1580 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1586 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1589 * @brief omap_start_dma_chain_transfers - Start the chain
1593 * @return - Success : 0
1594 * Failure : -EINVAL/-EBUSY
1596 int omap_start_dma_chain_transfers(int chain_id)
1601 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1602 printk(KERN_ERR "Invalid chain id\n");
1606 channels = dma_linked_lch[chain_id].linked_dmach_q;
1608 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1609 printk(KERN_ERR "Chain is already started\n");
1613 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1614 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1616 enable_lnk(channels[i]);
1617 omap_enable_channel_irq(channels[i]);
1620 omap_enable_channel_irq(channels[0]);
1623 l = p->dma_read(CCR, channels[0]);
1625 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1626 dma_chan[channels[0]].state = DMA_CH_STARTED;
1628 if ((0 == (l & (1 << 24))))
1632 p->dma_write(l, CCR, channels[0]);
1634 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1638 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1641 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1645 * @return - Success : 0
1648 int omap_stop_dma_chain_transfers(int chain_id)
1654 /* Check for input params */
1655 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1656 printk(KERN_ERR "Invalid chain id\n");
1660 /* Check if the chain exists */
1661 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1662 printk(KERN_ERR "Chain doesn't exists\n");
1665 channels = dma_linked_lch[chain_id].linked_dmach_q;
1667 if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1668 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1670 /* Middle mode reg set no Standby */
1671 l &= ~((1 << 12)|(1 << 13));
1672 p->dma_write(l, OCP_SYSCONFIG, 0);
1675 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1677 /* Stop the Channel transmission */
1678 l = p->dma_read(CCR, channels[i]);
1680 p->dma_write(l, CCR, channels[i]);
1682 /* Disable the link in all the channels */
1683 disable_lnk(channels[i]);
1684 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1687 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1689 /* Reset the Queue pointers */
1690 OMAP_DMA_CHAIN_QINIT(chain_id);
1692 if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1693 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1697 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1699 /* Get the index of the ongoing DMA in chain */
1701 * @brief omap_get_dma_chain_index - Get the element and frame index
1702 * of the ongoing DMA in chain
1705 * @param ei - Element index
1706 * @param fi - Frame index
1708 * @return - Success : 0
1711 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1716 /* Check for input params */
1717 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1718 printk(KERN_ERR "Invalid chain id\n");
1722 /* Check if the chain exists */
1723 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1724 printk(KERN_ERR "Chain doesn't exists\n");
1730 channels = dma_linked_lch[chain_id].linked_dmach_q;
1732 /* Get the current channel */
1733 lch = channels[dma_linked_lch[chain_id].q_head];
1735 *ei = p->dma_read(CCEN, lch);
1736 *fi = p->dma_read(CCFN, lch);
1740 EXPORT_SYMBOL(omap_get_dma_chain_index);
1743 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1744 * ongoing DMA in chain
1748 * @return - Success : Destination position
1751 int omap_get_dma_chain_dst_pos(int chain_id)
1756 /* Check for input params */
1757 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1758 printk(KERN_ERR "Invalid chain id\n");
1762 /* Check if the chain exists */
1763 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1764 printk(KERN_ERR "Chain doesn't exists\n");
1768 channels = dma_linked_lch[chain_id].linked_dmach_q;
1770 /* Get the current channel */
1771 lch = channels[dma_linked_lch[chain_id].q_head];
1773 return p->dma_read(CDAC, lch);
1775 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1778 * @brief omap_get_dma_chain_src_pos - Get the source position
1779 * of the ongoing DMA in chain
1782 * @return - Success : Destination position
1785 int omap_get_dma_chain_src_pos(int chain_id)
1790 /* Check for input params */
1791 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1792 printk(KERN_ERR "Invalid chain id\n");
1796 /* Check if the chain exists */
1797 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1798 printk(KERN_ERR "Chain doesn't exists\n");
1802 channels = dma_linked_lch[chain_id].linked_dmach_q;
1804 /* Get the current channel */
1805 lch = channels[dma_linked_lch[chain_id].q_head];
1807 return p->dma_read(CSAC, lch);
1809 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1810 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1812 /*----------------------------------------------------------------------------*/
1814 #ifdef CONFIG_ARCH_OMAP1
1816 static int omap1_dma_handle_ch(int ch)
1820 if (enable_1510_mode && ch >= 6) {
1821 csr = dma_chan[ch].saved_csr;
1822 dma_chan[ch].saved_csr = 0;
1824 csr = p->dma_read(CSR, ch);
1825 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1826 dma_chan[ch + 6].saved_csr = csr >> 7;
1829 if ((csr & 0x3f) == 0)
1831 if (unlikely(dma_chan[ch].dev_id == -1)) {
1832 pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
1836 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1837 pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
1838 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1839 pr_warn("DMA synchronization event drop occurred with device %d\n",
1840 dma_chan[ch].dev_id);
1841 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1842 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1843 if (likely(dma_chan[ch].callback != NULL))
1844 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1849 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1851 int ch = ((int) dev_id) - 1;
1855 int handled_now = 0;
1857 handled_now += omap1_dma_handle_ch(ch);
1858 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1859 handled_now += omap1_dma_handle_ch(ch + 6);
1862 handled += handled_now;
1865 return handled ? IRQ_HANDLED : IRQ_NONE;
1869 #define omap1_dma_irq_handler NULL
1872 #ifdef CONFIG_ARCH_OMAP2PLUS
1874 static int omap2_dma_handle_ch(int ch)
1876 u32 status = p->dma_read(CSR, ch);
1879 if (printk_ratelimit())
1880 pr_warn("Spurious DMA IRQ for lch %d\n", ch);
1881 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1884 if (unlikely(dma_chan[ch].dev_id == -1)) {
1885 if (printk_ratelimit())
1886 pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
1890 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1891 pr_info("DMA synchronization event drop occurred with device %d\n",
1892 dma_chan[ch].dev_id);
1893 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1894 printk(KERN_INFO "DMA transaction error with device %d\n",
1895 dma_chan[ch].dev_id);
1896 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1899 ccr = p->dma_read(CCR, ch);
1900 ccr &= ~OMAP_DMA_CCR_EN;
1901 p->dma_write(ccr, CCR, ch);
1902 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1905 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1906 printk(KERN_INFO "DMA secure error with device %d\n",
1907 dma_chan[ch].dev_id);
1908 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1909 printk(KERN_INFO "DMA misaligned error with device %d\n",
1910 dma_chan[ch].dev_id);
1912 p->dma_write(status, CSR, ch);
1913 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1914 /* read back the register to flush the write */
1915 p->dma_read(IRQSTATUS_L0, ch);
1917 /* If the ch is not chained then chain_id will be -1 */
1918 if (dma_chan[ch].chain_id != -1) {
1919 int chain_id = dma_chan[ch].chain_id;
1920 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1921 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1922 dma_chan[dma_chan[ch].next_linked_ch].state =
1924 if (dma_linked_lch[chain_id].chain_mode ==
1925 OMAP_DMA_DYNAMIC_CHAIN)
1928 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1929 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1931 status = p->dma_read(CSR, ch);
1932 p->dma_write(status, CSR, ch);
1935 if (likely(dma_chan[ch].callback != NULL))
1936 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1941 /* STATUS register count is from 1-32 while our is 0-31 */
1942 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1944 u32 val, enable_reg;
1947 val = p->dma_read(IRQSTATUS_L0, 0);
1949 if (printk_ratelimit())
1950 printk(KERN_WARNING "Spurious DMA IRQ\n");
1953 enable_reg = p->dma_read(IRQENABLE_L0, 0);
1954 val &= enable_reg; /* Dispatch only relevant interrupts */
1955 for (i = 0; i < dma_lch_count && val != 0; i++) {
1957 omap2_dma_handle_ch(i);
1964 static struct irqaction omap24xx_dma_irq = {
1966 .handler = omap2_dma_irq_handler,
1967 .flags = IRQF_DISABLED
1971 static struct irqaction omap24xx_dma_irq;
1974 /*----------------------------------------------------------------------------*/
1976 void omap_dma_global_context_save(void)
1978 omap_dma_global_context.dma_irqenable_l0 =
1979 p->dma_read(IRQENABLE_L0, 0);
1980 omap_dma_global_context.dma_ocp_sysconfig =
1981 p->dma_read(OCP_SYSCONFIG, 0);
1982 omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1985 void omap_dma_global_context_restore(void)
1989 p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1990 p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1992 p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1995 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1996 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1998 for (ch = 0; ch < dma_chan_count; ch++)
1999 if (dma_chan[ch].dev_id != -1)
2003 static int omap_system_dma_probe(struct platform_device *pdev)
2010 p = pdev->dev.platform_data;
2013 "%s: System DMA initialized without platform data\n",
2021 if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
2022 && (omap_dma_reserve_channels <= dma_lch_count))
2023 d->lch_count = omap_dma_reserve_channels;
2025 dma_lch_count = d->lch_count;
2026 dma_chan_count = dma_lch_count;
2028 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
2030 if (dma_omap2plus()) {
2031 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2032 dma_lch_count, GFP_KERNEL);
2033 if (!dma_linked_lch) {
2035 goto exit_dma_lch_fail;
2039 spin_lock_init(&dma_chan_lock);
2040 for (ch = 0; ch < dma_chan_count; ch++) {
2042 if (dma_omap2plus())
2043 omap2_disable_irq_lch(ch);
2045 dma_chan[ch].dev_id = -1;
2046 dma_chan[ch].next_lch = -1;
2048 if (ch >= 6 && enable_1510_mode)
2053 * request_irq() doesn't like dev_id (ie. ch) being
2054 * zero, so we have to kludge around this.
2056 sprintf(&irq_name[0], "%d", ch);
2057 dma_irq = platform_get_irq_byname(pdev, irq_name);
2061 goto exit_dma_irq_fail;
2064 /* INT_DMA_LCD is handled in lcd_dma.c */
2065 if (dma_irq == INT_DMA_LCD)
2068 ret = request_irq(dma_irq,
2069 omap1_dma_irq_handler, 0, "DMA",
2072 goto exit_dma_irq_fail;
2076 if (d->dev_caps & IS_RW_PRIORITY)
2077 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2078 DMA_DEFAULT_FIFO_DEPTH, 0);
2080 if (dma_omap2plus()) {
2081 strcpy(irq_name, "0");
2082 dma_irq = platform_get_irq_byname(pdev, irq_name);
2084 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2085 goto exit_dma_lch_fail;
2087 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2089 dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
2091 goto exit_dma_lch_fail;
2095 /* reserve dma channels 0 and 1 in high security devices on 34xx */
2096 if (d->dev_caps & HS_CHANNELS_RESERVED) {
2097 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
2098 dma_chan[0].dev_id = 0;
2099 dma_chan[1].dev_id = 1;
2105 dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
2107 for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2108 dma_irq = platform_get_irq(pdev, irq_rel);
2109 free_irq(dma_irq, (void *)(irq_rel + 1));
2119 static int omap_system_dma_remove(struct platform_device *pdev)
2123 if (dma_omap2plus()) {
2125 strcpy(irq_name, "0");
2126 dma_irq = platform_get_irq_byname(pdev, irq_name);
2127 remove_irq(dma_irq, &omap24xx_dma_irq);
2130 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2131 dma_irq = platform_get_irq(pdev, irq_rel);
2132 free_irq(dma_irq, (void *)(irq_rel + 1));
2141 static struct platform_driver omap_system_dma_driver = {
2142 .probe = omap_system_dma_probe,
2143 .remove = omap_system_dma_remove,
2145 .name = "omap_dma_system"
2149 static int __init omap_system_dma_init(void)
2151 return platform_driver_register(&omap_system_dma_driver);
2153 arch_initcall(omap_system_dma_init);
2155 static void __exit omap_system_dma_exit(void)
2157 platform_driver_unregister(&omap_system_dma_driver);
2160 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2161 MODULE_LICENSE("GPL");
2162 MODULE_ALIAS("platform:" DRIVER_NAME);
2163 MODULE_AUTHOR("Texas Instruments Inc");
2166 * Reserve the omap SDMA channels using cmdline bootarg
2167 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2169 static int __init omap_dma_cmdline_reserve_ch(char *str)
2171 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2172 omap_dma_reserve_channels = 0;
2176 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);