2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Support functions for the OMAP internal DMA channels.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
30 #include <asm/system.h>
31 #include <mach/hardware.h>
38 #ifndef CONFIG_ARCH_OMAP1
39 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
40 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
43 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
46 #define OMAP_DMA_ACTIVE 0x01
47 #define OMAP_DMA_CCR_EN (1 << 7)
48 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
50 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
52 static int enable_1510_mode;
60 void (*callback)(int lch, u16 ch_status, void *data);
63 #ifndef CONFIG_ARCH_OMAP1
64 /* required for Dynamic chaining */
75 struct dma_link_info {
77 int no_of_lchs_linked;
88 static struct dma_link_info *dma_linked_lch;
90 #ifndef CONFIG_ARCH_OMAP1
92 /* Chain handling macros */
93 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
95 dma_linked_lch[chain_id].q_head = \
96 dma_linked_lch[chain_id].q_tail = \
97 dma_linked_lch[chain_id].q_count = 0; \
99 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
100 (dma_linked_lch[chain_id].no_of_lchs_linked == \
101 dma_linked_lch[chain_id].q_count)
102 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
104 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
105 dma_linked_lch[chain_id].q_count) \
107 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
108 (0 == dma_linked_lch[chain_id].q_count)
109 #define __OMAP_DMA_CHAIN_INCQ(end) \
110 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
111 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
113 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
114 dma_linked_lch[chain_id].q_count--; \
117 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
119 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
120 dma_linked_lch[chain_id].q_count++; \
124 static int dma_lch_count;
125 static int dma_chan_count;
126 static int omap_dma_reserve_channels;
128 static spinlock_t dma_chan_lock;
129 static struct omap_dma_lch *dma_chan;
130 static void __iomem *omap_dma_base;
132 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
133 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
134 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
135 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
136 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
137 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
140 static inline void disable_lnk(int lch);
141 static void omap_disable_channel_irq(int lch);
142 static inline void omap_enable_channel_irq(int lch);
144 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
147 #define dma_read(reg) \
150 if (cpu_class_is_omap1()) \
151 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
153 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
157 #define dma_write(val, reg) \
159 if (cpu_class_is_omap1()) \
160 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
162 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
165 #ifdef CONFIG_ARCH_OMAP15XX
166 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
167 int omap_dma_in_1510_mode(void)
169 return enable_1510_mode;
172 #define omap_dma_in_1510_mode() 0
175 #ifdef CONFIG_ARCH_OMAP1
176 static inline int get_gdma_dev(int req)
178 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
179 int shift = ((req - 1) % 5) * 6;
181 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
184 static inline void set_gdma_dev(int req, int dev)
186 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
187 int shift = ((req - 1) % 5) * 6;
191 l &= ~(0x3f << shift);
192 l |= (dev - 1) << shift;
196 #define set_gdma_dev(req, dev) do {} while (0)
200 static void clear_lch_regs(int lch)
203 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
205 for (i = 0; i < 0x2c; i += 2)
206 __raw_writew(0, lch_base + i);
209 void omap_set_dma_priority(int lch, int dst_port, int priority)
214 if (cpu_class_is_omap1()) {
216 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
217 reg = OMAP_TC_OCPT1_PRIOR;
219 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
220 reg = OMAP_TC_OCPT2_PRIOR;
222 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
223 reg = OMAP_TC_EMIFF_PRIOR;
225 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
226 reg = OMAP_TC_EMIFS_PRIOR;
234 l |= (priority & 0xf) << 8;
238 if (cpu_class_is_omap2()) {
241 ccr = dma_read(CCR(lch));
246 dma_write(ccr, CCR(lch));
249 EXPORT_SYMBOL(omap_set_dma_priority);
251 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
252 int frame_count, int sync_mode,
253 int dma_trigger, int src_or_dst_synch)
257 l = dma_read(CSDP(lch));
260 dma_write(l, CSDP(lch));
262 if (cpu_class_is_omap1()) {
265 ccr = dma_read(CCR(lch));
267 if (sync_mode == OMAP_DMA_SYNC_FRAME)
269 dma_write(ccr, CCR(lch));
271 ccr = dma_read(CCR2(lch));
273 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
275 dma_write(ccr, CCR2(lch));
278 if (cpu_class_is_omap2() && dma_trigger) {
281 val = dma_read(CCR(lch));
283 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
284 val &= ~((3 << 19) | 0x1f);
285 val |= (dma_trigger & ~0x1f) << 14;
286 val |= dma_trigger & 0x1f;
288 if (sync_mode & OMAP_DMA_SYNC_FRAME)
293 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
298 if (src_or_dst_synch)
299 val |= 1 << 24; /* source synch */
301 val &= ~(1 << 24); /* dest synch */
303 dma_write(val, CCR(lch));
306 dma_write(elem_count, CEN(lch));
307 dma_write(frame_count, CFN(lch));
309 EXPORT_SYMBOL(omap_set_dma_transfer_params);
311 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
313 BUG_ON(omap_dma_in_1510_mode());
315 if (cpu_class_is_omap1()) {
318 w = dma_read(CCR2(lch));
322 case OMAP_DMA_CONSTANT_FILL:
325 case OMAP_DMA_TRANSPARENT_COPY:
328 case OMAP_DMA_COLOR_DIS:
333 dma_write(w, CCR2(lch));
335 w = dma_read(LCH_CTRL(lch));
337 /* Default is channel type 2D */
339 dma_write((u16)color, COLOR_L(lch));
340 dma_write((u16)(color >> 16), COLOR_U(lch));
341 w |= 1; /* Channel type G */
343 dma_write(w, LCH_CTRL(lch));
346 if (cpu_class_is_omap2()) {
349 val = dma_read(CCR(lch));
350 val &= ~((1 << 17) | (1 << 16));
353 case OMAP_DMA_CONSTANT_FILL:
356 case OMAP_DMA_TRANSPARENT_COPY:
359 case OMAP_DMA_COLOR_DIS:
364 dma_write(val, CCR(lch));
367 dma_write(color, COLOR(lch));
370 EXPORT_SYMBOL(omap_set_dma_color_mode);
372 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
374 if (cpu_class_is_omap2()) {
377 csdp = dma_read(CSDP(lch));
378 csdp &= ~(0x3 << 16);
379 csdp |= (mode << 16);
380 dma_write(csdp, CSDP(lch));
383 EXPORT_SYMBOL(omap_set_dma_write_mode);
385 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
387 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
390 l = dma_read(LCH_CTRL(lch));
393 dma_write(l, LCH_CTRL(lch));
396 EXPORT_SYMBOL(omap_set_dma_channel_mode);
398 /* Note that src_port is only for omap1 */
399 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
400 unsigned long src_start,
401 int src_ei, int src_fi)
405 if (cpu_class_is_omap1()) {
408 w = dma_read(CSDP(lch));
411 dma_write(w, CSDP(lch));
414 l = dma_read(CCR(lch));
416 l |= src_amode << 12;
417 dma_write(l, CCR(lch));
419 if (cpu_class_is_omap1()) {
420 dma_write(src_start >> 16, CSSA_U(lch));
421 dma_write((u16)src_start, CSSA_L(lch));
424 if (cpu_class_is_omap2())
425 dma_write(src_start, CSSA(lch));
427 dma_write(src_ei, CSEI(lch));
428 dma_write(src_fi, CSFI(lch));
430 EXPORT_SYMBOL(omap_set_dma_src_params);
432 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
434 omap_set_dma_transfer_params(lch, params->data_type,
435 params->elem_count, params->frame_count,
436 params->sync_mode, params->trigger,
437 params->src_or_dst_synch);
438 omap_set_dma_src_params(lch, params->src_port,
439 params->src_amode, params->src_start,
440 params->src_ei, params->src_fi);
442 omap_set_dma_dest_params(lch, params->dst_port,
443 params->dst_amode, params->dst_start,
444 params->dst_ei, params->dst_fi);
445 if (params->read_prio || params->write_prio)
446 omap_dma_set_prio_lch(lch, params->read_prio,
449 EXPORT_SYMBOL(omap_set_dma_params);
451 void omap_set_dma_src_index(int lch, int eidx, int fidx)
453 if (cpu_class_is_omap2())
456 dma_write(eidx, CSEI(lch));
457 dma_write(fidx, CSFI(lch));
459 EXPORT_SYMBOL(omap_set_dma_src_index);
461 void omap_set_dma_src_data_pack(int lch, int enable)
465 l = dma_read(CSDP(lch));
469 dma_write(l, CSDP(lch));
471 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
473 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
475 unsigned int burst = 0;
478 l = dma_read(CSDP(lch));
481 switch (burst_mode) {
482 case OMAP_DMA_DATA_BURST_DIS:
484 case OMAP_DMA_DATA_BURST_4:
485 if (cpu_class_is_omap2())
490 case OMAP_DMA_DATA_BURST_8:
491 if (cpu_class_is_omap2()) {
495 /* not supported by current hardware on OMAP1
499 case OMAP_DMA_DATA_BURST_16:
500 if (cpu_class_is_omap2()) {
504 /* OMAP1 don't support burst 16
512 dma_write(l, CSDP(lch));
514 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
516 /* Note that dest_port is only for OMAP1 */
517 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
518 unsigned long dest_start,
519 int dst_ei, int dst_fi)
523 if (cpu_class_is_omap1()) {
524 l = dma_read(CSDP(lch));
527 dma_write(l, CSDP(lch));
530 l = dma_read(CCR(lch));
532 l |= dest_amode << 14;
533 dma_write(l, CCR(lch));
535 if (cpu_class_is_omap1()) {
536 dma_write(dest_start >> 16, CDSA_U(lch));
537 dma_write(dest_start, CDSA_L(lch));
540 if (cpu_class_is_omap2())
541 dma_write(dest_start, CDSA(lch));
543 dma_write(dst_ei, CDEI(lch));
544 dma_write(dst_fi, CDFI(lch));
546 EXPORT_SYMBOL(omap_set_dma_dest_params);
548 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
550 if (cpu_class_is_omap2())
553 dma_write(eidx, CDEI(lch));
554 dma_write(fidx, CDFI(lch));
556 EXPORT_SYMBOL(omap_set_dma_dest_index);
558 void omap_set_dma_dest_data_pack(int lch, int enable)
562 l = dma_read(CSDP(lch));
566 dma_write(l, CSDP(lch));
568 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
570 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
572 unsigned int burst = 0;
575 l = dma_read(CSDP(lch));
578 switch (burst_mode) {
579 case OMAP_DMA_DATA_BURST_DIS:
581 case OMAP_DMA_DATA_BURST_4:
582 if (cpu_class_is_omap2())
587 case OMAP_DMA_DATA_BURST_8:
588 if (cpu_class_is_omap2())
593 case OMAP_DMA_DATA_BURST_16:
594 if (cpu_class_is_omap2()) {
598 /* OMAP1 don't support burst 16
602 printk(KERN_ERR "Invalid DMA burst mode\n");
607 dma_write(l, CSDP(lch));
609 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
611 static inline void omap_enable_channel_irq(int lch)
616 if (cpu_class_is_omap1())
617 status = dma_read(CSR(lch));
618 else if (cpu_class_is_omap2())
619 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
621 /* Enable some nice interrupts. */
622 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
625 static void omap_disable_channel_irq(int lch)
627 if (cpu_class_is_omap2())
628 dma_write(0, CICR(lch));
631 void omap_enable_dma_irq(int lch, u16 bits)
633 dma_chan[lch].enabled_irqs |= bits;
635 EXPORT_SYMBOL(omap_enable_dma_irq);
637 void omap_disable_dma_irq(int lch, u16 bits)
639 dma_chan[lch].enabled_irqs &= ~bits;
641 EXPORT_SYMBOL(omap_disable_dma_irq);
643 static inline void enable_lnk(int lch)
647 l = dma_read(CLNK_CTRL(lch));
649 if (cpu_class_is_omap1())
652 /* Set the ENABLE_LNK bits */
653 if (dma_chan[lch].next_lch != -1)
654 l = dma_chan[lch].next_lch | (1 << 15);
656 #ifndef CONFIG_ARCH_OMAP1
657 if (cpu_class_is_omap2())
658 if (dma_chan[lch].next_linked_ch != -1)
659 l = dma_chan[lch].next_linked_ch | (1 << 15);
662 dma_write(l, CLNK_CTRL(lch));
665 static inline void disable_lnk(int lch)
669 l = dma_read(CLNK_CTRL(lch));
671 /* Disable interrupts */
672 if (cpu_class_is_omap1()) {
673 dma_write(0, CICR(lch));
674 /* Set the STOP_LNK bit */
678 if (cpu_class_is_omap2()) {
679 omap_disable_channel_irq(lch);
680 /* Clear the ENABLE_LNK bit */
684 dma_write(l, CLNK_CTRL(lch));
685 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
688 static inline void omap2_enable_irq_lch(int lch)
692 if (!cpu_class_is_omap2())
695 val = dma_read(IRQENABLE_L0);
697 dma_write(val, IRQENABLE_L0);
700 int omap_request_dma(int dev_id, const char *dev_name,
701 void (*callback)(int lch, u16 ch_status, void *data),
702 void *data, int *dma_ch_out)
704 int ch, free_ch = -1;
706 struct omap_dma_lch *chan;
708 spin_lock_irqsave(&dma_chan_lock, flags);
709 for (ch = 0; ch < dma_chan_count; ch++) {
710 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
717 spin_unlock_irqrestore(&dma_chan_lock, flags);
720 chan = dma_chan + free_ch;
721 chan->dev_id = dev_id;
723 if (cpu_class_is_omap1())
724 clear_lch_regs(free_ch);
726 if (cpu_class_is_omap2())
727 omap_clear_dma(free_ch);
729 spin_unlock_irqrestore(&dma_chan_lock, flags);
731 chan->dev_name = dev_name;
732 chan->callback = callback;
736 #ifndef CONFIG_ARCH_OMAP1
737 if (cpu_class_is_omap2()) {
739 chan->next_linked_ch = -1;
743 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
745 if (cpu_class_is_omap1())
746 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
747 else if (cpu_class_is_omap2())
748 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
749 OMAP2_DMA_TRANS_ERR_IRQ;
751 if (cpu_is_omap16xx()) {
752 /* If the sync device is set, configure it dynamically. */
754 set_gdma_dev(free_ch + 1, dev_id);
755 dev_id = free_ch + 1;
758 * Disable the 1510 compatibility mode and set the sync device
761 dma_write(dev_id | (1 << 10), CCR(free_ch));
762 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
763 dma_write(dev_id, CCR(free_ch));
766 if (cpu_class_is_omap2()) {
767 omap2_enable_irq_lch(free_ch);
768 omap_enable_channel_irq(free_ch);
769 /* Clear the CSR register and IRQ status register */
770 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
771 dma_write(1 << free_ch, IRQSTATUS_L0);
774 *dma_ch_out = free_ch;
778 EXPORT_SYMBOL(omap_request_dma);
780 void omap_free_dma(int lch)
784 if (dma_chan[lch].dev_id == -1) {
785 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
790 if (cpu_class_is_omap1()) {
791 /* Disable all DMA interrupts for the channel. */
792 dma_write(0, CICR(lch));
793 /* Make sure the DMA transfer is stopped. */
794 dma_write(0, CCR(lch));
797 if (cpu_class_is_omap2()) {
799 /* Disable interrupts */
800 val = dma_read(IRQENABLE_L0);
802 dma_write(val, IRQENABLE_L0);
804 /* Clear the CSR register and IRQ status register */
805 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
806 dma_write(1 << lch, IRQSTATUS_L0);
808 /* Disable all DMA interrupts for the channel. */
809 dma_write(0, CICR(lch));
811 /* Make sure the DMA transfer is stopped. */
812 dma_write(0, CCR(lch));
816 spin_lock_irqsave(&dma_chan_lock, flags);
817 dma_chan[lch].dev_id = -1;
818 dma_chan[lch].next_lch = -1;
819 dma_chan[lch].callback = NULL;
820 spin_unlock_irqrestore(&dma_chan_lock, flags);
822 EXPORT_SYMBOL(omap_free_dma);
825 * @brief omap_dma_set_global_params : Set global priority settings for dma
828 * @param max_fifo_depth
829 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
830 * DMA_THREAD_RESERVE_ONET
831 * DMA_THREAD_RESERVE_TWOT
832 * DMA_THREAD_RESERVE_THREET
835 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
839 if (!cpu_class_is_omap2()) {
840 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
847 reg = (arb_rate & 0xff) << 16;
848 reg |= (0xff & max_fifo_depth);
852 EXPORT_SYMBOL(omap_dma_set_global_params);
855 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
858 * @param read_prio - Read priority
859 * @param write_prio - Write priority
860 * Both of the above can be set with one of the following values :
861 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
864 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
865 unsigned char write_prio)
869 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
870 printk(KERN_ERR "Invalid channel id\n");
873 l = dma_read(CCR(lch));
874 l &= ~((1 << 6) | (1 << 26));
875 if (cpu_is_omap2430() || cpu_is_omap34xx())
876 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
878 l |= ((read_prio & 0x1) << 6);
880 dma_write(l, CCR(lch));
884 EXPORT_SYMBOL(omap_dma_set_prio_lch);
887 * Clears any DMA state so the DMA engine is ready to restart with new buffers
888 * through omap_start_dma(). Any buffers in flight are discarded.
890 void omap_clear_dma(int lch)
894 local_irq_save(flags);
896 if (cpu_class_is_omap1()) {
899 l = dma_read(CCR(lch));
900 l &= ~OMAP_DMA_CCR_EN;
901 dma_write(l, CCR(lch));
903 /* Clear pending interrupts */
904 l = dma_read(CSR(lch));
907 if (cpu_class_is_omap2()) {
909 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
910 for (i = 0; i < 0x44; i += 4)
911 __raw_writel(0, lch_base + i);
914 local_irq_restore(flags);
916 EXPORT_SYMBOL(omap_clear_dma);
918 void omap_start_dma(int lch)
922 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
923 int next_lch, cur_lch;
924 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
926 dma_chan_link_map[lch] = 1;
927 /* Set the link register of the first channel */
930 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
931 cur_lch = dma_chan[lch].next_lch;
933 next_lch = dma_chan[cur_lch].next_lch;
935 /* The loop case: we've been here already */
936 if (dma_chan_link_map[cur_lch])
938 /* Mark the current channel */
939 dma_chan_link_map[cur_lch] = 1;
942 omap_enable_channel_irq(cur_lch);
945 } while (next_lch != -1);
946 } else if (cpu_class_is_omap2()) {
947 /* Errata: Need to write lch even if not using chaining */
948 dma_write(lch, CLNK_CTRL(lch));
951 omap_enable_channel_irq(lch);
953 l = dma_read(CCR(lch));
956 * Errata: On ES2.0 BUFFERING disable must be set.
957 * This will always fail on ES1.0
959 if (cpu_is_omap24xx())
960 l |= OMAP_DMA_CCR_EN;
962 l |= OMAP_DMA_CCR_EN;
963 dma_write(l, CCR(lch));
965 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
967 EXPORT_SYMBOL(omap_start_dma);
969 void omap_stop_dma(int lch)
973 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
974 int next_lch, cur_lch = lch;
975 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
977 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
979 /* The loop case: we've been here already */
980 if (dma_chan_link_map[cur_lch])
982 /* Mark the current channel */
983 dma_chan_link_map[cur_lch] = 1;
985 disable_lnk(cur_lch);
987 next_lch = dma_chan[cur_lch].next_lch;
989 } while (next_lch != -1);
994 /* Disable all interrupts on the channel */
995 if (cpu_class_is_omap1())
996 dma_write(0, CICR(lch));
998 l = dma_read(CCR(lch));
999 l &= ~OMAP_DMA_CCR_EN;
1000 dma_write(l, CCR(lch));
1002 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1004 EXPORT_SYMBOL(omap_stop_dma);
1007 * Allows changing the DMA callback function or data. This may be needed if
1008 * the driver shares a single DMA channel for multiple dma triggers.
1010 int omap_set_dma_callback(int lch,
1011 void (*callback)(int lch, u16 ch_status, void *data),
1014 unsigned long flags;
1019 spin_lock_irqsave(&dma_chan_lock, flags);
1020 if (dma_chan[lch].dev_id == -1) {
1021 printk(KERN_ERR "DMA callback for not set for free channel\n");
1022 spin_unlock_irqrestore(&dma_chan_lock, flags);
1025 dma_chan[lch].callback = callback;
1026 dma_chan[lch].data = data;
1027 spin_unlock_irqrestore(&dma_chan_lock, flags);
1031 EXPORT_SYMBOL(omap_set_dma_callback);
1034 * Returns current physical source address for the given DMA channel.
1035 * If the channel is running the caller must disable interrupts prior calling
1036 * this function and process the returned value before re-enabling interrupt to
1037 * prevent races with the interrupt handler. Note that in continuous mode there
1038 * is a chance for CSSA_L register overflow inbetween the two reads resulting
1039 * in incorrect return value.
1041 dma_addr_t omap_get_dma_src_pos(int lch)
1043 dma_addr_t offset = 0;
1045 if (cpu_is_omap15xx())
1046 offset = dma_read(CPC(lch));
1048 offset = dma_read(CSAC(lch));
1051 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1052 * read before the DMA controller finished disabling the channel.
1054 if (!cpu_is_omap15xx() && offset == 0)
1055 offset = dma_read(CSAC(lch));
1057 if (cpu_class_is_omap1())
1058 offset |= (dma_read(CSSA_U(lch)) << 16);
1062 EXPORT_SYMBOL(omap_get_dma_src_pos);
1065 * Returns current physical destination address for the given DMA channel.
1066 * If the channel is running the caller must disable interrupts prior calling
1067 * this function and process the returned value before re-enabling interrupt to
1068 * prevent races with the interrupt handler. Note that in continuous mode there
1069 * is a chance for CDSA_L register overflow inbetween the two reads resulting
1070 * in incorrect return value.
1072 dma_addr_t omap_get_dma_dst_pos(int lch)
1074 dma_addr_t offset = 0;
1076 if (cpu_is_omap15xx())
1077 offset = dma_read(CPC(lch));
1079 offset = dma_read(CDAC(lch));
1082 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1083 * read before the DMA controller finished disabling the channel.
1085 if (!cpu_is_omap15xx() && offset == 0)
1086 offset = dma_read(CDAC(lch));
1088 if (cpu_class_is_omap1())
1089 offset |= (dma_read(CDSA_U(lch)) << 16);
1093 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1095 int omap_get_dma_active_status(int lch)
1097 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1099 EXPORT_SYMBOL(omap_get_dma_active_status);
1101 int omap_dma_running(void)
1105 /* Check if LCD DMA is running */
1106 if (cpu_is_omap16xx())
1107 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1110 for (lch = 0; lch < dma_chan_count; lch++)
1111 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1118 * lch_queue DMA will start right after lch_head one is finished.
1119 * For this DMA link to start, you still need to start (see omap_start_dma)
1120 * the first one. That will fire up the entire queue.
1122 void omap_dma_link_lch(int lch_head, int lch_queue)
1124 if (omap_dma_in_1510_mode()) {
1125 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1130 if ((dma_chan[lch_head].dev_id == -1) ||
1131 (dma_chan[lch_queue].dev_id == -1)) {
1132 printk(KERN_ERR "omap_dma: trying to link "
1133 "non requested channels\n");
1137 dma_chan[lch_head].next_lch = lch_queue;
1139 EXPORT_SYMBOL(omap_dma_link_lch);
1142 * Once the DMA queue is stopped, we can destroy it.
1144 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1146 if (omap_dma_in_1510_mode()) {
1147 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1152 if (dma_chan[lch_head].next_lch != lch_queue ||
1153 dma_chan[lch_head].next_lch == -1) {
1154 printk(KERN_ERR "omap_dma: trying to unlink "
1155 "non linked channels\n");
1159 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1160 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1161 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1162 "before unlinking\n");
1166 dma_chan[lch_head].next_lch = -1;
1168 EXPORT_SYMBOL(omap_dma_unlink_lch);
1170 /*----------------------------------------------------------------------------*/
1172 #ifndef CONFIG_ARCH_OMAP1
1173 /* Create chain of DMA channesls */
1174 static void create_dma_lch_chain(int lch_head, int lch_queue)
1178 /* Check if this is the first link in chain */
1179 if (dma_chan[lch_head].next_linked_ch == -1) {
1180 dma_chan[lch_head].next_linked_ch = lch_queue;
1181 dma_chan[lch_head].prev_linked_ch = lch_queue;
1182 dma_chan[lch_queue].next_linked_ch = lch_head;
1183 dma_chan[lch_queue].prev_linked_ch = lch_head;
1186 /* a link exists, link the new channel in circular chain */
1188 dma_chan[lch_queue].next_linked_ch =
1189 dma_chan[lch_head].next_linked_ch;
1190 dma_chan[lch_queue].prev_linked_ch = lch_head;
1191 dma_chan[lch_head].next_linked_ch = lch_queue;
1192 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1196 l = dma_read(CLNK_CTRL(lch_head));
1199 dma_write(l, CLNK_CTRL(lch_head));
1201 l = dma_read(CLNK_CTRL(lch_queue));
1203 l |= (dma_chan[lch_queue].next_linked_ch);
1204 dma_write(l, CLNK_CTRL(lch_queue));
1208 * @brief omap_request_dma_chain : Request a chain of DMA channels
1210 * @param dev_id - Device id using the dma channel
1211 * @param dev_name - Device name
1212 * @param callback - Call back function
1214 * @no_of_chans - Number of channels requested
1215 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1216 * OMAP_DMA_DYNAMIC_CHAIN
1217 * @params - Channel parameters
1219 * @return - Succes : 0
1220 * Failure: -EINVAL/-ENOMEM
1222 int omap_request_dma_chain(int dev_id, const char *dev_name,
1223 void (*callback) (int chain_id, u16 ch_status,
1225 int *chain_id, int no_of_chans, int chain_mode,
1226 struct omap_dma_channel_params params)
1231 /* Is the chain mode valid ? */
1232 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1233 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1234 printk(KERN_ERR "Invalid chain mode requested\n");
1238 if (unlikely((no_of_chans < 1
1239 || no_of_chans > dma_lch_count))) {
1240 printk(KERN_ERR "Invalid Number of channels requested\n");
1244 /* Allocate a queue to maintain the status of the channels
1246 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1247 if (channels == NULL) {
1248 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1252 /* request and reserve DMA channels for the chain */
1253 for (i = 0; i < no_of_chans; i++) {
1254 err = omap_request_dma(dev_id, dev_name,
1255 callback, NULL, &channels[i]);
1258 for (j = 0; j < i; j++)
1259 omap_free_dma(channels[j]);
1261 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1264 dma_chan[channels[i]].prev_linked_ch = -1;
1265 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1268 * Allowing client drivers to set common parameters now,
1269 * so that later only relevant (src_start, dest_start
1270 * and element count) can be set
1272 omap_set_dma_params(channels[i], ¶ms);
1275 *chain_id = channels[0];
1276 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1277 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1278 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1279 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1281 for (i = 0; i < no_of_chans; i++)
1282 dma_chan[channels[i]].chain_id = *chain_id;
1284 /* Reset the Queue pointers */
1285 OMAP_DMA_CHAIN_QINIT(*chain_id);
1287 /* Set up the chain */
1288 if (no_of_chans == 1)
1289 create_dma_lch_chain(channels[0], channels[0]);
1291 for (i = 0; i < (no_of_chans - 1); i++)
1292 create_dma_lch_chain(channels[i], channels[i + 1]);
1297 EXPORT_SYMBOL(omap_request_dma_chain);
1300 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1301 * params after setting it. Dont do this while dma is running!!
1303 * @param chain_id - Chained logical channel id.
1306 * @return - Success : 0
1309 int omap_modify_dma_chain_params(int chain_id,
1310 struct omap_dma_channel_params params)
1315 /* Check for input params */
1316 if (unlikely((chain_id < 0
1317 || chain_id >= dma_lch_count))) {
1318 printk(KERN_ERR "Invalid chain id\n");
1322 /* Check if the chain exists */
1323 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1324 printk(KERN_ERR "Chain doesn't exists\n");
1327 channels = dma_linked_lch[chain_id].linked_dmach_q;
1329 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1331 * Allowing client drivers to set common parameters now,
1332 * so that later only relevant (src_start, dest_start
1333 * and element count) can be set
1335 omap_set_dma_params(channels[i], ¶ms);
1340 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1343 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1347 * @return - Success : 0
1350 int omap_free_dma_chain(int chain_id)
1355 /* Check for input params */
1356 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1357 printk(KERN_ERR "Invalid chain id\n");
1361 /* Check if the chain exists */
1362 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1363 printk(KERN_ERR "Chain doesn't exists\n");
1367 channels = dma_linked_lch[chain_id].linked_dmach_q;
1368 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1369 dma_chan[channels[i]].next_linked_ch = -1;
1370 dma_chan[channels[i]].prev_linked_ch = -1;
1371 dma_chan[channels[i]].chain_id = -1;
1372 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1373 omap_free_dma(channels[i]);
1378 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1379 dma_linked_lch[chain_id].chain_mode = -1;
1380 dma_linked_lch[chain_id].chain_state = -1;
1384 EXPORT_SYMBOL(omap_free_dma_chain);
1387 * @brief omap_dma_chain_status - Check if the chain is in
1388 * active / inactive state.
1391 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1394 int omap_dma_chain_status(int chain_id)
1396 /* Check for input params */
1397 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1398 printk(KERN_ERR "Invalid chain id\n");
1402 /* Check if the chain exists */
1403 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1404 printk(KERN_ERR "Chain doesn't exists\n");
1407 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1408 dma_linked_lch[chain_id].q_count);
1410 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1411 return OMAP_DMA_CHAIN_INACTIVE;
1413 return OMAP_DMA_CHAIN_ACTIVE;
1415 EXPORT_SYMBOL(omap_dma_chain_status);
1418 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1419 * set the params and start the transfer.
1422 * @param src_start - buffer start address
1423 * @param dest_start - Dest address
1425 * @param frame_count
1426 * @param callbk_data - channel callback parameter data.
1428 * @return - Success : 0
1429 * Failure: -EINVAL/-EBUSY
1431 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1432 int elem_count, int frame_count, void *callbk_data)
1439 * if buffer size is less than 1 then there is
1440 * no use of starting the chain
1442 if (elem_count < 1) {
1443 printk(KERN_ERR "Invalid buffer size\n");
1447 /* Check for input params */
1448 if (unlikely((chain_id < 0
1449 || chain_id >= dma_lch_count))) {
1450 printk(KERN_ERR "Invalid chain id\n");
1454 /* Check if the chain exists */
1455 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1456 printk(KERN_ERR "Chain doesn't exist\n");
1460 /* Check if all the channels in chain are in use */
1461 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1464 /* Frame count may be negative in case of indexed transfers */
1465 channels = dma_linked_lch[chain_id].linked_dmach_q;
1467 /* Get a free channel */
1468 lch = channels[dma_linked_lch[chain_id].q_tail];
1470 /* Store the callback data */
1471 dma_chan[lch].data = callbk_data;
1473 /* Increment the q_tail */
1474 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1476 /* Set the params to the free channel */
1478 dma_write(src_start, CSSA(lch));
1479 if (dest_start != 0)
1480 dma_write(dest_start, CDSA(lch));
1482 /* Write the buffer size */
1483 dma_write(elem_count, CEN(lch));
1484 dma_write(frame_count, CFN(lch));
1487 * If the chain is dynamically linked,
1488 * then we may have to start the chain if its not active
1490 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1493 * In Dynamic chain, if the chain is not started,
1496 if (dma_linked_lch[chain_id].chain_state ==
1497 DMA_CHAIN_NOTSTARTED) {
1498 /* Enable the link in previous channel */
1499 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1501 enable_lnk(dma_chan[lch].prev_linked_ch);
1502 dma_chan[lch].state = DMA_CH_QUEUED;
1506 * Chain is already started, make sure its active,
1507 * if not then start the chain
1512 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1514 enable_lnk(dma_chan[lch].prev_linked_ch);
1515 dma_chan[lch].state = DMA_CH_QUEUED;
1517 if (0 == ((1 << 7) & dma_read(
1518 CCR(dma_chan[lch].prev_linked_ch)))) {
1519 disable_lnk(dma_chan[lch].
1521 pr_debug("\n prev ch is stopped\n");
1526 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1528 enable_lnk(dma_chan[lch].prev_linked_ch);
1529 dma_chan[lch].state = DMA_CH_QUEUED;
1532 omap_enable_channel_irq(lch);
1534 l = dma_read(CCR(lch));
1536 if ((0 == (l & (1 << 24))))
1540 if (start_dma == 1) {
1541 if (0 == (l & (1 << 7))) {
1543 dma_chan[lch].state = DMA_CH_STARTED;
1544 pr_debug("starting %d\n", lch);
1545 dma_write(l, CCR(lch));
1549 if (0 == (l & (1 << 7)))
1550 dma_write(l, CCR(lch));
1552 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1558 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1561 * @brief omap_start_dma_chain_transfers - Start the chain
1565 * @return - Success : 0
1566 * Failure : -EINVAL/-EBUSY
1568 int omap_start_dma_chain_transfers(int chain_id)
1573 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1574 printk(KERN_ERR "Invalid chain id\n");
1578 channels = dma_linked_lch[chain_id].linked_dmach_q;
1580 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1581 printk(KERN_ERR "Chain is already started\n");
1585 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1586 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1588 enable_lnk(channels[i]);
1589 omap_enable_channel_irq(channels[i]);
1592 omap_enable_channel_irq(channels[0]);
1595 l = dma_read(CCR(channels[0]));
1597 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1598 dma_chan[channels[0]].state = DMA_CH_STARTED;
1600 if ((0 == (l & (1 << 24))))
1604 dma_write(l, CCR(channels[0]));
1606 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1610 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1613 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1617 * @return - Success : 0
1620 int omap_stop_dma_chain_transfers(int chain_id)
1626 /* Check for input params */
1627 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1628 printk(KERN_ERR "Invalid chain id\n");
1632 /* Check if the chain exists */
1633 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1634 printk(KERN_ERR "Chain doesn't exists\n");
1637 channels = dma_linked_lch[chain_id].linked_dmach_q;
1641 * Special programming model needed to disable DMA before end of block
1643 sys_cf = dma_read(OCP_SYSCONFIG);
1645 /* Middle mode reg set no Standby */
1646 l &= ~((1 << 12)|(1 << 13));
1647 dma_write(l, OCP_SYSCONFIG);
1649 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1651 /* Stop the Channel transmission */
1652 l = dma_read(CCR(channels[i]));
1654 dma_write(l, CCR(channels[i]));
1656 /* Disable the link in all the channels */
1657 disable_lnk(channels[i]);
1658 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1661 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1663 /* Reset the Queue pointers */
1664 OMAP_DMA_CHAIN_QINIT(chain_id);
1666 /* Errata - put in the old value */
1667 dma_write(sys_cf, OCP_SYSCONFIG);
1671 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1673 /* Get the index of the ongoing DMA in chain */
1675 * @brief omap_get_dma_chain_index - Get the element and frame index
1676 * of the ongoing DMA in chain
1679 * @param ei - Element index
1680 * @param fi - Frame index
1682 * @return - Success : 0
1685 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1690 /* Check for input params */
1691 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1692 printk(KERN_ERR "Invalid chain id\n");
1696 /* Check if the chain exists */
1697 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1698 printk(KERN_ERR "Chain doesn't exists\n");
1704 channels = dma_linked_lch[chain_id].linked_dmach_q;
1706 /* Get the current channel */
1707 lch = channels[dma_linked_lch[chain_id].q_head];
1709 *ei = dma_read(CCEN(lch));
1710 *fi = dma_read(CCFN(lch));
1714 EXPORT_SYMBOL(omap_get_dma_chain_index);
1717 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1718 * ongoing DMA in chain
1722 * @return - Success : Destination position
1725 int omap_get_dma_chain_dst_pos(int chain_id)
1730 /* Check for input params */
1731 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1732 printk(KERN_ERR "Invalid chain id\n");
1736 /* Check if the chain exists */
1737 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1738 printk(KERN_ERR "Chain doesn't exists\n");
1742 channels = dma_linked_lch[chain_id].linked_dmach_q;
1744 /* Get the current channel */
1745 lch = channels[dma_linked_lch[chain_id].q_head];
1747 return dma_read(CDAC(lch));
1749 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1752 * @brief omap_get_dma_chain_src_pos - Get the source position
1753 * of the ongoing DMA in chain
1756 * @return - Success : Destination position
1759 int omap_get_dma_chain_src_pos(int chain_id)
1764 /* Check for input params */
1765 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1766 printk(KERN_ERR "Invalid chain id\n");
1770 /* Check if the chain exists */
1771 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1772 printk(KERN_ERR "Chain doesn't exists\n");
1776 channels = dma_linked_lch[chain_id].linked_dmach_q;
1778 /* Get the current channel */
1779 lch = channels[dma_linked_lch[chain_id].q_head];
1781 return dma_read(CSAC(lch));
1783 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1784 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1786 /*----------------------------------------------------------------------------*/
1788 #ifdef CONFIG_ARCH_OMAP1
1790 static int omap1_dma_handle_ch(int ch)
1794 if (enable_1510_mode && ch >= 6) {
1795 csr = dma_chan[ch].saved_csr;
1796 dma_chan[ch].saved_csr = 0;
1798 csr = dma_read(CSR(ch));
1799 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1800 dma_chan[ch + 6].saved_csr = csr >> 7;
1803 if ((csr & 0x3f) == 0)
1805 if (unlikely(dma_chan[ch].dev_id == -1)) {
1806 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1807 "%d (CSR %04x)\n", ch, csr);
1810 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1811 printk(KERN_WARNING "DMA timeout with device %d\n",
1812 dma_chan[ch].dev_id);
1813 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1814 printk(KERN_WARNING "DMA synchronization event drop occurred "
1815 "with device %d\n", dma_chan[ch].dev_id);
1816 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1817 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1818 if (likely(dma_chan[ch].callback != NULL))
1819 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1824 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1826 int ch = ((int) dev_id) - 1;
1830 int handled_now = 0;
1832 handled_now += omap1_dma_handle_ch(ch);
1833 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1834 handled_now += omap1_dma_handle_ch(ch + 6);
1837 handled += handled_now;
1840 return handled ? IRQ_HANDLED : IRQ_NONE;
1844 #define omap1_dma_irq_handler NULL
1847 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1849 static int omap2_dma_handle_ch(int ch)
1851 u32 status = dma_read(CSR(ch));
1854 if (printk_ratelimit())
1855 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1857 dma_write(1 << ch, IRQSTATUS_L0);
1860 if (unlikely(dma_chan[ch].dev_id == -1)) {
1861 if (printk_ratelimit())
1862 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1863 "channel %d\n", status, ch);
1866 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1868 "DMA synchronization event drop occurred with device "
1869 "%d\n", dma_chan[ch].dev_id);
1870 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1871 printk(KERN_INFO "DMA transaction error with device %d\n",
1872 dma_chan[ch].dev_id);
1873 if (cpu_class_is_omap2()) {
1874 /* Errata: sDMA Channel is not disabled
1875 * after a transaction error. So we explicitely
1876 * disable the channel
1880 ccr = dma_read(CCR(ch));
1881 ccr &= ~OMAP_DMA_CCR_EN;
1882 dma_write(ccr, CCR(ch));
1883 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1886 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1887 printk(KERN_INFO "DMA secure error with device %d\n",
1888 dma_chan[ch].dev_id);
1889 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1890 printk(KERN_INFO "DMA misaligned error with device %d\n",
1891 dma_chan[ch].dev_id);
1893 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1894 dma_write(1 << ch, IRQSTATUS_L0);
1896 /* If the ch is not chained then chain_id will be -1 */
1897 if (dma_chan[ch].chain_id != -1) {
1898 int chain_id = dma_chan[ch].chain_id;
1899 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1900 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1901 dma_chan[dma_chan[ch].next_linked_ch].state =
1903 if (dma_linked_lch[chain_id].chain_mode ==
1904 OMAP_DMA_DYNAMIC_CHAIN)
1907 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1908 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1910 status = dma_read(CSR(ch));
1913 dma_write(status, CSR(ch));
1915 if (likely(dma_chan[ch].callback != NULL))
1916 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1921 /* STATUS register count is from 1-32 while our is 0-31 */
1922 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1924 u32 val, enable_reg;
1927 val = dma_read(IRQSTATUS_L0);
1929 if (printk_ratelimit())
1930 printk(KERN_WARNING "Spurious DMA IRQ\n");
1933 enable_reg = dma_read(IRQENABLE_L0);
1934 val &= enable_reg; /* Dispatch only relevant interrupts */
1935 for (i = 0; i < dma_lch_count && val != 0; i++) {
1937 omap2_dma_handle_ch(i);
1944 static struct irqaction omap24xx_dma_irq = {
1946 .handler = omap2_dma_irq_handler,
1947 .flags = IRQF_DISABLED
1951 static struct irqaction omap24xx_dma_irq;
1954 /*----------------------------------------------------------------------------*/
1956 static struct lcd_dma_info {
1959 void (*callback)(u16 status, void *data);
1963 unsigned long addr, size;
1964 int rotate, data_type, xres, yres;
1970 int single_transfer;
1973 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1976 lcd_dma.addr = addr;
1977 lcd_dma.data_type = data_type;
1978 lcd_dma.xres = fb_xres;
1979 lcd_dma.yres = fb_yres;
1981 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1983 void omap_set_lcd_dma_src_port(int port)
1985 lcd_dma.src_port = port;
1988 void omap_set_lcd_dma_ext_controller(int external)
1990 lcd_dma.ext_ctrl = external;
1992 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1994 void omap_set_lcd_dma_single_transfer(int single)
1996 lcd_dma.single_transfer = single;
1998 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2000 void omap_set_lcd_dma_b1_rotation(int rotate)
2002 if (omap_dma_in_1510_mode()) {
2003 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
2007 lcd_dma.rotate = rotate;
2009 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2011 void omap_set_lcd_dma_b1_mirror(int mirror)
2013 if (omap_dma_in_1510_mode()) {
2014 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
2017 lcd_dma.mirror = mirror;
2019 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2021 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2023 if (omap_dma_in_1510_mode()) {
2024 printk(KERN_ERR "DMA virtual resulotion is not supported "
2028 lcd_dma.vxres = vxres;
2030 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2032 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2034 if (omap_dma_in_1510_mode()) {
2035 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2038 lcd_dma.xscale = xscale;
2039 lcd_dma.yscale = yscale;
2041 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2043 static void set_b1_regs(void)
2045 unsigned long top, bottom;
2048 unsigned long en, fn;
2050 unsigned long vxres;
2051 unsigned int xscale, yscale;
2053 switch (lcd_dma.data_type) {
2054 case OMAP_DMA_DATA_TYPE_S8:
2057 case OMAP_DMA_DATA_TYPE_S16:
2060 case OMAP_DMA_DATA_TYPE_S32:
2068 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2069 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2070 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2071 BUG_ON(vxres < lcd_dma.xres);
2073 #define PIXADDR(x, y) (lcd_dma.addr + \
2074 ((y) * vxres * yscale + (x) * xscale) * es)
2075 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2077 switch (lcd_dma.rotate) {
2079 if (!lcd_dma.mirror) {
2080 top = PIXADDR(0, 0);
2081 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2082 /* 1510 DMA requires the bottom address to be 2 more
2083 * than the actual last memory access location. */
2084 if (omap_dma_in_1510_mode() &&
2085 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2087 ei = PIXSTEP(0, 0, 1, 0);
2088 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2090 top = PIXADDR(lcd_dma.xres - 1, 0);
2091 bottom = PIXADDR(0, lcd_dma.yres - 1);
2092 ei = PIXSTEP(1, 0, 0, 0);
2093 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2099 if (!lcd_dma.mirror) {
2100 top = PIXADDR(0, lcd_dma.yres - 1);
2101 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2102 ei = PIXSTEP(0, 1, 0, 0);
2103 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2105 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2106 bottom = PIXADDR(0, 0);
2107 ei = PIXSTEP(0, 1, 0, 0);
2108 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2114 if (!lcd_dma.mirror) {
2115 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2116 bottom = PIXADDR(0, 0);
2117 ei = PIXSTEP(1, 0, 0, 0);
2118 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2120 top = PIXADDR(0, lcd_dma.yres - 1);
2121 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2122 ei = PIXSTEP(0, 0, 1, 0);
2123 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2129 if (!lcd_dma.mirror) {
2130 top = PIXADDR(lcd_dma.xres - 1, 0);
2131 bottom = PIXADDR(0, lcd_dma.yres - 1);
2132 ei = PIXSTEP(0, 0, 0, 1);
2133 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2135 top = PIXADDR(0, 0);
2136 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2137 ei = PIXSTEP(0, 0, 0, 1);
2138 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2145 return; /* Suppress warning about uninitialized vars */
2148 if (omap_dma_in_1510_mode()) {
2149 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2150 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2151 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2152 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2158 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2159 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2160 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2161 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2163 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2164 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2166 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2168 w |= lcd_dma.data_type;
2169 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2171 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2172 /* Always set the source port as SDRAM for now*/
2174 if (lcd_dma.callback != NULL)
2175 w |= 1 << 1; /* Block interrupt enable */
2178 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2180 if (!(lcd_dma.rotate || lcd_dma.mirror ||
2181 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2184 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2185 /* Set the double-indexed addressing mode */
2187 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2189 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2190 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2191 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2194 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2198 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2199 if (unlikely(!(w & (1 << 3)))) {
2200 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2205 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2207 if (lcd_dma.callback != NULL)
2208 lcd_dma.callback(w, lcd_dma.cb_data);
2213 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2216 spin_lock_irq(&lcd_dma.lock);
2217 if (lcd_dma.reserved) {
2218 spin_unlock_irq(&lcd_dma.lock);
2219 printk(KERN_ERR "LCD DMA channel already reserved\n");
2223 lcd_dma.reserved = 1;
2224 spin_unlock_irq(&lcd_dma.lock);
2225 lcd_dma.callback = callback;
2226 lcd_dma.cb_data = data;
2228 lcd_dma.single_transfer = 0;
2234 lcd_dma.ext_ctrl = 0;
2235 lcd_dma.src_port = 0;
2239 EXPORT_SYMBOL(omap_request_lcd_dma);
2241 void omap_free_lcd_dma(void)
2243 spin_lock(&lcd_dma.lock);
2244 if (!lcd_dma.reserved) {
2245 spin_unlock(&lcd_dma.lock);
2246 printk(KERN_ERR "LCD DMA is not reserved\n");
2250 if (!enable_1510_mode)
2251 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2252 OMAP1610_DMA_LCD_CCR);
2253 lcd_dma.reserved = 0;
2254 spin_unlock(&lcd_dma.lock);
2256 EXPORT_SYMBOL(omap_free_lcd_dma);
2258 void omap_enable_lcd_dma(void)
2263 * Set the Enable bit only if an external controller is
2264 * connected. Otherwise the OMAP internal controller will
2265 * start the transfer when it gets enabled.
2267 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2270 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2272 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2276 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2278 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2280 EXPORT_SYMBOL(omap_enable_lcd_dma);
2282 void omap_setup_lcd_dma(void)
2284 BUG_ON(lcd_dma.active);
2285 if (!enable_1510_mode) {
2286 /* Set some reasonable defaults */
2287 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2288 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2289 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2292 if (!enable_1510_mode) {
2295 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2297 * If DMA was already active set the end_prog bit to have
2298 * the programmed register set loaded into the active
2301 w |= 1 << 11; /* End_prog */
2302 if (!lcd_dma.single_transfer)
2303 w |= (3 << 8); /* Auto_init, repeat */
2304 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2307 EXPORT_SYMBOL(omap_setup_lcd_dma);
2309 void omap_stop_lcd_dma(void)
2314 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2317 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2319 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2321 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2323 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2325 EXPORT_SYMBOL(omap_stop_lcd_dma);
2327 /*----------------------------------------------------------------------------*/
2329 static int __init omap_init_dma(void)
2333 if (cpu_class_is_omap1()) {
2334 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
2335 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2336 } else if (cpu_is_omap24xx()) {
2337 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
2338 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2339 } else if (cpu_is_omap34xx()) {
2340 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
2341 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2343 pr_err("DMA init failed for unsupported omap\n");
2347 if (cpu_class_is_omap2() && omap_dma_reserve_channels
2348 && (omap_dma_reserve_channels <= dma_lch_count))
2349 dma_lch_count = omap_dma_reserve_channels;
2351 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2356 if (cpu_class_is_omap2()) {
2357 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2358 dma_lch_count, GFP_KERNEL);
2359 if (!dma_linked_lch) {
2365 if (cpu_is_omap15xx()) {
2366 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2368 enable_1510_mode = 1;
2369 } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2370 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2372 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2373 (dma_read(CAPS_0_U) << 16) |
2375 (dma_read(CAPS_1_U) << 16) |
2377 dma_read(CAPS_2), dma_read(CAPS_3),
2379 if (!enable_1510_mode) {
2382 /* Disable OMAP 3.0/3.1 compatibility mode. */
2386 dma_chan_count = 16;
2389 if (cpu_is_omap16xx()) {
2392 /* this would prevent OMAP sleep */
2393 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2395 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2397 } else if (cpu_class_is_omap2()) {
2398 u8 revision = dma_read(REVISION) & 0xff;
2399 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2400 revision >> 4, revision & 0xf);
2401 dma_chan_count = dma_lch_count;
2407 spin_lock_init(&lcd_dma.lock);
2408 spin_lock_init(&dma_chan_lock);
2410 for (ch = 0; ch < dma_chan_count; ch++) {
2412 dma_chan[ch].dev_id = -1;
2413 dma_chan[ch].next_lch = -1;
2415 if (ch >= 6 && enable_1510_mode)
2418 if (cpu_class_is_omap1()) {
2420 * request_irq() doesn't like dev_id (ie. ch) being
2421 * zero, so we have to kludge around this.
2423 r = request_irq(omap1_dma_irq[ch],
2424 omap1_dma_irq_handler, 0, "DMA",
2429 printk(KERN_ERR "unable to request IRQ %d "
2430 "for DMA (error %d)\n",
2431 omap1_dma_irq[ch], r);
2432 for (i = 0; i < ch; i++)
2433 free_irq(omap1_dma_irq[i],
2440 if (cpu_is_omap2430() || cpu_is_omap34xx())
2441 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2442 DMA_DEFAULT_FIFO_DEPTH, 0);
2444 if (cpu_class_is_omap2())
2445 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2447 /* FIXME: Update LCD DMA to work on 24xx */
2448 if (cpu_class_is_omap1()) {
2449 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2454 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2456 for (i = 0; i < dma_chan_count; i++)
2457 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2465 arch_initcall(omap_init_dma);
2468 * Reserve the omap SDMA channels using cmdline bootarg
2469 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2471 static int __init omap_dma_cmdline_reserve_ch(char *str)
2473 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2474 omap_dma_reserve_channels = 0;
2478 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);