2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Support functions for the OMAP internal DMA channels.
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <linux/omap-dma.h>
42 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
43 * channels that an instance of the SDMA IP block can support. Used
44 * to size arrays. (The actual maximum on a particular SoC may be less
45 * than this -- for example, OMAP1 SDMA instances only support 17 logical
48 #define MAX_LOGICAL_DMA_CH_COUNT 32
52 #ifndef CONFIG_ARCH_OMAP1
53 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
54 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
57 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
60 #define OMAP_DMA_ACTIVE 0x01
61 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
63 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
65 static struct omap_system_dma_plat_info *p;
66 static struct omap_dma_dev_attr *d;
67 static void omap_clear_dma(int lch);
68 static int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
69 unsigned char write_prio);
70 static int enable_1510_mode;
73 static struct omap_dma_global_context_registers {
76 u32 dma_ocp_sysconfig;
78 } omap_dma_global_context;
80 struct dma_link_info {
82 int no_of_lchs_linked;
93 static struct dma_link_info *dma_linked_lch;
95 #ifndef CONFIG_ARCH_OMAP1
97 /* Chain handling macros */
98 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
100 dma_linked_lch[chain_id].q_head = \
101 dma_linked_lch[chain_id].q_tail = \
102 dma_linked_lch[chain_id].q_count = 0; \
104 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
105 (dma_linked_lch[chain_id].no_of_lchs_linked == \
106 dma_linked_lch[chain_id].q_count)
107 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
109 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
110 dma_linked_lch[chain_id].q_count) \
112 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
113 (0 == dma_linked_lch[chain_id].q_count)
114 #define __OMAP_DMA_CHAIN_INCQ(end) \
115 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
116 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
118 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
119 dma_linked_lch[chain_id].q_count--; \
122 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
124 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
125 dma_linked_lch[chain_id].q_count++; \
129 static int dma_lch_count;
130 static int dma_chan_count;
131 static int omap_dma_reserve_channels;
133 static spinlock_t dma_chan_lock;
134 static struct omap_dma_lch *dma_chan;
136 static inline void disable_lnk(int lch);
137 static void omap_disable_channel_irq(int lch);
138 static inline void omap_enable_channel_irq(int lch);
140 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
143 #ifdef CONFIG_ARCH_OMAP15XX
144 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
145 static int omap_dma_in_1510_mode(void)
147 return enable_1510_mode;
150 #define omap_dma_in_1510_mode() 0
153 #ifdef CONFIG_ARCH_OMAP1
154 static inline void set_gdma_dev(int req, int dev)
156 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
157 int shift = ((req - 1) % 5) * 6;
161 l &= ~(0x3f << shift);
162 l |= (dev - 1) << shift;
166 #define set_gdma_dev(req, dev) do {} while (0)
167 #define omap_readl(reg) 0
168 #define omap_writel(val, reg) do {} while (0)
171 #ifdef CONFIG_ARCH_OMAP1
172 void omap_set_dma_priority(int lch, int dst_port, int priority)
179 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
180 reg = OMAP_TC_OCPT1_PRIOR;
182 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
183 reg = OMAP_TC_OCPT2_PRIOR;
185 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
186 reg = OMAP_TC_EMIFF_PRIOR;
188 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
189 reg = OMAP_TC_EMIFS_PRIOR;
197 l |= (priority & 0xf) << 8;
203 #ifdef CONFIG_ARCH_OMAP2PLUS
204 void omap_set_dma_priority(int lch, int dst_port, int priority)
208 ccr = p->dma_read(CCR, lch);
213 p->dma_write(ccr, CCR, lch);
216 EXPORT_SYMBOL(omap_set_dma_priority);
218 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
219 int frame_count, int sync_mode,
220 int dma_trigger, int src_or_dst_synch)
224 l = p->dma_read(CSDP, lch);
227 p->dma_write(l, CSDP, lch);
232 ccr = p->dma_read(CCR, lch);
234 if (sync_mode == OMAP_DMA_SYNC_FRAME)
236 p->dma_write(ccr, CCR, lch);
238 ccr = p->dma_read(CCR2, lch);
240 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
242 p->dma_write(ccr, CCR2, lch);
245 if (dma_omap2plus() && dma_trigger) {
248 val = p->dma_read(CCR, lch);
250 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
251 val &= ~((1 << 23) | (3 << 19) | 0x1f);
252 val |= (dma_trigger & ~0x1f) << 14;
253 val |= dma_trigger & 0x1f;
255 if (sync_mode & OMAP_DMA_SYNC_FRAME)
260 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
265 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
266 val &= ~(1 << 24); /* dest synch */
267 val |= (1 << 23); /* Prefetch */
268 } else if (src_or_dst_synch) {
269 val |= 1 << 24; /* source synch */
271 val &= ~(1 << 24); /* dest synch */
273 p->dma_write(val, CCR, lch);
276 p->dma_write(elem_count, CEN, lch);
277 p->dma_write(frame_count, CFN, lch);
279 EXPORT_SYMBOL(omap_set_dma_transfer_params);
281 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
283 if (dma_omap2plus()) {
286 csdp = p->dma_read(CSDP, lch);
287 csdp &= ~(0x3 << 16);
288 csdp |= (mode << 16);
289 p->dma_write(csdp, CSDP, lch);
292 EXPORT_SYMBOL(omap_set_dma_write_mode);
294 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
296 if (dma_omap1() && !dma_omap15xx()) {
299 l = p->dma_read(LCH_CTRL, lch);
302 p->dma_write(l, LCH_CTRL, lch);
305 EXPORT_SYMBOL(omap_set_dma_channel_mode);
307 /* Note that src_port is only for omap1 */
308 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
309 unsigned long src_start,
310 int src_ei, int src_fi)
317 w = p->dma_read(CSDP, lch);
320 p->dma_write(w, CSDP, lch);
323 l = p->dma_read(CCR, lch);
325 l |= src_amode << 12;
326 p->dma_write(l, CCR, lch);
328 p->dma_write(src_start, CSSA, lch);
330 p->dma_write(src_ei, CSEI, lch);
331 p->dma_write(src_fi, CSFI, lch);
333 EXPORT_SYMBOL(omap_set_dma_src_params);
335 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
337 omap_set_dma_transfer_params(lch, params->data_type,
338 params->elem_count, params->frame_count,
339 params->sync_mode, params->trigger,
340 params->src_or_dst_synch);
341 omap_set_dma_src_params(lch, params->src_port,
342 params->src_amode, params->src_start,
343 params->src_ei, params->src_fi);
345 omap_set_dma_dest_params(lch, params->dst_port,
346 params->dst_amode, params->dst_start,
347 params->dst_ei, params->dst_fi);
348 if (params->read_prio || params->write_prio)
349 omap_dma_set_prio_lch(lch, params->read_prio,
352 EXPORT_SYMBOL(omap_set_dma_params);
354 void omap_set_dma_src_data_pack(int lch, int enable)
358 l = p->dma_read(CSDP, lch);
362 p->dma_write(l, CSDP, lch);
364 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
366 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
368 unsigned int burst = 0;
371 l = p->dma_read(CSDP, lch);
374 switch (burst_mode) {
375 case OMAP_DMA_DATA_BURST_DIS:
377 case OMAP_DMA_DATA_BURST_4:
383 case OMAP_DMA_DATA_BURST_8:
384 if (dma_omap2plus()) {
389 * not supported by current hardware on OMAP1
393 case OMAP_DMA_DATA_BURST_16:
394 if (dma_omap2plus()) {
399 * OMAP1 don't support burst 16
407 p->dma_write(l, CSDP, lch);
409 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
411 /* Note that dest_port is only for OMAP1 */
412 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
413 unsigned long dest_start,
414 int dst_ei, int dst_fi)
419 l = p->dma_read(CSDP, lch);
422 p->dma_write(l, CSDP, lch);
425 l = p->dma_read(CCR, lch);
427 l |= dest_amode << 14;
428 p->dma_write(l, CCR, lch);
430 p->dma_write(dest_start, CDSA, lch);
432 p->dma_write(dst_ei, CDEI, lch);
433 p->dma_write(dst_fi, CDFI, lch);
435 EXPORT_SYMBOL(omap_set_dma_dest_params);
437 void omap_set_dma_dest_data_pack(int lch, int enable)
441 l = p->dma_read(CSDP, lch);
445 p->dma_write(l, CSDP, lch);
447 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
449 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
451 unsigned int burst = 0;
454 l = p->dma_read(CSDP, lch);
457 switch (burst_mode) {
458 case OMAP_DMA_DATA_BURST_DIS:
460 case OMAP_DMA_DATA_BURST_4:
466 case OMAP_DMA_DATA_BURST_8:
472 case OMAP_DMA_DATA_BURST_16:
473 if (dma_omap2plus()) {
478 * OMAP1 don't support burst 16
482 printk(KERN_ERR "Invalid DMA burst mode\n");
487 p->dma_write(l, CSDP, lch);
489 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
491 static inline void omap_enable_channel_irq(int lch)
495 p->dma_read(CSR, lch);
497 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
499 /* Enable some nice interrupts. */
500 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
503 static inline void omap_disable_channel_irq(int lch)
505 /* disable channel interrupts */
506 p->dma_write(0, CICR, lch);
509 p->dma_read(CSR, lch);
511 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
514 void omap_enable_dma_irq(int lch, u16 bits)
516 dma_chan[lch].enabled_irqs |= bits;
518 EXPORT_SYMBOL(omap_enable_dma_irq);
520 void omap_disable_dma_irq(int lch, u16 bits)
522 dma_chan[lch].enabled_irqs &= ~bits;
524 EXPORT_SYMBOL(omap_disable_dma_irq);
526 static inline void enable_lnk(int lch)
530 l = p->dma_read(CLNK_CTRL, lch);
535 /* Set the ENABLE_LNK bits */
536 if (dma_chan[lch].next_lch != -1)
537 l = dma_chan[lch].next_lch | (1 << 15);
539 #ifndef CONFIG_ARCH_OMAP1
541 if (dma_chan[lch].next_linked_ch != -1)
542 l = dma_chan[lch].next_linked_ch | (1 << 15);
545 p->dma_write(l, CLNK_CTRL, lch);
548 static inline void disable_lnk(int lch)
552 l = p->dma_read(CLNK_CTRL, lch);
554 /* Disable interrupts */
555 omap_disable_channel_irq(lch);
558 /* Set the STOP_LNK bit */
562 if (dma_omap2plus()) {
563 /* Clear the ENABLE_LNK bit */
567 p->dma_write(l, CLNK_CTRL, lch);
568 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
571 static inline void omap2_enable_irq_lch(int lch)
579 spin_lock_irqsave(&dma_chan_lock, flags);
580 /* clear IRQ STATUS */
581 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
582 /* Enable interrupt */
583 val = p->dma_read(IRQENABLE_L0, lch);
585 p->dma_write(val, IRQENABLE_L0, lch);
586 spin_unlock_irqrestore(&dma_chan_lock, flags);
589 static inline void omap2_disable_irq_lch(int lch)
597 spin_lock_irqsave(&dma_chan_lock, flags);
598 /* Disable interrupt */
599 val = p->dma_read(IRQENABLE_L0, lch);
601 p->dma_write(val, IRQENABLE_L0, lch);
602 /* clear IRQ STATUS */
603 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
604 spin_unlock_irqrestore(&dma_chan_lock, flags);
607 int omap_request_dma(int dev_id, const char *dev_name,
608 void (*callback)(int lch, u16 ch_status, void *data),
609 void *data, int *dma_ch_out)
611 int ch, free_ch = -1;
613 struct omap_dma_lch *chan;
615 WARN(strcmp(dev_name, "DMA engine"), "Using deprecated platform DMA API - please update to DMA engine");
617 spin_lock_irqsave(&dma_chan_lock, flags);
618 for (ch = 0; ch < dma_chan_count; ch++) {
619 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
621 /* Exit after first free channel found */
626 spin_unlock_irqrestore(&dma_chan_lock, flags);
629 chan = dma_chan + free_ch;
630 chan->dev_id = dev_id;
632 if (p->clear_lch_regs)
633 p->clear_lch_regs(free_ch);
636 omap_clear_dma(free_ch);
638 spin_unlock_irqrestore(&dma_chan_lock, flags);
640 chan->dev_name = dev_name;
641 chan->callback = callback;
645 #ifndef CONFIG_ARCH_OMAP1
646 if (dma_omap2plus()) {
648 chan->next_linked_ch = -1;
652 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
655 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
656 else if (dma_omap2plus())
657 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
658 OMAP2_DMA_TRANS_ERR_IRQ;
660 if (dma_omap16xx()) {
661 /* If the sync device is set, configure it dynamically. */
663 set_gdma_dev(free_ch + 1, dev_id);
664 dev_id = free_ch + 1;
667 * Disable the 1510 compatibility mode and set the sync device
670 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
671 } else if (dma_omap1()) {
672 p->dma_write(dev_id, CCR, free_ch);
675 if (dma_omap2plus()) {
676 omap_enable_channel_irq(free_ch);
677 omap2_enable_irq_lch(free_ch);
680 *dma_ch_out = free_ch;
684 EXPORT_SYMBOL(omap_request_dma);
686 void omap_free_dma(int lch)
690 if (dma_chan[lch].dev_id == -1) {
691 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
696 /* Disable interrupt for logical channel */
698 omap2_disable_irq_lch(lch);
700 /* Disable all DMA interrupts for the channel. */
701 omap_disable_channel_irq(lch);
703 /* Make sure the DMA transfer is stopped. */
704 p->dma_write(0, CCR, lch);
706 /* Clear registers */
710 spin_lock_irqsave(&dma_chan_lock, flags);
711 dma_chan[lch].dev_id = -1;
712 dma_chan[lch].next_lch = -1;
713 dma_chan[lch].callback = NULL;
714 spin_unlock_irqrestore(&dma_chan_lock, flags);
716 EXPORT_SYMBOL(omap_free_dma);
719 * @brief omap_dma_set_global_params : Set global priority settings for dma
722 * @param max_fifo_depth
723 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
724 * DMA_THREAD_RESERVE_ONET
725 * DMA_THREAD_RESERVE_TWOT
726 * DMA_THREAD_RESERVE_THREET
729 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
734 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
738 if (max_fifo_depth == 0)
743 reg = 0xff & max_fifo_depth;
744 reg |= (0x3 & tparams) << 12;
745 reg |= (arb_rate & 0xff) << 16;
747 p->dma_write(reg, GCR, 0);
749 EXPORT_SYMBOL(omap_dma_set_global_params);
752 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
755 * @param read_prio - Read priority
756 * @param write_prio - Write priority
757 * Both of the above can be set with one of the following values :
758 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
761 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
762 unsigned char write_prio)
766 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
767 printk(KERN_ERR "Invalid channel id\n");
770 l = p->dma_read(CCR, lch);
771 l &= ~((1 << 6) | (1 << 26));
772 if (d->dev_caps & IS_RW_PRIORITY)
773 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
775 l |= ((read_prio & 0x1) << 6);
777 p->dma_write(l, CCR, lch);
784 * Clears any DMA state so the DMA engine is ready to restart with new buffers
785 * through omap_start_dma(). Any buffers in flight are discarded.
787 static void omap_clear_dma(int lch)
791 local_irq_save(flags);
793 local_irq_restore(flags);
796 void omap_start_dma(int lch)
801 * The CPC/CDAC register needs to be initialized to zero
802 * before starting dma transfer.
805 p->dma_write(0, CPC, lch);
807 p->dma_write(0, CDAC, lch);
809 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
810 int next_lch, cur_lch;
811 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
813 /* Set the link register of the first channel */
816 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
817 dma_chan_link_map[lch] = 1;
819 cur_lch = dma_chan[lch].next_lch;
821 next_lch = dma_chan[cur_lch].next_lch;
823 /* The loop case: we've been here already */
824 if (dma_chan_link_map[cur_lch])
826 /* Mark the current channel */
827 dma_chan_link_map[cur_lch] = 1;
830 omap_enable_channel_irq(cur_lch);
833 } while (next_lch != -1);
834 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
835 p->dma_write(lch, CLNK_CTRL, lch);
837 omap_enable_channel_irq(lch);
839 l = p->dma_read(CCR, lch);
841 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
842 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
843 l |= OMAP_DMA_CCR_EN;
846 * As dma_write() uses IO accessors which are weakly ordered, there
847 * is no guarantee that data in coherent DMA memory will be visible
848 * to the DMA device. Add a memory barrier here to ensure that any
849 * such data is visible prior to enabling DMA.
852 p->dma_write(l, CCR, lch);
854 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
856 EXPORT_SYMBOL(omap_start_dma);
858 void omap_stop_dma(int lch)
862 /* Disable all interrupts on the channel */
863 omap_disable_channel_irq(lch);
865 l = p->dma_read(CCR, lch);
866 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
867 (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
871 /* Configure No-Standby */
872 l = p->dma_read(OCP_SYSCONFIG, lch);
874 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
875 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
876 p->dma_write(l , OCP_SYSCONFIG, 0);
878 l = p->dma_read(CCR, lch);
879 l &= ~OMAP_DMA_CCR_EN;
880 p->dma_write(l, CCR, lch);
882 /* Wait for sDMA FIFO drain */
883 l = p->dma_read(CCR, lch);
884 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
885 OMAP_DMA_CCR_WR_ACTIVE))) {
888 l = p->dma_read(CCR, lch);
891 pr_err("DMA drain did not complete on lch %d\n", lch);
892 /* Restore OCP_SYSCONFIG */
893 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
895 l &= ~OMAP_DMA_CCR_EN;
896 p->dma_write(l, CCR, lch);
900 * Ensure that data transferred by DMA is visible to any access
901 * after DMA has been disabled. This is important for coherent
906 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
907 int next_lch, cur_lch = lch;
908 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
910 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
912 /* The loop case: we've been here already */
913 if (dma_chan_link_map[cur_lch])
915 /* Mark the current channel */
916 dma_chan_link_map[cur_lch] = 1;
918 disable_lnk(cur_lch);
920 next_lch = dma_chan[cur_lch].next_lch;
922 } while (next_lch != -1);
925 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
927 EXPORT_SYMBOL(omap_stop_dma);
930 * Allows changing the DMA callback function or data. This may be needed if
931 * the driver shares a single DMA channel for multiple dma triggers.
933 int omap_set_dma_callback(int lch,
934 void (*callback)(int lch, u16 ch_status, void *data),
942 spin_lock_irqsave(&dma_chan_lock, flags);
943 if (dma_chan[lch].dev_id == -1) {
944 printk(KERN_ERR "DMA callback for not set for free channel\n");
945 spin_unlock_irqrestore(&dma_chan_lock, flags);
948 dma_chan[lch].callback = callback;
949 dma_chan[lch].data = data;
950 spin_unlock_irqrestore(&dma_chan_lock, flags);
954 EXPORT_SYMBOL(omap_set_dma_callback);
957 * Returns current physical source address for the given DMA channel.
958 * If the channel is running the caller must disable interrupts prior calling
959 * this function and process the returned value before re-enabling interrupt to
960 * prevent races with the interrupt handler. Note that in continuous mode there
961 * is a chance for CSSA_L register overflow between the two reads resulting
962 * in incorrect return value.
964 dma_addr_t omap_get_dma_src_pos(int lch)
966 dma_addr_t offset = 0;
969 offset = p->dma_read(CPC, lch);
971 offset = p->dma_read(CSAC, lch);
973 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
974 offset = p->dma_read(CSAC, lch);
976 if (!dma_omap15xx()) {
978 * CDAC == 0 indicates that the DMA transfer on the channel has
979 * not been started (no data has been transferred so far).
980 * Return the programmed source start address in this case.
982 if (likely(p->dma_read(CDAC, lch)))
983 offset = p->dma_read(CSAC, lch);
985 offset = p->dma_read(CSSA, lch);
989 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
993 EXPORT_SYMBOL(omap_get_dma_src_pos);
996 * Returns current physical destination address for the given DMA channel.
997 * If the channel is running the caller must disable interrupts prior calling
998 * this function and process the returned value before re-enabling interrupt to
999 * prevent races with the interrupt handler. Note that in continuous mode there
1000 * is a chance for CDSA_L register overflow between the two reads resulting
1001 * in incorrect return value.
1003 dma_addr_t omap_get_dma_dst_pos(int lch)
1005 dma_addr_t offset = 0;
1008 offset = p->dma_read(CPC, lch);
1010 offset = p->dma_read(CDAC, lch);
1013 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1014 * read before the DMA controller finished disabling the channel.
1016 if (!dma_omap15xx() && offset == 0) {
1017 offset = p->dma_read(CDAC, lch);
1019 * CDAC == 0 indicates that the DMA transfer on the channel has
1020 * not been started (no data has been transferred so far).
1021 * Return the programmed destination start address in this case.
1023 if (unlikely(!offset))
1024 offset = p->dma_read(CDSA, lch);
1028 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1032 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1034 int omap_get_dma_active_status(int lch)
1036 return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1038 EXPORT_SYMBOL(omap_get_dma_active_status);
1040 int omap_dma_running(void)
1045 if (omap_lcd_dma_running())
1048 for (lch = 0; lch < dma_chan_count; lch++)
1049 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1056 * lch_queue DMA will start right after lch_head one is finished.
1057 * For this DMA link to start, you still need to start (see omap_start_dma)
1058 * the first one. That will fire up the entire queue.
1060 void omap_dma_link_lch(int lch_head, int lch_queue)
1062 if (omap_dma_in_1510_mode()) {
1063 if (lch_head == lch_queue) {
1064 p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1068 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1073 if ((dma_chan[lch_head].dev_id == -1) ||
1074 (dma_chan[lch_queue].dev_id == -1)) {
1075 pr_err("omap_dma: trying to link non requested channels\n");
1079 dma_chan[lch_head].next_lch = lch_queue;
1081 EXPORT_SYMBOL(omap_dma_link_lch);
1083 /*----------------------------------------------------------------------------*/
1085 #ifdef CONFIG_ARCH_OMAP1
1087 static int omap1_dma_handle_ch(int ch)
1091 if (enable_1510_mode && ch >= 6) {
1092 csr = dma_chan[ch].saved_csr;
1093 dma_chan[ch].saved_csr = 0;
1095 csr = p->dma_read(CSR, ch);
1096 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1097 dma_chan[ch + 6].saved_csr = csr >> 7;
1100 if ((csr & 0x3f) == 0)
1102 if (unlikely(dma_chan[ch].dev_id == -1)) {
1103 pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
1107 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1108 pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
1109 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1110 pr_warn("DMA synchronization event drop occurred with device %d\n",
1111 dma_chan[ch].dev_id);
1112 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1113 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1114 if (likely(dma_chan[ch].callback != NULL))
1115 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1120 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1122 int ch = ((int) dev_id) - 1;
1126 int handled_now = 0;
1128 handled_now += omap1_dma_handle_ch(ch);
1129 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1130 handled_now += omap1_dma_handle_ch(ch + 6);
1133 handled += handled_now;
1136 return handled ? IRQ_HANDLED : IRQ_NONE;
1140 #define omap1_dma_irq_handler NULL
1143 #ifdef CONFIG_ARCH_OMAP2PLUS
1145 static int omap2_dma_handle_ch(int ch)
1147 u32 status = p->dma_read(CSR, ch);
1150 if (printk_ratelimit())
1151 pr_warn("Spurious DMA IRQ for lch %d\n", ch);
1152 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1155 if (unlikely(dma_chan[ch].dev_id == -1)) {
1156 if (printk_ratelimit())
1157 pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
1161 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1162 pr_info("DMA synchronization event drop occurred with device %d\n",
1163 dma_chan[ch].dev_id);
1164 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1165 printk(KERN_INFO "DMA transaction error with device %d\n",
1166 dma_chan[ch].dev_id);
1167 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1170 ccr = p->dma_read(CCR, ch);
1171 ccr &= ~OMAP_DMA_CCR_EN;
1172 p->dma_write(ccr, CCR, ch);
1173 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1176 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1177 printk(KERN_INFO "DMA secure error with device %d\n",
1178 dma_chan[ch].dev_id);
1179 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1180 printk(KERN_INFO "DMA misaligned error with device %d\n",
1181 dma_chan[ch].dev_id);
1183 p->dma_write(status, CSR, ch);
1184 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1185 /* read back the register to flush the write */
1186 p->dma_read(IRQSTATUS_L0, ch);
1188 /* If the ch is not chained then chain_id will be -1 */
1189 if (dma_chan[ch].chain_id != -1) {
1190 int chain_id = dma_chan[ch].chain_id;
1191 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1192 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1193 dma_chan[dma_chan[ch].next_linked_ch].state =
1195 if (dma_linked_lch[chain_id].chain_mode ==
1196 OMAP_DMA_DYNAMIC_CHAIN)
1199 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1200 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1202 status = p->dma_read(CSR, ch);
1203 p->dma_write(status, CSR, ch);
1206 if (likely(dma_chan[ch].callback != NULL))
1207 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1212 /* STATUS register count is from 1-32 while our is 0-31 */
1213 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1215 u32 val, enable_reg;
1218 val = p->dma_read(IRQSTATUS_L0, 0);
1220 if (printk_ratelimit())
1221 printk(KERN_WARNING "Spurious DMA IRQ\n");
1224 enable_reg = p->dma_read(IRQENABLE_L0, 0);
1225 val &= enable_reg; /* Dispatch only relevant interrupts */
1226 for (i = 0; i < dma_lch_count && val != 0; i++) {
1228 omap2_dma_handle_ch(i);
1235 static struct irqaction omap24xx_dma_irq = {
1237 .handler = omap2_dma_irq_handler,
1241 static struct irqaction omap24xx_dma_irq;
1244 /*----------------------------------------------------------------------------*/
1247 * Note that we are currently using only IRQENABLE_L0 and L1.
1248 * As the DSP may be using IRQENABLE_L2 and L3, let's not
1249 * touch those for now.
1251 void omap_dma_global_context_save(void)
1253 omap_dma_global_context.dma_irqenable_l0 =
1254 p->dma_read(IRQENABLE_L0, 0);
1255 omap_dma_global_context.dma_irqenable_l1 =
1256 p->dma_read(IRQENABLE_L1, 0);
1257 omap_dma_global_context.dma_ocp_sysconfig =
1258 p->dma_read(OCP_SYSCONFIG, 0);
1259 omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1262 void omap_dma_global_context_restore(void)
1266 p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1267 p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1269 p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1271 p->dma_write(omap_dma_global_context.dma_irqenable_l1,
1274 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1275 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1277 for (ch = 0; ch < dma_chan_count; ch++)
1278 if (dma_chan[ch].dev_id != -1)
1282 struct omap_system_dma_plat_info *omap_get_plat_info(void)
1286 EXPORT_SYMBOL_GPL(omap_get_plat_info);
1288 static int omap_system_dma_probe(struct platform_device *pdev)
1295 p = pdev->dev.platform_data;
1298 "%s: System DMA initialized without platform data\n",
1306 if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
1307 && (omap_dma_reserve_channels < d->lch_count))
1308 d->lch_count = omap_dma_reserve_channels;
1310 dma_lch_count = d->lch_count;
1311 dma_chan_count = dma_lch_count;
1312 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
1314 dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count,
1315 sizeof(struct omap_dma_lch), GFP_KERNEL);
1317 dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
1322 if (dma_omap2plus()) {
1323 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
1324 dma_lch_count, GFP_KERNEL);
1325 if (!dma_linked_lch) {
1327 goto exit_dma_lch_fail;
1331 spin_lock_init(&dma_chan_lock);
1332 for (ch = 0; ch < dma_chan_count; ch++) {
1334 if (dma_omap2plus())
1335 omap2_disable_irq_lch(ch);
1337 dma_chan[ch].dev_id = -1;
1338 dma_chan[ch].next_lch = -1;
1340 if (ch >= 6 && enable_1510_mode)
1345 * request_irq() doesn't like dev_id (ie. ch) being
1346 * zero, so we have to kludge around this.
1348 sprintf(&irq_name[0], "%d", ch);
1349 dma_irq = platform_get_irq_byname(pdev, irq_name);
1353 goto exit_dma_irq_fail;
1356 /* INT_DMA_LCD is handled in lcd_dma.c */
1357 if (dma_irq == INT_DMA_LCD)
1360 ret = request_irq(dma_irq,
1361 omap1_dma_irq_handler, 0, "DMA",
1364 goto exit_dma_irq_fail;
1368 if (d->dev_caps & IS_RW_PRIORITY)
1369 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
1370 DMA_DEFAULT_FIFO_DEPTH, 0);
1372 if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) {
1373 strcpy(irq_name, "0");
1374 dma_irq = platform_get_irq_byname(pdev, irq_name);
1376 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
1378 goto exit_dma_lch_fail;
1380 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
1382 dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
1384 goto exit_dma_lch_fail;
1388 /* reserve dma channels 0 and 1 in high security devices on 34xx */
1389 if (d->dev_caps & HS_CHANNELS_RESERVED) {
1390 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
1391 dma_chan[0].dev_id = 0;
1392 dma_chan[1].dev_id = 1;
1398 dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
1400 for (irq_rel = 0; irq_rel < ch; irq_rel++) {
1401 dma_irq = platform_get_irq(pdev, irq_rel);
1402 free_irq(dma_irq, (void *)(irq_rel + 1));
1409 static int omap_system_dma_remove(struct platform_device *pdev)
1413 if (dma_omap2plus()) {
1415 strcpy(irq_name, "0");
1416 dma_irq = platform_get_irq_byname(pdev, irq_name);
1418 remove_irq(dma_irq, &omap24xx_dma_irq);
1421 for ( ; irq_rel < dma_chan_count; irq_rel++) {
1422 dma_irq = platform_get_irq(pdev, irq_rel);
1423 free_irq(dma_irq, (void *)(irq_rel + 1));
1429 static struct platform_driver omap_system_dma_driver = {
1430 .probe = omap_system_dma_probe,
1431 .remove = omap_system_dma_remove,
1433 .name = "omap_dma_system"
1437 static int __init omap_system_dma_init(void)
1439 return platform_driver_register(&omap_system_dma_driver);
1441 arch_initcall(omap_system_dma_init);
1443 static void __exit omap_system_dma_exit(void)
1445 platform_driver_unregister(&omap_system_dma_driver);
1448 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
1449 MODULE_LICENSE("GPL");
1450 MODULE_ALIAS("platform:" DRIVER_NAME);
1451 MODULE_AUTHOR("Texas Instruments Inc");
1454 * Reserve the omap SDMA channels using cmdline bootarg
1455 * "omap_dma_reserve_ch=". The valid range is 1 to 32
1457 static int __init omap_dma_cmdline_reserve_ch(char *str)
1459 if (get_option(&str, &omap_dma_reserve_channels) != 1)
1460 omap_dma_reserve_channels = 0;
1464 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);