2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Support functions for the OMAP internal DMA channels.
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/sched.h>
27 #include <linux/spinlock.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
35 #include <asm/system.h>
36 #include <mach/hardware.h>
43 #ifndef CONFIG_ARCH_OMAP1
44 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
45 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
48 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
51 #define OMAP_DMA_ACTIVE 0x01
52 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
54 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
56 static int enable_1510_mode;
58 static struct omap_dma_global_context_registers {
60 u32 dma_ocp_sysconfig;
62 } omap_dma_global_context;
70 void (*callback)(int lch, u16 ch_status, void *data);
73 #ifndef CONFIG_ARCH_OMAP1
74 /* required for Dynamic chaining */
85 struct dma_link_info {
87 int no_of_lchs_linked;
98 static struct dma_link_info *dma_linked_lch;
100 #ifndef CONFIG_ARCH_OMAP1
102 /* Chain handling macros */
103 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
105 dma_linked_lch[chain_id].q_head = \
106 dma_linked_lch[chain_id].q_tail = \
107 dma_linked_lch[chain_id].q_count = 0; \
109 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
110 (dma_linked_lch[chain_id].no_of_lchs_linked == \
111 dma_linked_lch[chain_id].q_count)
112 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
114 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
115 dma_linked_lch[chain_id].q_count) \
117 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
118 (0 == dma_linked_lch[chain_id].q_count)
119 #define __OMAP_DMA_CHAIN_INCQ(end) \
120 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
121 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
123 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
124 dma_linked_lch[chain_id].q_count--; \
127 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
129 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
130 dma_linked_lch[chain_id].q_count++; \
134 static int dma_lch_count;
135 static int dma_chan_count;
136 static int omap_dma_reserve_channels;
138 static spinlock_t dma_chan_lock;
139 static struct omap_dma_lch *dma_chan;
140 static void __iomem *omap_dma_base;
142 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
143 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
144 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
145 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
146 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
147 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
150 static inline void disable_lnk(int lch);
151 static void omap_disable_channel_irq(int lch);
152 static inline void omap_enable_channel_irq(int lch);
154 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
157 #define dma_read(reg) \
160 if (cpu_class_is_omap1()) \
161 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
163 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
167 #define dma_write(val, reg) \
169 if (cpu_class_is_omap1()) \
170 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
172 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
175 #ifdef CONFIG_ARCH_OMAP15XX
176 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
177 int omap_dma_in_1510_mode(void)
179 return enable_1510_mode;
182 #define omap_dma_in_1510_mode() 0
185 #ifdef CONFIG_ARCH_OMAP1
186 static inline int get_gdma_dev(int req)
188 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
189 int shift = ((req - 1) % 5) * 6;
191 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
194 static inline void set_gdma_dev(int req, int dev)
196 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
197 int shift = ((req - 1) % 5) * 6;
201 l &= ~(0x3f << shift);
202 l |= (dev - 1) << shift;
206 #define set_gdma_dev(req, dev) do {} while (0)
210 static void clear_lch_regs(int lch)
213 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
215 for (i = 0; i < 0x2c; i += 2)
216 __raw_writew(0, lch_base + i);
219 void omap_set_dma_priority(int lch, int dst_port, int priority)
224 if (cpu_class_is_omap1()) {
226 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
227 reg = OMAP_TC_OCPT1_PRIOR;
229 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
230 reg = OMAP_TC_OCPT2_PRIOR;
232 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
233 reg = OMAP_TC_EMIFF_PRIOR;
235 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
236 reg = OMAP_TC_EMIFS_PRIOR;
244 l |= (priority & 0xf) << 8;
248 if (cpu_class_is_omap2()) {
251 ccr = dma_read(CCR(lch));
256 dma_write(ccr, CCR(lch));
259 EXPORT_SYMBOL(omap_set_dma_priority);
261 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
262 int frame_count, int sync_mode,
263 int dma_trigger, int src_or_dst_synch)
267 l = dma_read(CSDP(lch));
270 dma_write(l, CSDP(lch));
272 if (cpu_class_is_omap1()) {
275 ccr = dma_read(CCR(lch));
277 if (sync_mode == OMAP_DMA_SYNC_FRAME)
279 dma_write(ccr, CCR(lch));
281 ccr = dma_read(CCR2(lch));
283 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
285 dma_write(ccr, CCR2(lch));
288 if (cpu_class_is_omap2() && dma_trigger) {
291 val = dma_read(CCR(lch));
293 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
294 val &= ~((1 << 23) | (3 << 19) | 0x1f);
295 val |= (dma_trigger & ~0x1f) << 14;
296 val |= dma_trigger & 0x1f;
298 if (sync_mode & OMAP_DMA_SYNC_FRAME)
303 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
308 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
309 val &= ~(1 << 24); /* dest synch */
310 val |= (1 << 23); /* Prefetch */
311 } else if (src_or_dst_synch) {
312 val |= 1 << 24; /* source synch */
314 val &= ~(1 << 24); /* dest synch */
316 dma_write(val, CCR(lch));
319 dma_write(elem_count, CEN(lch));
320 dma_write(frame_count, CFN(lch));
322 EXPORT_SYMBOL(omap_set_dma_transfer_params);
324 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
326 BUG_ON(omap_dma_in_1510_mode());
328 if (cpu_class_is_omap1()) {
331 w = dma_read(CCR2(lch));
335 case OMAP_DMA_CONSTANT_FILL:
338 case OMAP_DMA_TRANSPARENT_COPY:
341 case OMAP_DMA_COLOR_DIS:
346 dma_write(w, CCR2(lch));
348 w = dma_read(LCH_CTRL(lch));
350 /* Default is channel type 2D */
352 dma_write((u16)color, COLOR_L(lch));
353 dma_write((u16)(color >> 16), COLOR_U(lch));
354 w |= 1; /* Channel type G */
356 dma_write(w, LCH_CTRL(lch));
359 if (cpu_class_is_omap2()) {
362 val = dma_read(CCR(lch));
363 val &= ~((1 << 17) | (1 << 16));
366 case OMAP_DMA_CONSTANT_FILL:
369 case OMAP_DMA_TRANSPARENT_COPY:
372 case OMAP_DMA_COLOR_DIS:
377 dma_write(val, CCR(lch));
380 dma_write(color, COLOR(lch));
383 EXPORT_SYMBOL(omap_set_dma_color_mode);
385 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
387 if (cpu_class_is_omap2()) {
390 csdp = dma_read(CSDP(lch));
391 csdp &= ~(0x3 << 16);
392 csdp |= (mode << 16);
393 dma_write(csdp, CSDP(lch));
396 EXPORT_SYMBOL(omap_set_dma_write_mode);
398 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
400 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
403 l = dma_read(LCH_CTRL(lch));
406 dma_write(l, LCH_CTRL(lch));
409 EXPORT_SYMBOL(omap_set_dma_channel_mode);
411 /* Note that src_port is only for omap1 */
412 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
413 unsigned long src_start,
414 int src_ei, int src_fi)
418 if (cpu_class_is_omap1()) {
421 w = dma_read(CSDP(lch));
424 dma_write(w, CSDP(lch));
427 l = dma_read(CCR(lch));
429 l |= src_amode << 12;
430 dma_write(l, CCR(lch));
432 if (cpu_class_is_omap1()) {
433 dma_write(src_start >> 16, CSSA_U(lch));
434 dma_write((u16)src_start, CSSA_L(lch));
437 if (cpu_class_is_omap2())
438 dma_write(src_start, CSSA(lch));
440 dma_write(src_ei, CSEI(lch));
441 dma_write(src_fi, CSFI(lch));
443 EXPORT_SYMBOL(omap_set_dma_src_params);
445 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
447 omap_set_dma_transfer_params(lch, params->data_type,
448 params->elem_count, params->frame_count,
449 params->sync_mode, params->trigger,
450 params->src_or_dst_synch);
451 omap_set_dma_src_params(lch, params->src_port,
452 params->src_amode, params->src_start,
453 params->src_ei, params->src_fi);
455 omap_set_dma_dest_params(lch, params->dst_port,
456 params->dst_amode, params->dst_start,
457 params->dst_ei, params->dst_fi);
458 if (params->read_prio || params->write_prio)
459 omap_dma_set_prio_lch(lch, params->read_prio,
462 EXPORT_SYMBOL(omap_set_dma_params);
464 void omap_set_dma_src_index(int lch, int eidx, int fidx)
466 if (cpu_class_is_omap2())
469 dma_write(eidx, CSEI(lch));
470 dma_write(fidx, CSFI(lch));
472 EXPORT_SYMBOL(omap_set_dma_src_index);
474 void omap_set_dma_src_data_pack(int lch, int enable)
478 l = dma_read(CSDP(lch));
482 dma_write(l, CSDP(lch));
484 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
486 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
488 unsigned int burst = 0;
491 l = dma_read(CSDP(lch));
494 switch (burst_mode) {
495 case OMAP_DMA_DATA_BURST_DIS:
497 case OMAP_DMA_DATA_BURST_4:
498 if (cpu_class_is_omap2())
503 case OMAP_DMA_DATA_BURST_8:
504 if (cpu_class_is_omap2()) {
509 * not supported by current hardware on OMAP1
513 case OMAP_DMA_DATA_BURST_16:
514 if (cpu_class_is_omap2()) {
519 * OMAP1 don't support burst 16
527 dma_write(l, CSDP(lch));
529 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
531 /* Note that dest_port is only for OMAP1 */
532 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
533 unsigned long dest_start,
534 int dst_ei, int dst_fi)
538 if (cpu_class_is_omap1()) {
539 l = dma_read(CSDP(lch));
542 dma_write(l, CSDP(lch));
545 l = dma_read(CCR(lch));
547 l |= dest_amode << 14;
548 dma_write(l, CCR(lch));
550 if (cpu_class_is_omap1()) {
551 dma_write(dest_start >> 16, CDSA_U(lch));
552 dma_write(dest_start, CDSA_L(lch));
555 if (cpu_class_is_omap2())
556 dma_write(dest_start, CDSA(lch));
558 dma_write(dst_ei, CDEI(lch));
559 dma_write(dst_fi, CDFI(lch));
561 EXPORT_SYMBOL(omap_set_dma_dest_params);
563 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
565 if (cpu_class_is_omap2())
568 dma_write(eidx, CDEI(lch));
569 dma_write(fidx, CDFI(lch));
571 EXPORT_SYMBOL(omap_set_dma_dest_index);
573 void omap_set_dma_dest_data_pack(int lch, int enable)
577 l = dma_read(CSDP(lch));
581 dma_write(l, CSDP(lch));
583 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
585 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
587 unsigned int burst = 0;
590 l = dma_read(CSDP(lch));
593 switch (burst_mode) {
594 case OMAP_DMA_DATA_BURST_DIS:
596 case OMAP_DMA_DATA_BURST_4:
597 if (cpu_class_is_omap2())
602 case OMAP_DMA_DATA_BURST_8:
603 if (cpu_class_is_omap2())
608 case OMAP_DMA_DATA_BURST_16:
609 if (cpu_class_is_omap2()) {
614 * OMAP1 don't support burst 16
618 printk(KERN_ERR "Invalid DMA burst mode\n");
623 dma_write(l, CSDP(lch));
625 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
627 static inline void omap_enable_channel_irq(int lch)
632 if (cpu_class_is_omap1())
633 status = dma_read(CSR(lch));
634 else if (cpu_class_is_omap2())
635 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
637 /* Enable some nice interrupts. */
638 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
641 static void omap_disable_channel_irq(int lch)
643 if (cpu_class_is_omap2())
644 dma_write(0, CICR(lch));
647 void omap_enable_dma_irq(int lch, u16 bits)
649 dma_chan[lch].enabled_irqs |= bits;
651 EXPORT_SYMBOL(omap_enable_dma_irq);
653 void omap_disable_dma_irq(int lch, u16 bits)
655 dma_chan[lch].enabled_irqs &= ~bits;
657 EXPORT_SYMBOL(omap_disable_dma_irq);
659 static inline void enable_lnk(int lch)
663 l = dma_read(CLNK_CTRL(lch));
665 if (cpu_class_is_omap1())
668 /* Set the ENABLE_LNK bits */
669 if (dma_chan[lch].next_lch != -1)
670 l = dma_chan[lch].next_lch | (1 << 15);
672 #ifndef CONFIG_ARCH_OMAP1
673 if (cpu_class_is_omap2())
674 if (dma_chan[lch].next_linked_ch != -1)
675 l = dma_chan[lch].next_linked_ch | (1 << 15);
678 dma_write(l, CLNK_CTRL(lch));
681 static inline void disable_lnk(int lch)
685 l = dma_read(CLNK_CTRL(lch));
687 /* Disable interrupts */
688 if (cpu_class_is_omap1()) {
689 dma_write(0, CICR(lch));
690 /* Set the STOP_LNK bit */
694 if (cpu_class_is_omap2()) {
695 omap_disable_channel_irq(lch);
696 /* Clear the ENABLE_LNK bit */
700 dma_write(l, CLNK_CTRL(lch));
701 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
704 static inline void omap2_enable_irq_lch(int lch)
709 if (!cpu_class_is_omap2())
712 spin_lock_irqsave(&dma_chan_lock, flags);
713 val = dma_read(IRQENABLE_L0);
715 dma_write(val, IRQENABLE_L0);
716 spin_unlock_irqrestore(&dma_chan_lock, flags);
719 static inline void omap2_disable_irq_lch(int lch)
724 if (!cpu_class_is_omap2())
727 spin_lock_irqsave(&dma_chan_lock, flags);
728 val = dma_read(IRQENABLE_L0);
730 dma_write(val, IRQENABLE_L0);
731 spin_unlock_irqrestore(&dma_chan_lock, flags);
734 int omap_request_dma(int dev_id, const char *dev_name,
735 void (*callback)(int lch, u16 ch_status, void *data),
736 void *data, int *dma_ch_out)
738 int ch, free_ch = -1;
740 struct omap_dma_lch *chan;
742 spin_lock_irqsave(&dma_chan_lock, flags);
743 for (ch = 0; ch < dma_chan_count; ch++) {
744 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
751 spin_unlock_irqrestore(&dma_chan_lock, flags);
754 chan = dma_chan + free_ch;
755 chan->dev_id = dev_id;
757 if (cpu_class_is_omap1())
758 clear_lch_regs(free_ch);
760 if (cpu_class_is_omap2())
761 omap_clear_dma(free_ch);
763 spin_unlock_irqrestore(&dma_chan_lock, flags);
765 chan->dev_name = dev_name;
766 chan->callback = callback;
770 #ifndef CONFIG_ARCH_OMAP1
771 if (cpu_class_is_omap2()) {
773 chan->next_linked_ch = -1;
777 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
779 if (cpu_class_is_omap1())
780 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
781 else if (cpu_class_is_omap2())
782 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
783 OMAP2_DMA_TRANS_ERR_IRQ;
785 if (cpu_is_omap16xx()) {
786 /* If the sync device is set, configure it dynamically. */
788 set_gdma_dev(free_ch + 1, dev_id);
789 dev_id = free_ch + 1;
792 * Disable the 1510 compatibility mode and set the sync device
795 dma_write(dev_id | (1 << 10), CCR(free_ch));
796 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
797 dma_write(dev_id, CCR(free_ch));
800 if (cpu_class_is_omap2()) {
801 omap2_enable_irq_lch(free_ch);
802 omap_enable_channel_irq(free_ch);
803 /* Clear the CSR register and IRQ status register */
804 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
805 dma_write(1 << free_ch, IRQSTATUS_L0);
808 *dma_ch_out = free_ch;
812 EXPORT_SYMBOL(omap_request_dma);
814 void omap_free_dma(int lch)
818 if (dma_chan[lch].dev_id == -1) {
819 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
824 if (cpu_class_is_omap1()) {
825 /* Disable all DMA interrupts for the channel. */
826 dma_write(0, CICR(lch));
827 /* Make sure the DMA transfer is stopped. */
828 dma_write(0, CCR(lch));
831 if (cpu_class_is_omap2()) {
832 omap2_disable_irq_lch(lch);
834 /* Clear the CSR register and IRQ status register */
835 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
836 dma_write(1 << lch, IRQSTATUS_L0);
838 /* Disable all DMA interrupts for the channel. */
839 dma_write(0, CICR(lch));
841 /* Make sure the DMA transfer is stopped. */
842 dma_write(0, CCR(lch));
846 spin_lock_irqsave(&dma_chan_lock, flags);
847 dma_chan[lch].dev_id = -1;
848 dma_chan[lch].next_lch = -1;
849 dma_chan[lch].callback = NULL;
850 spin_unlock_irqrestore(&dma_chan_lock, flags);
852 EXPORT_SYMBOL(omap_free_dma);
855 * @brief omap_dma_set_global_params : Set global priority settings for dma
858 * @param max_fifo_depth
859 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
860 * DMA_THREAD_RESERVE_ONET
861 * DMA_THREAD_RESERVE_TWOT
862 * DMA_THREAD_RESERVE_THREET
865 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
869 if (!cpu_class_is_omap2()) {
870 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
874 if (max_fifo_depth == 0)
879 reg = 0xff & max_fifo_depth;
880 reg |= (0x3 & tparams) << 12;
881 reg |= (arb_rate & 0xff) << 16;
885 EXPORT_SYMBOL(omap_dma_set_global_params);
888 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
891 * @param read_prio - Read priority
892 * @param write_prio - Write priority
893 * Both of the above can be set with one of the following values :
894 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
897 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
898 unsigned char write_prio)
902 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
903 printk(KERN_ERR "Invalid channel id\n");
906 l = dma_read(CCR(lch));
907 l &= ~((1 << 6) | (1 << 26));
908 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
909 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
911 l |= ((read_prio & 0x1) << 6);
913 dma_write(l, CCR(lch));
917 EXPORT_SYMBOL(omap_dma_set_prio_lch);
920 * Clears any DMA state so the DMA engine is ready to restart with new buffers
921 * through omap_start_dma(). Any buffers in flight are discarded.
923 void omap_clear_dma(int lch)
927 local_irq_save(flags);
929 if (cpu_class_is_omap1()) {
932 l = dma_read(CCR(lch));
933 l &= ~OMAP_DMA_CCR_EN;
934 dma_write(l, CCR(lch));
936 /* Clear pending interrupts */
937 l = dma_read(CSR(lch));
940 if (cpu_class_is_omap2()) {
942 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
943 for (i = 0; i < 0x44; i += 4)
944 __raw_writel(0, lch_base + i);
947 local_irq_restore(flags);
949 EXPORT_SYMBOL(omap_clear_dma);
951 void omap_start_dma(int lch)
956 * The CPC/CDAC register needs to be initialized to zero
957 * before starting dma transfer.
959 if (cpu_is_omap15xx())
960 dma_write(0, CPC(lch));
962 dma_write(0, CDAC(lch));
964 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
965 int next_lch, cur_lch;
966 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
968 dma_chan_link_map[lch] = 1;
969 /* Set the link register of the first channel */
972 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
973 cur_lch = dma_chan[lch].next_lch;
975 next_lch = dma_chan[cur_lch].next_lch;
977 /* The loop case: we've been here already */
978 if (dma_chan_link_map[cur_lch])
980 /* Mark the current channel */
981 dma_chan_link_map[cur_lch] = 1;
984 omap_enable_channel_irq(cur_lch);
987 } while (next_lch != -1);
988 } else if (cpu_is_omap242x() ||
989 (cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) {
991 /* Errata: Need to write lch even if not using chaining */
992 dma_write(lch, CLNK_CTRL(lch));
995 omap_enable_channel_irq(lch);
997 l = dma_read(CCR(lch));
1000 * Errata: Inter Frame DMA buffering issue (All OMAP2420 and
1001 * OMAP2430ES1.0): DMA will wrongly buffer elements if packing and
1002 * bursting is enabled. This might result in data gets stalled in
1003 * FIFO at the end of the block.
1004 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
1005 * guarantee no data will stay in the DMA FIFO in case inter frame
1008 if (cpu_is_omap2420() ||
1009 (cpu_is_omap2430() && (omap_type() == OMAP2430_REV_ES1_0)))
1010 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
1012 l |= OMAP_DMA_CCR_EN;
1013 dma_write(l, CCR(lch));
1015 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1017 EXPORT_SYMBOL(omap_start_dma);
1019 void omap_stop_dma(int lch)
1023 /* Disable all interrupts on the channel */
1024 if (cpu_class_is_omap1())
1025 dma_write(0, CICR(lch));
1027 l = dma_read(CCR(lch));
1028 /* OMAP3 Errata i541: sDMA FIFO draining does not finish */
1029 if (cpu_is_omap34xx() && (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
1033 /* Configure No-Standby */
1034 l = dma_read(OCP_SYSCONFIG);
1036 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
1037 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
1038 dma_write(l , OCP_SYSCONFIG);
1040 l = dma_read(CCR(lch));
1041 l &= ~OMAP_DMA_CCR_EN;
1042 dma_write(l, CCR(lch));
1044 /* Wait for sDMA FIFO drain */
1045 l = dma_read(CCR(lch));
1046 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
1047 OMAP_DMA_CCR_WR_ACTIVE))) {
1050 l = dma_read(CCR(lch));
1053 printk(KERN_ERR "DMA drain did not complete on "
1055 /* Restore OCP_SYSCONFIG */
1056 dma_write(sys_cf, OCP_SYSCONFIG);
1058 l &= ~OMAP_DMA_CCR_EN;
1059 dma_write(l, CCR(lch));
1062 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
1063 int next_lch, cur_lch = lch;
1064 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
1066 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
1068 /* The loop case: we've been here already */
1069 if (dma_chan_link_map[cur_lch])
1071 /* Mark the current channel */
1072 dma_chan_link_map[cur_lch] = 1;
1074 disable_lnk(cur_lch);
1076 next_lch = dma_chan[cur_lch].next_lch;
1078 } while (next_lch != -1);
1081 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1083 EXPORT_SYMBOL(omap_stop_dma);
1086 * Allows changing the DMA callback function or data. This may be needed if
1087 * the driver shares a single DMA channel for multiple dma triggers.
1089 int omap_set_dma_callback(int lch,
1090 void (*callback)(int lch, u16 ch_status, void *data),
1093 unsigned long flags;
1098 spin_lock_irqsave(&dma_chan_lock, flags);
1099 if (dma_chan[lch].dev_id == -1) {
1100 printk(KERN_ERR "DMA callback for not set for free channel\n");
1101 spin_unlock_irqrestore(&dma_chan_lock, flags);
1104 dma_chan[lch].callback = callback;
1105 dma_chan[lch].data = data;
1106 spin_unlock_irqrestore(&dma_chan_lock, flags);
1110 EXPORT_SYMBOL(omap_set_dma_callback);
1113 * Returns current physical source address for the given DMA channel.
1114 * If the channel is running the caller must disable interrupts prior calling
1115 * this function and process the returned value before re-enabling interrupt to
1116 * prevent races with the interrupt handler. Note that in continuous mode there
1117 * is a chance for CSSA_L register overflow inbetween the two reads resulting
1118 * in incorrect return value.
1120 dma_addr_t omap_get_dma_src_pos(int lch)
1122 dma_addr_t offset = 0;
1124 if (cpu_is_omap15xx())
1125 offset = dma_read(CPC(lch));
1127 offset = dma_read(CSAC(lch));
1130 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1131 * read before the DMA controller finished disabling the channel.
1133 if (!cpu_is_omap15xx() && offset == 0)
1134 offset = dma_read(CSAC(lch));
1136 if (cpu_class_is_omap1())
1137 offset |= (dma_read(CSSA_U(lch)) << 16);
1141 EXPORT_SYMBOL(omap_get_dma_src_pos);
1144 * Returns current physical destination address for the given DMA channel.
1145 * If the channel is running the caller must disable interrupts prior calling
1146 * this function and process the returned value before re-enabling interrupt to
1147 * prevent races with the interrupt handler. Note that in continuous mode there
1148 * is a chance for CDSA_L register overflow inbetween the two reads resulting
1149 * in incorrect return value.
1151 dma_addr_t omap_get_dma_dst_pos(int lch)
1153 dma_addr_t offset = 0;
1155 if (cpu_is_omap15xx())
1156 offset = dma_read(CPC(lch));
1158 offset = dma_read(CDAC(lch));
1161 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1162 * read before the DMA controller finished disabling the channel.
1164 if (!cpu_is_omap15xx() && offset == 0)
1165 offset = dma_read(CDAC(lch));
1167 if (cpu_class_is_omap1())
1168 offset |= (dma_read(CDSA_U(lch)) << 16);
1172 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1174 int omap_get_dma_active_status(int lch)
1176 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1178 EXPORT_SYMBOL(omap_get_dma_active_status);
1180 int omap_dma_running(void)
1184 if (cpu_class_is_omap1())
1185 if (omap_lcd_dma_running())
1188 for (lch = 0; lch < dma_chan_count; lch++)
1189 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1196 * lch_queue DMA will start right after lch_head one is finished.
1197 * For this DMA link to start, you still need to start (see omap_start_dma)
1198 * the first one. That will fire up the entire queue.
1200 void omap_dma_link_lch(int lch_head, int lch_queue)
1202 if (omap_dma_in_1510_mode()) {
1203 if (lch_head == lch_queue) {
1204 dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1208 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1213 if ((dma_chan[lch_head].dev_id == -1) ||
1214 (dma_chan[lch_queue].dev_id == -1)) {
1215 printk(KERN_ERR "omap_dma: trying to link "
1216 "non requested channels\n");
1220 dma_chan[lch_head].next_lch = lch_queue;
1222 EXPORT_SYMBOL(omap_dma_link_lch);
1225 * Once the DMA queue is stopped, we can destroy it.
1227 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1229 if (omap_dma_in_1510_mode()) {
1230 if (lch_head == lch_queue) {
1231 dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1235 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1240 if (dma_chan[lch_head].next_lch != lch_queue ||
1241 dma_chan[lch_head].next_lch == -1) {
1242 printk(KERN_ERR "omap_dma: trying to unlink "
1243 "non linked channels\n");
1247 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1248 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1249 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1250 "before unlinking\n");
1254 dma_chan[lch_head].next_lch = -1;
1256 EXPORT_SYMBOL(omap_dma_unlink_lch);
1258 /*----------------------------------------------------------------------------*/
1260 #ifndef CONFIG_ARCH_OMAP1
1261 /* Create chain of DMA channesls */
1262 static void create_dma_lch_chain(int lch_head, int lch_queue)
1266 /* Check if this is the first link in chain */
1267 if (dma_chan[lch_head].next_linked_ch == -1) {
1268 dma_chan[lch_head].next_linked_ch = lch_queue;
1269 dma_chan[lch_head].prev_linked_ch = lch_queue;
1270 dma_chan[lch_queue].next_linked_ch = lch_head;
1271 dma_chan[lch_queue].prev_linked_ch = lch_head;
1274 /* a link exists, link the new channel in circular chain */
1276 dma_chan[lch_queue].next_linked_ch =
1277 dma_chan[lch_head].next_linked_ch;
1278 dma_chan[lch_queue].prev_linked_ch = lch_head;
1279 dma_chan[lch_head].next_linked_ch = lch_queue;
1280 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1284 l = dma_read(CLNK_CTRL(lch_head));
1287 dma_write(l, CLNK_CTRL(lch_head));
1289 l = dma_read(CLNK_CTRL(lch_queue));
1291 l |= (dma_chan[lch_queue].next_linked_ch);
1292 dma_write(l, CLNK_CTRL(lch_queue));
1296 * @brief omap_request_dma_chain : Request a chain of DMA channels
1298 * @param dev_id - Device id using the dma channel
1299 * @param dev_name - Device name
1300 * @param callback - Call back function
1302 * @no_of_chans - Number of channels requested
1303 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1304 * OMAP_DMA_DYNAMIC_CHAIN
1305 * @params - Channel parameters
1307 * @return - Success : 0
1308 * Failure: -EINVAL/-ENOMEM
1310 int omap_request_dma_chain(int dev_id, const char *dev_name,
1311 void (*callback) (int lch, u16 ch_status,
1313 int *chain_id, int no_of_chans, int chain_mode,
1314 struct omap_dma_channel_params params)
1319 /* Is the chain mode valid ? */
1320 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1321 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1322 printk(KERN_ERR "Invalid chain mode requested\n");
1326 if (unlikely((no_of_chans < 1
1327 || no_of_chans > dma_lch_count))) {
1328 printk(KERN_ERR "Invalid Number of channels requested\n");
1333 * Allocate a queue to maintain the status of the channels
1336 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1337 if (channels == NULL) {
1338 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1342 /* request and reserve DMA channels for the chain */
1343 for (i = 0; i < no_of_chans; i++) {
1344 err = omap_request_dma(dev_id, dev_name,
1345 callback, NULL, &channels[i]);
1348 for (j = 0; j < i; j++)
1349 omap_free_dma(channels[j]);
1351 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1354 dma_chan[channels[i]].prev_linked_ch = -1;
1355 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1358 * Allowing client drivers to set common parameters now,
1359 * so that later only relevant (src_start, dest_start
1360 * and element count) can be set
1362 omap_set_dma_params(channels[i], ¶ms);
1365 *chain_id = channels[0];
1366 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1367 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1368 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1369 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1371 for (i = 0; i < no_of_chans; i++)
1372 dma_chan[channels[i]].chain_id = *chain_id;
1374 /* Reset the Queue pointers */
1375 OMAP_DMA_CHAIN_QINIT(*chain_id);
1377 /* Set up the chain */
1378 if (no_of_chans == 1)
1379 create_dma_lch_chain(channels[0], channels[0]);
1381 for (i = 0; i < (no_of_chans - 1); i++)
1382 create_dma_lch_chain(channels[i], channels[i + 1]);
1387 EXPORT_SYMBOL(omap_request_dma_chain);
1390 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1391 * params after setting it. Dont do this while dma is running!!
1393 * @param chain_id - Chained logical channel id.
1396 * @return - Success : 0
1399 int omap_modify_dma_chain_params(int chain_id,
1400 struct omap_dma_channel_params params)
1405 /* Check for input params */
1406 if (unlikely((chain_id < 0
1407 || chain_id >= dma_lch_count))) {
1408 printk(KERN_ERR "Invalid chain id\n");
1412 /* Check if the chain exists */
1413 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1414 printk(KERN_ERR "Chain doesn't exists\n");
1417 channels = dma_linked_lch[chain_id].linked_dmach_q;
1419 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1421 * Allowing client drivers to set common parameters now,
1422 * so that later only relevant (src_start, dest_start
1423 * and element count) can be set
1425 omap_set_dma_params(channels[i], ¶ms);
1430 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1433 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1437 * @return - Success : 0
1440 int omap_free_dma_chain(int chain_id)
1445 /* Check for input params */
1446 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1447 printk(KERN_ERR "Invalid chain id\n");
1451 /* Check if the chain exists */
1452 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1453 printk(KERN_ERR "Chain doesn't exists\n");
1457 channels = dma_linked_lch[chain_id].linked_dmach_q;
1458 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1459 dma_chan[channels[i]].next_linked_ch = -1;
1460 dma_chan[channels[i]].prev_linked_ch = -1;
1461 dma_chan[channels[i]].chain_id = -1;
1462 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1463 omap_free_dma(channels[i]);
1468 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1469 dma_linked_lch[chain_id].chain_mode = -1;
1470 dma_linked_lch[chain_id].chain_state = -1;
1474 EXPORT_SYMBOL(omap_free_dma_chain);
1477 * @brief omap_dma_chain_status - Check if the chain is in
1478 * active / inactive state.
1481 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1484 int omap_dma_chain_status(int chain_id)
1486 /* Check for input params */
1487 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1488 printk(KERN_ERR "Invalid chain id\n");
1492 /* Check if the chain exists */
1493 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1494 printk(KERN_ERR "Chain doesn't exists\n");
1497 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1498 dma_linked_lch[chain_id].q_count);
1500 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1501 return OMAP_DMA_CHAIN_INACTIVE;
1503 return OMAP_DMA_CHAIN_ACTIVE;
1505 EXPORT_SYMBOL(omap_dma_chain_status);
1508 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1509 * set the params and start the transfer.
1512 * @param src_start - buffer start address
1513 * @param dest_start - Dest address
1515 * @param frame_count
1516 * @param callbk_data - channel callback parameter data.
1518 * @return - Success : 0
1519 * Failure: -EINVAL/-EBUSY
1521 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1522 int elem_count, int frame_count, void *callbk_data)
1529 * if buffer size is less than 1 then there is
1530 * no use of starting the chain
1532 if (elem_count < 1) {
1533 printk(KERN_ERR "Invalid buffer size\n");
1537 /* Check for input params */
1538 if (unlikely((chain_id < 0
1539 || chain_id >= dma_lch_count))) {
1540 printk(KERN_ERR "Invalid chain id\n");
1544 /* Check if the chain exists */
1545 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1546 printk(KERN_ERR "Chain doesn't exist\n");
1550 /* Check if all the channels in chain are in use */
1551 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1554 /* Frame count may be negative in case of indexed transfers */
1555 channels = dma_linked_lch[chain_id].linked_dmach_q;
1557 /* Get a free channel */
1558 lch = channels[dma_linked_lch[chain_id].q_tail];
1560 /* Store the callback data */
1561 dma_chan[lch].data = callbk_data;
1563 /* Increment the q_tail */
1564 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1566 /* Set the params to the free channel */
1568 dma_write(src_start, CSSA(lch));
1569 if (dest_start != 0)
1570 dma_write(dest_start, CDSA(lch));
1572 /* Write the buffer size */
1573 dma_write(elem_count, CEN(lch));
1574 dma_write(frame_count, CFN(lch));
1577 * If the chain is dynamically linked,
1578 * then we may have to start the chain if its not active
1580 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1583 * In Dynamic chain, if the chain is not started,
1586 if (dma_linked_lch[chain_id].chain_state ==
1587 DMA_CHAIN_NOTSTARTED) {
1588 /* Enable the link in previous channel */
1589 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1591 enable_lnk(dma_chan[lch].prev_linked_ch);
1592 dma_chan[lch].state = DMA_CH_QUEUED;
1596 * Chain is already started, make sure its active,
1597 * if not then start the chain
1602 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1604 enable_lnk(dma_chan[lch].prev_linked_ch);
1605 dma_chan[lch].state = DMA_CH_QUEUED;
1607 if (0 == ((1 << 7) & dma_read(
1608 CCR(dma_chan[lch].prev_linked_ch)))) {
1609 disable_lnk(dma_chan[lch].
1611 pr_debug("\n prev ch is stopped\n");
1616 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1618 enable_lnk(dma_chan[lch].prev_linked_ch);
1619 dma_chan[lch].state = DMA_CH_QUEUED;
1622 omap_enable_channel_irq(lch);
1624 l = dma_read(CCR(lch));
1626 if ((0 == (l & (1 << 24))))
1630 if (start_dma == 1) {
1631 if (0 == (l & (1 << 7))) {
1633 dma_chan[lch].state = DMA_CH_STARTED;
1634 pr_debug("starting %d\n", lch);
1635 dma_write(l, CCR(lch));
1639 if (0 == (l & (1 << 7)))
1640 dma_write(l, CCR(lch));
1642 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1648 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1651 * @brief omap_start_dma_chain_transfers - Start the chain
1655 * @return - Success : 0
1656 * Failure : -EINVAL/-EBUSY
1658 int omap_start_dma_chain_transfers(int chain_id)
1663 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1664 printk(KERN_ERR "Invalid chain id\n");
1668 channels = dma_linked_lch[chain_id].linked_dmach_q;
1670 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1671 printk(KERN_ERR "Chain is already started\n");
1675 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1676 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1678 enable_lnk(channels[i]);
1679 omap_enable_channel_irq(channels[i]);
1682 omap_enable_channel_irq(channels[0]);
1685 l = dma_read(CCR(channels[0]));
1687 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1688 dma_chan[channels[0]].state = DMA_CH_STARTED;
1690 if ((0 == (l & (1 << 24))))
1694 dma_write(l, CCR(channels[0]));
1696 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1700 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1703 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1707 * @return - Success : 0
1710 int omap_stop_dma_chain_transfers(int chain_id)
1716 /* Check for input params */
1717 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1718 printk(KERN_ERR "Invalid chain id\n");
1722 /* Check if the chain exists */
1723 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1724 printk(KERN_ERR "Chain doesn't exists\n");
1727 channels = dma_linked_lch[chain_id].linked_dmach_q;
1731 * Special programming model needed to disable DMA before end of block
1733 sys_cf = dma_read(OCP_SYSCONFIG);
1735 /* Middle mode reg set no Standby */
1736 l &= ~((1 << 12)|(1 << 13));
1737 dma_write(l, OCP_SYSCONFIG);
1739 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1741 /* Stop the Channel transmission */
1742 l = dma_read(CCR(channels[i]));
1744 dma_write(l, CCR(channels[i]));
1746 /* Disable the link in all the channels */
1747 disable_lnk(channels[i]);
1748 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1751 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1753 /* Reset the Queue pointers */
1754 OMAP_DMA_CHAIN_QINIT(chain_id);
1756 /* Errata - put in the old value */
1757 dma_write(sys_cf, OCP_SYSCONFIG);
1761 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1763 /* Get the index of the ongoing DMA in chain */
1765 * @brief omap_get_dma_chain_index - Get the element and frame index
1766 * of the ongoing DMA in chain
1769 * @param ei - Element index
1770 * @param fi - Frame index
1772 * @return - Success : 0
1775 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1780 /* Check for input params */
1781 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1782 printk(KERN_ERR "Invalid chain id\n");
1786 /* Check if the chain exists */
1787 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1788 printk(KERN_ERR "Chain doesn't exists\n");
1794 channels = dma_linked_lch[chain_id].linked_dmach_q;
1796 /* Get the current channel */
1797 lch = channels[dma_linked_lch[chain_id].q_head];
1799 *ei = dma_read(CCEN(lch));
1800 *fi = dma_read(CCFN(lch));
1804 EXPORT_SYMBOL(omap_get_dma_chain_index);
1807 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1808 * ongoing DMA in chain
1812 * @return - Success : Destination position
1815 int omap_get_dma_chain_dst_pos(int chain_id)
1820 /* Check for input params */
1821 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1822 printk(KERN_ERR "Invalid chain id\n");
1826 /* Check if the chain exists */
1827 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1828 printk(KERN_ERR "Chain doesn't exists\n");
1832 channels = dma_linked_lch[chain_id].linked_dmach_q;
1834 /* Get the current channel */
1835 lch = channels[dma_linked_lch[chain_id].q_head];
1837 return dma_read(CDAC(lch));
1839 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1842 * @brief omap_get_dma_chain_src_pos - Get the source position
1843 * of the ongoing DMA in chain
1846 * @return - Success : Destination position
1849 int omap_get_dma_chain_src_pos(int chain_id)
1854 /* Check for input params */
1855 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1856 printk(KERN_ERR "Invalid chain id\n");
1860 /* Check if the chain exists */
1861 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1862 printk(KERN_ERR "Chain doesn't exists\n");
1866 channels = dma_linked_lch[chain_id].linked_dmach_q;
1868 /* Get the current channel */
1869 lch = channels[dma_linked_lch[chain_id].q_head];
1871 return dma_read(CSAC(lch));
1873 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1874 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1876 /*----------------------------------------------------------------------------*/
1878 #ifdef CONFIG_ARCH_OMAP1
1880 static int omap1_dma_handle_ch(int ch)
1884 if (enable_1510_mode && ch >= 6) {
1885 csr = dma_chan[ch].saved_csr;
1886 dma_chan[ch].saved_csr = 0;
1888 csr = dma_read(CSR(ch));
1889 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1890 dma_chan[ch + 6].saved_csr = csr >> 7;
1893 if ((csr & 0x3f) == 0)
1895 if (unlikely(dma_chan[ch].dev_id == -1)) {
1896 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1897 "%d (CSR %04x)\n", ch, csr);
1900 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1901 printk(KERN_WARNING "DMA timeout with device %d\n",
1902 dma_chan[ch].dev_id);
1903 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1904 printk(KERN_WARNING "DMA synchronization event drop occurred "
1905 "with device %d\n", dma_chan[ch].dev_id);
1906 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1907 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1908 if (likely(dma_chan[ch].callback != NULL))
1909 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1914 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1916 int ch = ((int) dev_id) - 1;
1920 int handled_now = 0;
1922 handled_now += omap1_dma_handle_ch(ch);
1923 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1924 handled_now += omap1_dma_handle_ch(ch + 6);
1927 handled += handled_now;
1930 return handled ? IRQ_HANDLED : IRQ_NONE;
1934 #define omap1_dma_irq_handler NULL
1937 #ifdef CONFIG_ARCH_OMAP2PLUS
1939 static int omap2_dma_handle_ch(int ch)
1941 u32 status = dma_read(CSR(ch));
1944 if (printk_ratelimit())
1945 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1947 dma_write(1 << ch, IRQSTATUS_L0);
1950 if (unlikely(dma_chan[ch].dev_id == -1)) {
1951 if (printk_ratelimit())
1952 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1953 "channel %d\n", status, ch);
1956 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1958 "DMA synchronization event drop occurred with device "
1959 "%d\n", dma_chan[ch].dev_id);
1960 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1961 printk(KERN_INFO "DMA transaction error with device %d\n",
1962 dma_chan[ch].dev_id);
1963 if (cpu_class_is_omap2()) {
1965 * Errata: sDMA Channel is not disabled
1966 * after a transaction error. So we explicitely
1967 * disable the channel
1971 ccr = dma_read(CCR(ch));
1972 ccr &= ~OMAP_DMA_CCR_EN;
1973 dma_write(ccr, CCR(ch));
1974 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1977 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1978 printk(KERN_INFO "DMA secure error with device %d\n",
1979 dma_chan[ch].dev_id);
1980 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1981 printk(KERN_INFO "DMA misaligned error with device %d\n",
1982 dma_chan[ch].dev_id);
1984 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1985 dma_write(1 << ch, IRQSTATUS_L0);
1987 /* If the ch is not chained then chain_id will be -1 */
1988 if (dma_chan[ch].chain_id != -1) {
1989 int chain_id = dma_chan[ch].chain_id;
1990 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1991 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1992 dma_chan[dma_chan[ch].next_linked_ch].state =
1994 if (dma_linked_lch[chain_id].chain_mode ==
1995 OMAP_DMA_DYNAMIC_CHAIN)
1998 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1999 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
2001 status = dma_read(CSR(ch));
2004 dma_write(status, CSR(ch));
2006 if (likely(dma_chan[ch].callback != NULL))
2007 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
2012 /* STATUS register count is from 1-32 while our is 0-31 */
2013 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
2015 u32 val, enable_reg;
2018 val = dma_read(IRQSTATUS_L0);
2020 if (printk_ratelimit())
2021 printk(KERN_WARNING "Spurious DMA IRQ\n");
2024 enable_reg = dma_read(IRQENABLE_L0);
2025 val &= enable_reg; /* Dispatch only relevant interrupts */
2026 for (i = 0; i < dma_lch_count && val != 0; i++) {
2028 omap2_dma_handle_ch(i);
2035 static struct irqaction omap24xx_dma_irq = {
2037 .handler = omap2_dma_irq_handler,
2038 .flags = IRQF_DISABLED
2042 static struct irqaction omap24xx_dma_irq;
2045 /*----------------------------------------------------------------------------*/
2047 void omap_dma_global_context_save(void)
2049 omap_dma_global_context.dma_irqenable_l0 =
2050 dma_read(IRQENABLE_L0);
2051 omap_dma_global_context.dma_ocp_sysconfig =
2052 dma_read(OCP_SYSCONFIG);
2053 omap_dma_global_context.dma_gcr = dma_read(GCR);
2056 void omap_dma_global_context_restore(void)
2060 dma_write(omap_dma_global_context.dma_gcr, GCR);
2061 dma_write(omap_dma_global_context.dma_ocp_sysconfig,
2063 dma_write(omap_dma_global_context.dma_irqenable_l0,
2067 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
2068 * after secure sram context save and restore. Hence we need to
2069 * manually clear those IRQs to avoid spurious interrupts. This
2070 * affects only secure devices.
2072 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
2073 dma_write(0x3 , IRQSTATUS_L0);
2075 for (ch = 0; ch < dma_chan_count; ch++)
2076 if (dma_chan[ch].dev_id != -1)
2080 /*----------------------------------------------------------------------------*/
2082 static int __init omap_init_dma(void)
2087 if (cpu_class_is_omap1()) {
2088 base = OMAP1_DMA_BASE;
2089 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2090 } else if (cpu_is_omap24xx()) {
2091 base = OMAP24XX_DMA4_BASE;
2092 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2093 } else if (cpu_is_omap34xx()) {
2094 base = OMAP34XX_DMA4_BASE;
2095 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2096 } else if (cpu_is_omap44xx()) {
2097 base = OMAP44XX_DMA4_BASE;
2098 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2100 pr_err("DMA init failed for unsupported omap\n");
2104 omap_dma_base = ioremap(base, SZ_4K);
2105 BUG_ON(!omap_dma_base);
2107 if (cpu_class_is_omap2() && omap_dma_reserve_channels
2108 && (omap_dma_reserve_channels <= dma_lch_count))
2109 dma_lch_count = omap_dma_reserve_channels;
2111 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2118 if (cpu_class_is_omap2()) {
2119 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2120 dma_lch_count, GFP_KERNEL);
2121 if (!dma_linked_lch) {
2127 if (cpu_is_omap15xx()) {
2128 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2130 enable_1510_mode = 1;
2131 } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2132 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2134 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2135 (dma_read(CAPS_0_U) << 16) |
2137 (dma_read(CAPS_1_U) << 16) |
2139 dma_read(CAPS_2), dma_read(CAPS_3),
2141 if (!enable_1510_mode) {
2144 /* Disable OMAP 3.0/3.1 compatibility mode. */
2148 dma_chan_count = 16;
2151 } else if (cpu_class_is_omap2()) {
2152 u8 revision = dma_read(REVISION) & 0xff;
2153 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2154 revision >> 4, revision & 0xf);
2155 dma_chan_count = dma_lch_count;
2161 spin_lock_init(&dma_chan_lock);
2163 for (ch = 0; ch < dma_chan_count; ch++) {
2165 if (cpu_class_is_omap2())
2166 omap2_disable_irq_lch(ch);
2168 dma_chan[ch].dev_id = -1;
2169 dma_chan[ch].next_lch = -1;
2171 if (ch >= 6 && enable_1510_mode)
2174 if (cpu_class_is_omap1()) {
2176 * request_irq() doesn't like dev_id (ie. ch) being
2177 * zero, so we have to kludge around this.
2179 r = request_irq(omap1_dma_irq[ch],
2180 omap1_dma_irq_handler, 0, "DMA",
2185 printk(KERN_ERR "unable to request IRQ %d "
2186 "for DMA (error %d)\n",
2187 omap1_dma_irq[ch], r);
2188 for (i = 0; i < ch; i++)
2189 free_irq(omap1_dma_irq[i],
2196 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2197 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2198 DMA_DEFAULT_FIFO_DEPTH, 0);
2200 if (cpu_class_is_omap2()) {
2202 if (cpu_is_omap44xx())
2203 irq = OMAP44XX_IRQ_SDMA_0;
2205 irq = INT_24XX_SDMA_IRQ0;
2206 setup_irq(irq, &omap24xx_dma_irq);
2209 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
2210 /* Enable smartidle idlemodes and autoidle */
2211 u32 v = dma_read(OCP_SYSCONFIG);
2212 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2213 DMA_SYSCONFIG_SIDLEMODE_MASK |
2214 DMA_SYSCONFIG_AUTOIDLE);
2215 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2216 DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2217 DMA_SYSCONFIG_AUTOIDLE);
2218 dma_write(v , OCP_SYSCONFIG);
2219 /* reserve dma channels 0 and 1 in high security devices */
2220 if (cpu_is_omap34xx() &&
2221 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2222 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2224 dma_chan[0].dev_id = 0;
2225 dma_chan[1].dev_id = 1;
2235 iounmap(omap_dma_base);
2240 arch_initcall(omap_init_dma);
2243 * Reserve the omap SDMA channels using cmdline bootarg
2244 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2246 static int __init omap_dma_cmdline_reserve_ch(char *str)
2248 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2249 omap_dma_reserve_channels = 0;
2253 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);