2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Support functions for the OMAP internal DMA channels.
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/sched.h>
27 #include <linux/spinlock.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
32 #include <linux/slab.h>
34 #include <asm/system.h>
35 #include <mach/hardware.h>
42 #ifndef CONFIG_ARCH_OMAP1
43 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
44 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
47 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
50 #define OMAP_DMA_ACTIVE 0x01
51 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
53 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
55 static int enable_1510_mode;
57 static struct omap_dma_global_context_registers {
59 u32 dma_ocp_sysconfig;
61 } omap_dma_global_context;
69 void (*callback)(int lch, u16 ch_status, void *data);
72 #ifndef CONFIG_ARCH_OMAP1
73 /* required for Dynamic chaining */
84 struct dma_link_info {
86 int no_of_lchs_linked;
97 static struct dma_link_info *dma_linked_lch;
99 #ifndef CONFIG_ARCH_OMAP1
101 /* Chain handling macros */
102 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
104 dma_linked_lch[chain_id].q_head = \
105 dma_linked_lch[chain_id].q_tail = \
106 dma_linked_lch[chain_id].q_count = 0; \
108 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
109 (dma_linked_lch[chain_id].no_of_lchs_linked == \
110 dma_linked_lch[chain_id].q_count)
111 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
113 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
114 dma_linked_lch[chain_id].q_count) \
116 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
117 (0 == dma_linked_lch[chain_id].q_count)
118 #define __OMAP_DMA_CHAIN_INCQ(end) \
119 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
120 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
122 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
123 dma_linked_lch[chain_id].q_count--; \
126 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
128 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
129 dma_linked_lch[chain_id].q_count++; \
133 static int dma_lch_count;
134 static int dma_chan_count;
135 static int omap_dma_reserve_channels;
137 static spinlock_t dma_chan_lock;
138 static struct omap_dma_lch *dma_chan;
139 static void __iomem *omap_dma_base;
141 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
142 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
143 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
144 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
145 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
146 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
149 static inline void disable_lnk(int lch);
150 static void omap_disable_channel_irq(int lch);
151 static inline void omap_enable_channel_irq(int lch);
153 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
156 #define dma_read(reg) \
159 if (cpu_class_is_omap1()) \
160 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
162 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
166 #define dma_write(val, reg) \
168 if (cpu_class_is_omap1()) \
169 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
171 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
174 #ifdef CONFIG_ARCH_OMAP15XX
175 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
176 int omap_dma_in_1510_mode(void)
178 return enable_1510_mode;
181 #define omap_dma_in_1510_mode() 0
184 #ifdef CONFIG_ARCH_OMAP1
185 static inline int get_gdma_dev(int req)
187 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
188 int shift = ((req - 1) % 5) * 6;
190 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
193 static inline void set_gdma_dev(int req, int dev)
195 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
196 int shift = ((req - 1) % 5) * 6;
200 l &= ~(0x3f << shift);
201 l |= (dev - 1) << shift;
205 #define set_gdma_dev(req, dev) do {} while (0)
209 static void clear_lch_regs(int lch)
212 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
214 for (i = 0; i < 0x2c; i += 2)
215 __raw_writew(0, lch_base + i);
218 void omap_set_dma_priority(int lch, int dst_port, int priority)
223 if (cpu_class_is_omap1()) {
225 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
226 reg = OMAP_TC_OCPT1_PRIOR;
228 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
229 reg = OMAP_TC_OCPT2_PRIOR;
231 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
232 reg = OMAP_TC_EMIFF_PRIOR;
234 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
235 reg = OMAP_TC_EMIFS_PRIOR;
243 l |= (priority & 0xf) << 8;
247 if (cpu_class_is_omap2()) {
250 ccr = dma_read(CCR(lch));
255 dma_write(ccr, CCR(lch));
258 EXPORT_SYMBOL(omap_set_dma_priority);
260 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
261 int frame_count, int sync_mode,
262 int dma_trigger, int src_or_dst_synch)
266 l = dma_read(CSDP(lch));
269 dma_write(l, CSDP(lch));
271 if (cpu_class_is_omap1()) {
274 ccr = dma_read(CCR(lch));
276 if (sync_mode == OMAP_DMA_SYNC_FRAME)
278 dma_write(ccr, CCR(lch));
280 ccr = dma_read(CCR2(lch));
282 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
284 dma_write(ccr, CCR2(lch));
287 if (cpu_class_is_omap2() && dma_trigger) {
290 val = dma_read(CCR(lch));
292 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
293 val &= ~((1 << 23) | (3 << 19) | 0x1f);
294 val |= (dma_trigger & ~0x1f) << 14;
295 val |= dma_trigger & 0x1f;
297 if (sync_mode & OMAP_DMA_SYNC_FRAME)
302 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
307 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
308 val &= ~(1 << 24); /* dest synch */
309 val |= (1 << 23); /* Prefetch */
310 } else if (src_or_dst_synch) {
311 val |= 1 << 24; /* source synch */
313 val &= ~(1 << 24); /* dest synch */
315 dma_write(val, CCR(lch));
318 dma_write(elem_count, CEN(lch));
319 dma_write(frame_count, CFN(lch));
321 EXPORT_SYMBOL(omap_set_dma_transfer_params);
323 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
325 BUG_ON(omap_dma_in_1510_mode());
327 if (cpu_class_is_omap1()) {
330 w = dma_read(CCR2(lch));
334 case OMAP_DMA_CONSTANT_FILL:
337 case OMAP_DMA_TRANSPARENT_COPY:
340 case OMAP_DMA_COLOR_DIS:
345 dma_write(w, CCR2(lch));
347 w = dma_read(LCH_CTRL(lch));
349 /* Default is channel type 2D */
351 dma_write((u16)color, COLOR_L(lch));
352 dma_write((u16)(color >> 16), COLOR_U(lch));
353 w |= 1; /* Channel type G */
355 dma_write(w, LCH_CTRL(lch));
358 if (cpu_class_is_omap2()) {
361 val = dma_read(CCR(lch));
362 val &= ~((1 << 17) | (1 << 16));
365 case OMAP_DMA_CONSTANT_FILL:
368 case OMAP_DMA_TRANSPARENT_COPY:
371 case OMAP_DMA_COLOR_DIS:
376 dma_write(val, CCR(lch));
379 dma_write(color, COLOR(lch));
382 EXPORT_SYMBOL(omap_set_dma_color_mode);
384 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
386 if (cpu_class_is_omap2()) {
389 csdp = dma_read(CSDP(lch));
390 csdp &= ~(0x3 << 16);
391 csdp |= (mode << 16);
392 dma_write(csdp, CSDP(lch));
395 EXPORT_SYMBOL(omap_set_dma_write_mode);
397 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
399 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
402 l = dma_read(LCH_CTRL(lch));
405 dma_write(l, LCH_CTRL(lch));
408 EXPORT_SYMBOL(omap_set_dma_channel_mode);
410 /* Note that src_port is only for omap1 */
411 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
412 unsigned long src_start,
413 int src_ei, int src_fi)
417 if (cpu_class_is_omap1()) {
420 w = dma_read(CSDP(lch));
423 dma_write(w, CSDP(lch));
426 l = dma_read(CCR(lch));
428 l |= src_amode << 12;
429 dma_write(l, CCR(lch));
431 if (cpu_class_is_omap1()) {
432 dma_write(src_start >> 16, CSSA_U(lch));
433 dma_write((u16)src_start, CSSA_L(lch));
436 if (cpu_class_is_omap2())
437 dma_write(src_start, CSSA(lch));
439 dma_write(src_ei, CSEI(lch));
440 dma_write(src_fi, CSFI(lch));
442 EXPORT_SYMBOL(omap_set_dma_src_params);
444 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
446 omap_set_dma_transfer_params(lch, params->data_type,
447 params->elem_count, params->frame_count,
448 params->sync_mode, params->trigger,
449 params->src_or_dst_synch);
450 omap_set_dma_src_params(lch, params->src_port,
451 params->src_amode, params->src_start,
452 params->src_ei, params->src_fi);
454 omap_set_dma_dest_params(lch, params->dst_port,
455 params->dst_amode, params->dst_start,
456 params->dst_ei, params->dst_fi);
457 if (params->read_prio || params->write_prio)
458 omap_dma_set_prio_lch(lch, params->read_prio,
461 EXPORT_SYMBOL(omap_set_dma_params);
463 void omap_set_dma_src_index(int lch, int eidx, int fidx)
465 if (cpu_class_is_omap2())
468 dma_write(eidx, CSEI(lch));
469 dma_write(fidx, CSFI(lch));
471 EXPORT_SYMBOL(omap_set_dma_src_index);
473 void omap_set_dma_src_data_pack(int lch, int enable)
477 l = dma_read(CSDP(lch));
481 dma_write(l, CSDP(lch));
483 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
485 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
487 unsigned int burst = 0;
490 l = dma_read(CSDP(lch));
493 switch (burst_mode) {
494 case OMAP_DMA_DATA_BURST_DIS:
496 case OMAP_DMA_DATA_BURST_4:
497 if (cpu_class_is_omap2())
502 case OMAP_DMA_DATA_BURST_8:
503 if (cpu_class_is_omap2()) {
508 * not supported by current hardware on OMAP1
512 case OMAP_DMA_DATA_BURST_16:
513 if (cpu_class_is_omap2()) {
518 * OMAP1 don't support burst 16
526 dma_write(l, CSDP(lch));
528 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
530 /* Note that dest_port is only for OMAP1 */
531 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
532 unsigned long dest_start,
533 int dst_ei, int dst_fi)
537 if (cpu_class_is_omap1()) {
538 l = dma_read(CSDP(lch));
541 dma_write(l, CSDP(lch));
544 l = dma_read(CCR(lch));
546 l |= dest_amode << 14;
547 dma_write(l, CCR(lch));
549 if (cpu_class_is_omap1()) {
550 dma_write(dest_start >> 16, CDSA_U(lch));
551 dma_write(dest_start, CDSA_L(lch));
554 if (cpu_class_is_omap2())
555 dma_write(dest_start, CDSA(lch));
557 dma_write(dst_ei, CDEI(lch));
558 dma_write(dst_fi, CDFI(lch));
560 EXPORT_SYMBOL(omap_set_dma_dest_params);
562 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
564 if (cpu_class_is_omap2())
567 dma_write(eidx, CDEI(lch));
568 dma_write(fidx, CDFI(lch));
570 EXPORT_SYMBOL(omap_set_dma_dest_index);
572 void omap_set_dma_dest_data_pack(int lch, int enable)
576 l = dma_read(CSDP(lch));
580 dma_write(l, CSDP(lch));
582 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
584 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
586 unsigned int burst = 0;
589 l = dma_read(CSDP(lch));
592 switch (burst_mode) {
593 case OMAP_DMA_DATA_BURST_DIS:
595 case OMAP_DMA_DATA_BURST_4:
596 if (cpu_class_is_omap2())
601 case OMAP_DMA_DATA_BURST_8:
602 if (cpu_class_is_omap2())
607 case OMAP_DMA_DATA_BURST_16:
608 if (cpu_class_is_omap2()) {
613 * OMAP1 don't support burst 16
617 printk(KERN_ERR "Invalid DMA burst mode\n");
622 dma_write(l, CSDP(lch));
624 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
626 static inline void omap_enable_channel_irq(int lch)
631 if (cpu_class_is_omap1())
632 status = dma_read(CSR(lch));
633 else if (cpu_class_is_omap2())
634 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
636 /* Enable some nice interrupts. */
637 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
640 static void omap_disable_channel_irq(int lch)
642 if (cpu_class_is_omap2())
643 dma_write(0, CICR(lch));
646 void omap_enable_dma_irq(int lch, u16 bits)
648 dma_chan[lch].enabled_irqs |= bits;
650 EXPORT_SYMBOL(omap_enable_dma_irq);
652 void omap_disable_dma_irq(int lch, u16 bits)
654 dma_chan[lch].enabled_irqs &= ~bits;
656 EXPORT_SYMBOL(omap_disable_dma_irq);
658 static inline void enable_lnk(int lch)
662 l = dma_read(CLNK_CTRL(lch));
664 if (cpu_class_is_omap1())
667 /* Set the ENABLE_LNK bits */
668 if (dma_chan[lch].next_lch != -1)
669 l = dma_chan[lch].next_lch | (1 << 15);
671 #ifndef CONFIG_ARCH_OMAP1
672 if (cpu_class_is_omap2())
673 if (dma_chan[lch].next_linked_ch != -1)
674 l = dma_chan[lch].next_linked_ch | (1 << 15);
677 dma_write(l, CLNK_CTRL(lch));
680 static inline void disable_lnk(int lch)
684 l = dma_read(CLNK_CTRL(lch));
686 /* Disable interrupts */
687 if (cpu_class_is_omap1()) {
688 dma_write(0, CICR(lch));
689 /* Set the STOP_LNK bit */
693 if (cpu_class_is_omap2()) {
694 omap_disable_channel_irq(lch);
695 /* Clear the ENABLE_LNK bit */
699 dma_write(l, CLNK_CTRL(lch));
700 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
703 static inline void omap2_enable_irq_lch(int lch)
708 if (!cpu_class_is_omap2())
711 spin_lock_irqsave(&dma_chan_lock, flags);
712 val = dma_read(IRQENABLE_L0);
714 dma_write(val, IRQENABLE_L0);
715 spin_unlock_irqrestore(&dma_chan_lock, flags);
718 static inline void omap2_disable_irq_lch(int lch)
723 if (!cpu_class_is_omap2())
726 spin_lock_irqsave(&dma_chan_lock, flags);
727 val = dma_read(IRQENABLE_L0);
729 dma_write(val, IRQENABLE_L0);
730 spin_unlock_irqrestore(&dma_chan_lock, flags);
733 int omap_request_dma(int dev_id, const char *dev_name,
734 void (*callback)(int lch, u16 ch_status, void *data),
735 void *data, int *dma_ch_out)
737 int ch, free_ch = -1;
739 struct omap_dma_lch *chan;
741 spin_lock_irqsave(&dma_chan_lock, flags);
742 for (ch = 0; ch < dma_chan_count; ch++) {
743 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
750 spin_unlock_irqrestore(&dma_chan_lock, flags);
753 chan = dma_chan + free_ch;
754 chan->dev_id = dev_id;
756 if (cpu_class_is_omap1())
757 clear_lch_regs(free_ch);
759 if (cpu_class_is_omap2())
760 omap_clear_dma(free_ch);
762 spin_unlock_irqrestore(&dma_chan_lock, flags);
764 chan->dev_name = dev_name;
765 chan->callback = callback;
769 #ifndef CONFIG_ARCH_OMAP1
770 if (cpu_class_is_omap2()) {
772 chan->next_linked_ch = -1;
776 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
778 if (cpu_class_is_omap1())
779 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
780 else if (cpu_class_is_omap2())
781 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
782 OMAP2_DMA_TRANS_ERR_IRQ;
784 if (cpu_is_omap16xx()) {
785 /* If the sync device is set, configure it dynamically. */
787 set_gdma_dev(free_ch + 1, dev_id);
788 dev_id = free_ch + 1;
791 * Disable the 1510 compatibility mode and set the sync device
794 dma_write(dev_id | (1 << 10), CCR(free_ch));
795 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
796 dma_write(dev_id, CCR(free_ch));
799 if (cpu_class_is_omap2()) {
800 omap2_enable_irq_lch(free_ch);
801 omap_enable_channel_irq(free_ch);
802 /* Clear the CSR register and IRQ status register */
803 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
804 dma_write(1 << free_ch, IRQSTATUS_L0);
807 *dma_ch_out = free_ch;
811 EXPORT_SYMBOL(omap_request_dma);
813 void omap_free_dma(int lch)
817 if (dma_chan[lch].dev_id == -1) {
818 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
823 if (cpu_class_is_omap1()) {
824 /* Disable all DMA interrupts for the channel. */
825 dma_write(0, CICR(lch));
826 /* Make sure the DMA transfer is stopped. */
827 dma_write(0, CCR(lch));
830 if (cpu_class_is_omap2()) {
831 omap2_disable_irq_lch(lch);
833 /* Clear the CSR register and IRQ status register */
834 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
835 dma_write(1 << lch, IRQSTATUS_L0);
837 /* Disable all DMA interrupts for the channel. */
838 dma_write(0, CICR(lch));
840 /* Make sure the DMA transfer is stopped. */
841 dma_write(0, CCR(lch));
845 spin_lock_irqsave(&dma_chan_lock, flags);
846 dma_chan[lch].dev_id = -1;
847 dma_chan[lch].next_lch = -1;
848 dma_chan[lch].callback = NULL;
849 spin_unlock_irqrestore(&dma_chan_lock, flags);
851 EXPORT_SYMBOL(omap_free_dma);
854 * @brief omap_dma_set_global_params : Set global priority settings for dma
857 * @param max_fifo_depth
858 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
859 * DMA_THREAD_RESERVE_ONET
860 * DMA_THREAD_RESERVE_TWOT
861 * DMA_THREAD_RESERVE_THREET
864 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
868 if (!cpu_class_is_omap2()) {
869 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
873 if (max_fifo_depth == 0)
878 reg = 0xff & max_fifo_depth;
879 reg |= (0x3 & tparams) << 12;
880 reg |= (arb_rate & 0xff) << 16;
884 EXPORT_SYMBOL(omap_dma_set_global_params);
887 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
890 * @param read_prio - Read priority
891 * @param write_prio - Write priority
892 * Both of the above can be set with one of the following values :
893 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
896 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
897 unsigned char write_prio)
901 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
902 printk(KERN_ERR "Invalid channel id\n");
905 l = dma_read(CCR(lch));
906 l &= ~((1 << 6) | (1 << 26));
907 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
908 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
910 l |= ((read_prio & 0x1) << 6);
912 dma_write(l, CCR(lch));
916 EXPORT_SYMBOL(omap_dma_set_prio_lch);
919 * Clears any DMA state so the DMA engine is ready to restart with new buffers
920 * through omap_start_dma(). Any buffers in flight are discarded.
922 void omap_clear_dma(int lch)
926 local_irq_save(flags);
928 if (cpu_class_is_omap1()) {
931 l = dma_read(CCR(lch));
932 l &= ~OMAP_DMA_CCR_EN;
933 dma_write(l, CCR(lch));
935 /* Clear pending interrupts */
936 l = dma_read(CSR(lch));
939 if (cpu_class_is_omap2()) {
941 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
942 for (i = 0; i < 0x44; i += 4)
943 __raw_writel(0, lch_base + i);
946 local_irq_restore(flags);
948 EXPORT_SYMBOL(omap_clear_dma);
950 void omap_start_dma(int lch)
955 * The CPC/CDAC register needs to be initialized to zero
956 * before starting dma transfer.
958 if (cpu_is_omap15xx())
959 dma_write(0, CPC(lch));
961 dma_write(0, CDAC(lch));
963 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
964 int next_lch, cur_lch;
965 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
967 dma_chan_link_map[lch] = 1;
968 /* Set the link register of the first channel */
971 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
972 cur_lch = dma_chan[lch].next_lch;
974 next_lch = dma_chan[cur_lch].next_lch;
976 /* The loop case: we've been here already */
977 if (dma_chan_link_map[cur_lch])
979 /* Mark the current channel */
980 dma_chan_link_map[cur_lch] = 1;
983 omap_enable_channel_irq(cur_lch);
986 } while (next_lch != -1);
987 } else if (cpu_is_omap242x() ||
988 (cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) {
990 /* Errata: Need to write lch even if not using chaining */
991 dma_write(lch, CLNK_CTRL(lch));
994 omap_enable_channel_irq(lch);
996 l = dma_read(CCR(lch));
999 * Errata: On ES2.0 BUFFERING disable must be set.
1000 * This will always fail on ES1.0
1002 if (cpu_is_omap24xx())
1003 l |= OMAP_DMA_CCR_EN;
1005 l |= OMAP_DMA_CCR_EN;
1006 dma_write(l, CCR(lch));
1008 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1010 EXPORT_SYMBOL(omap_start_dma);
1012 void omap_stop_dma(int lch)
1016 /* Disable all interrupts on the channel */
1017 if (cpu_class_is_omap1())
1018 dma_write(0, CICR(lch));
1020 l = dma_read(CCR(lch));
1021 l &= ~OMAP_DMA_CCR_EN;
1022 dma_write(l, CCR(lch));
1024 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
1025 int next_lch, cur_lch = lch;
1026 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
1028 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
1030 /* The loop case: we've been here already */
1031 if (dma_chan_link_map[cur_lch])
1033 /* Mark the current channel */
1034 dma_chan_link_map[cur_lch] = 1;
1036 disable_lnk(cur_lch);
1038 next_lch = dma_chan[cur_lch].next_lch;
1040 } while (next_lch != -1);
1043 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1045 EXPORT_SYMBOL(omap_stop_dma);
1048 * Allows changing the DMA callback function or data. This may be needed if
1049 * the driver shares a single DMA channel for multiple dma triggers.
1051 int omap_set_dma_callback(int lch,
1052 void (*callback)(int lch, u16 ch_status, void *data),
1055 unsigned long flags;
1060 spin_lock_irqsave(&dma_chan_lock, flags);
1061 if (dma_chan[lch].dev_id == -1) {
1062 printk(KERN_ERR "DMA callback for not set for free channel\n");
1063 spin_unlock_irqrestore(&dma_chan_lock, flags);
1066 dma_chan[lch].callback = callback;
1067 dma_chan[lch].data = data;
1068 spin_unlock_irqrestore(&dma_chan_lock, flags);
1072 EXPORT_SYMBOL(omap_set_dma_callback);
1075 * Returns current physical source address for the given DMA channel.
1076 * If the channel is running the caller must disable interrupts prior calling
1077 * this function and process the returned value before re-enabling interrupt to
1078 * prevent races with the interrupt handler. Note that in continuous mode there
1079 * is a chance for CSSA_L register overflow inbetween the two reads resulting
1080 * in incorrect return value.
1082 dma_addr_t omap_get_dma_src_pos(int lch)
1084 dma_addr_t offset = 0;
1086 if (cpu_is_omap15xx())
1087 offset = dma_read(CPC(lch));
1089 offset = dma_read(CSAC(lch));
1092 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1093 * read before the DMA controller finished disabling the channel.
1095 if (!cpu_is_omap15xx() && offset == 0)
1096 offset = dma_read(CSAC(lch));
1098 if (cpu_class_is_omap1())
1099 offset |= (dma_read(CSSA_U(lch)) << 16);
1103 EXPORT_SYMBOL(omap_get_dma_src_pos);
1106 * Returns current physical destination address for the given DMA channel.
1107 * If the channel is running the caller must disable interrupts prior calling
1108 * this function and process the returned value before re-enabling interrupt to
1109 * prevent races with the interrupt handler. Note that in continuous mode there
1110 * is a chance for CDSA_L register overflow inbetween the two reads resulting
1111 * in incorrect return value.
1113 dma_addr_t omap_get_dma_dst_pos(int lch)
1115 dma_addr_t offset = 0;
1117 if (cpu_is_omap15xx())
1118 offset = dma_read(CPC(lch));
1120 offset = dma_read(CDAC(lch));
1123 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1124 * read before the DMA controller finished disabling the channel.
1126 if (!cpu_is_omap15xx() && offset == 0)
1127 offset = dma_read(CDAC(lch));
1129 if (cpu_class_is_omap1())
1130 offset |= (dma_read(CDSA_U(lch)) << 16);
1134 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1136 int omap_get_dma_active_status(int lch)
1138 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1140 EXPORT_SYMBOL(omap_get_dma_active_status);
1142 int omap_dma_running(void)
1146 if (cpu_class_is_omap1())
1147 if (omap_lcd_dma_running())
1150 for (lch = 0; lch < dma_chan_count; lch++)
1151 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1158 * lch_queue DMA will start right after lch_head one is finished.
1159 * For this DMA link to start, you still need to start (see omap_start_dma)
1160 * the first one. That will fire up the entire queue.
1162 void omap_dma_link_lch(int lch_head, int lch_queue)
1164 if (omap_dma_in_1510_mode()) {
1165 if (lch_head == lch_queue) {
1166 dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1170 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1175 if ((dma_chan[lch_head].dev_id == -1) ||
1176 (dma_chan[lch_queue].dev_id == -1)) {
1177 printk(KERN_ERR "omap_dma: trying to link "
1178 "non requested channels\n");
1182 dma_chan[lch_head].next_lch = lch_queue;
1184 EXPORT_SYMBOL(omap_dma_link_lch);
1187 * Once the DMA queue is stopped, we can destroy it.
1189 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1191 if (omap_dma_in_1510_mode()) {
1192 if (lch_head == lch_queue) {
1193 dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1197 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1202 if (dma_chan[lch_head].next_lch != lch_queue ||
1203 dma_chan[lch_head].next_lch == -1) {
1204 printk(KERN_ERR "omap_dma: trying to unlink "
1205 "non linked channels\n");
1209 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1210 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1211 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1212 "before unlinking\n");
1216 dma_chan[lch_head].next_lch = -1;
1218 EXPORT_SYMBOL(omap_dma_unlink_lch);
1220 /*----------------------------------------------------------------------------*/
1222 #ifndef CONFIG_ARCH_OMAP1
1223 /* Create chain of DMA channesls */
1224 static void create_dma_lch_chain(int lch_head, int lch_queue)
1228 /* Check if this is the first link in chain */
1229 if (dma_chan[lch_head].next_linked_ch == -1) {
1230 dma_chan[lch_head].next_linked_ch = lch_queue;
1231 dma_chan[lch_head].prev_linked_ch = lch_queue;
1232 dma_chan[lch_queue].next_linked_ch = lch_head;
1233 dma_chan[lch_queue].prev_linked_ch = lch_head;
1236 /* a link exists, link the new channel in circular chain */
1238 dma_chan[lch_queue].next_linked_ch =
1239 dma_chan[lch_head].next_linked_ch;
1240 dma_chan[lch_queue].prev_linked_ch = lch_head;
1241 dma_chan[lch_head].next_linked_ch = lch_queue;
1242 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1246 l = dma_read(CLNK_CTRL(lch_head));
1249 dma_write(l, CLNK_CTRL(lch_head));
1251 l = dma_read(CLNK_CTRL(lch_queue));
1253 l |= (dma_chan[lch_queue].next_linked_ch);
1254 dma_write(l, CLNK_CTRL(lch_queue));
1258 * @brief omap_request_dma_chain : Request a chain of DMA channels
1260 * @param dev_id - Device id using the dma channel
1261 * @param dev_name - Device name
1262 * @param callback - Call back function
1264 * @no_of_chans - Number of channels requested
1265 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1266 * OMAP_DMA_DYNAMIC_CHAIN
1267 * @params - Channel parameters
1269 * @return - Success : 0
1270 * Failure: -EINVAL/-ENOMEM
1272 int omap_request_dma_chain(int dev_id, const char *dev_name,
1273 void (*callback) (int lch, u16 ch_status,
1275 int *chain_id, int no_of_chans, int chain_mode,
1276 struct omap_dma_channel_params params)
1281 /* Is the chain mode valid ? */
1282 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1283 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1284 printk(KERN_ERR "Invalid chain mode requested\n");
1288 if (unlikely((no_of_chans < 1
1289 || no_of_chans > dma_lch_count))) {
1290 printk(KERN_ERR "Invalid Number of channels requested\n");
1295 * Allocate a queue to maintain the status of the channels
1298 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1299 if (channels == NULL) {
1300 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1304 /* request and reserve DMA channels for the chain */
1305 for (i = 0; i < no_of_chans; i++) {
1306 err = omap_request_dma(dev_id, dev_name,
1307 callback, NULL, &channels[i]);
1310 for (j = 0; j < i; j++)
1311 omap_free_dma(channels[j]);
1313 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1316 dma_chan[channels[i]].prev_linked_ch = -1;
1317 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1320 * Allowing client drivers to set common parameters now,
1321 * so that later only relevant (src_start, dest_start
1322 * and element count) can be set
1324 omap_set_dma_params(channels[i], ¶ms);
1327 *chain_id = channels[0];
1328 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1329 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1330 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1331 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1333 for (i = 0; i < no_of_chans; i++)
1334 dma_chan[channels[i]].chain_id = *chain_id;
1336 /* Reset the Queue pointers */
1337 OMAP_DMA_CHAIN_QINIT(*chain_id);
1339 /* Set up the chain */
1340 if (no_of_chans == 1)
1341 create_dma_lch_chain(channels[0], channels[0]);
1343 for (i = 0; i < (no_of_chans - 1); i++)
1344 create_dma_lch_chain(channels[i], channels[i + 1]);
1349 EXPORT_SYMBOL(omap_request_dma_chain);
1352 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1353 * params after setting it. Dont do this while dma is running!!
1355 * @param chain_id - Chained logical channel id.
1358 * @return - Success : 0
1361 int omap_modify_dma_chain_params(int chain_id,
1362 struct omap_dma_channel_params params)
1367 /* Check for input params */
1368 if (unlikely((chain_id < 0
1369 || chain_id >= dma_lch_count))) {
1370 printk(KERN_ERR "Invalid chain id\n");
1374 /* Check if the chain exists */
1375 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1376 printk(KERN_ERR "Chain doesn't exists\n");
1379 channels = dma_linked_lch[chain_id].linked_dmach_q;
1381 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1383 * Allowing client drivers to set common parameters now,
1384 * so that later only relevant (src_start, dest_start
1385 * and element count) can be set
1387 omap_set_dma_params(channels[i], ¶ms);
1392 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1395 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1399 * @return - Success : 0
1402 int omap_free_dma_chain(int chain_id)
1407 /* Check for input params */
1408 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1409 printk(KERN_ERR "Invalid chain id\n");
1413 /* Check if the chain exists */
1414 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1415 printk(KERN_ERR "Chain doesn't exists\n");
1419 channels = dma_linked_lch[chain_id].linked_dmach_q;
1420 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1421 dma_chan[channels[i]].next_linked_ch = -1;
1422 dma_chan[channels[i]].prev_linked_ch = -1;
1423 dma_chan[channels[i]].chain_id = -1;
1424 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1425 omap_free_dma(channels[i]);
1430 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1431 dma_linked_lch[chain_id].chain_mode = -1;
1432 dma_linked_lch[chain_id].chain_state = -1;
1436 EXPORT_SYMBOL(omap_free_dma_chain);
1439 * @brief omap_dma_chain_status - Check if the chain is in
1440 * active / inactive state.
1443 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1446 int omap_dma_chain_status(int chain_id)
1448 /* Check for input params */
1449 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1450 printk(KERN_ERR "Invalid chain id\n");
1454 /* Check if the chain exists */
1455 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1456 printk(KERN_ERR "Chain doesn't exists\n");
1459 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1460 dma_linked_lch[chain_id].q_count);
1462 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1463 return OMAP_DMA_CHAIN_INACTIVE;
1465 return OMAP_DMA_CHAIN_ACTIVE;
1467 EXPORT_SYMBOL(omap_dma_chain_status);
1470 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1471 * set the params and start the transfer.
1474 * @param src_start - buffer start address
1475 * @param dest_start - Dest address
1477 * @param frame_count
1478 * @param callbk_data - channel callback parameter data.
1480 * @return - Success : 0
1481 * Failure: -EINVAL/-EBUSY
1483 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1484 int elem_count, int frame_count, void *callbk_data)
1491 * if buffer size is less than 1 then there is
1492 * no use of starting the chain
1494 if (elem_count < 1) {
1495 printk(KERN_ERR "Invalid buffer size\n");
1499 /* Check for input params */
1500 if (unlikely((chain_id < 0
1501 || chain_id >= dma_lch_count))) {
1502 printk(KERN_ERR "Invalid chain id\n");
1506 /* Check if the chain exists */
1507 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1508 printk(KERN_ERR "Chain doesn't exist\n");
1512 /* Check if all the channels in chain are in use */
1513 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1516 /* Frame count may be negative in case of indexed transfers */
1517 channels = dma_linked_lch[chain_id].linked_dmach_q;
1519 /* Get a free channel */
1520 lch = channels[dma_linked_lch[chain_id].q_tail];
1522 /* Store the callback data */
1523 dma_chan[lch].data = callbk_data;
1525 /* Increment the q_tail */
1526 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1528 /* Set the params to the free channel */
1530 dma_write(src_start, CSSA(lch));
1531 if (dest_start != 0)
1532 dma_write(dest_start, CDSA(lch));
1534 /* Write the buffer size */
1535 dma_write(elem_count, CEN(lch));
1536 dma_write(frame_count, CFN(lch));
1539 * If the chain is dynamically linked,
1540 * then we may have to start the chain if its not active
1542 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1545 * In Dynamic chain, if the chain is not started,
1548 if (dma_linked_lch[chain_id].chain_state ==
1549 DMA_CHAIN_NOTSTARTED) {
1550 /* Enable the link in previous channel */
1551 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1553 enable_lnk(dma_chan[lch].prev_linked_ch);
1554 dma_chan[lch].state = DMA_CH_QUEUED;
1558 * Chain is already started, make sure its active,
1559 * if not then start the chain
1564 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1566 enable_lnk(dma_chan[lch].prev_linked_ch);
1567 dma_chan[lch].state = DMA_CH_QUEUED;
1569 if (0 == ((1 << 7) & dma_read(
1570 CCR(dma_chan[lch].prev_linked_ch)))) {
1571 disable_lnk(dma_chan[lch].
1573 pr_debug("\n prev ch is stopped\n");
1578 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1580 enable_lnk(dma_chan[lch].prev_linked_ch);
1581 dma_chan[lch].state = DMA_CH_QUEUED;
1584 omap_enable_channel_irq(lch);
1586 l = dma_read(CCR(lch));
1588 if ((0 == (l & (1 << 24))))
1592 if (start_dma == 1) {
1593 if (0 == (l & (1 << 7))) {
1595 dma_chan[lch].state = DMA_CH_STARTED;
1596 pr_debug("starting %d\n", lch);
1597 dma_write(l, CCR(lch));
1601 if (0 == (l & (1 << 7)))
1602 dma_write(l, CCR(lch));
1604 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1610 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1613 * @brief omap_start_dma_chain_transfers - Start the chain
1617 * @return - Success : 0
1618 * Failure : -EINVAL/-EBUSY
1620 int omap_start_dma_chain_transfers(int chain_id)
1625 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1626 printk(KERN_ERR "Invalid chain id\n");
1630 channels = dma_linked_lch[chain_id].linked_dmach_q;
1632 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1633 printk(KERN_ERR "Chain is already started\n");
1637 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1638 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1640 enable_lnk(channels[i]);
1641 omap_enable_channel_irq(channels[i]);
1644 omap_enable_channel_irq(channels[0]);
1647 l = dma_read(CCR(channels[0]));
1649 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1650 dma_chan[channels[0]].state = DMA_CH_STARTED;
1652 if ((0 == (l & (1 << 24))))
1656 dma_write(l, CCR(channels[0]));
1658 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1662 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1665 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1669 * @return - Success : 0
1672 int omap_stop_dma_chain_transfers(int chain_id)
1678 /* Check for input params */
1679 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1680 printk(KERN_ERR "Invalid chain id\n");
1684 /* Check if the chain exists */
1685 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1686 printk(KERN_ERR "Chain doesn't exists\n");
1689 channels = dma_linked_lch[chain_id].linked_dmach_q;
1693 * Special programming model needed to disable DMA before end of block
1695 sys_cf = dma_read(OCP_SYSCONFIG);
1697 /* Middle mode reg set no Standby */
1698 l &= ~((1 << 12)|(1 << 13));
1699 dma_write(l, OCP_SYSCONFIG);
1701 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1703 /* Stop the Channel transmission */
1704 l = dma_read(CCR(channels[i]));
1706 dma_write(l, CCR(channels[i]));
1708 /* Disable the link in all the channels */
1709 disable_lnk(channels[i]);
1710 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1713 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1715 /* Reset the Queue pointers */
1716 OMAP_DMA_CHAIN_QINIT(chain_id);
1718 /* Errata - put in the old value */
1719 dma_write(sys_cf, OCP_SYSCONFIG);
1723 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1725 /* Get the index of the ongoing DMA in chain */
1727 * @brief omap_get_dma_chain_index - Get the element and frame index
1728 * of the ongoing DMA in chain
1731 * @param ei - Element index
1732 * @param fi - Frame index
1734 * @return - Success : 0
1737 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1742 /* Check for input params */
1743 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1744 printk(KERN_ERR "Invalid chain id\n");
1748 /* Check if the chain exists */
1749 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1750 printk(KERN_ERR "Chain doesn't exists\n");
1756 channels = dma_linked_lch[chain_id].linked_dmach_q;
1758 /* Get the current channel */
1759 lch = channels[dma_linked_lch[chain_id].q_head];
1761 *ei = dma_read(CCEN(lch));
1762 *fi = dma_read(CCFN(lch));
1766 EXPORT_SYMBOL(omap_get_dma_chain_index);
1769 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1770 * ongoing DMA in chain
1774 * @return - Success : Destination position
1777 int omap_get_dma_chain_dst_pos(int chain_id)
1782 /* Check for input params */
1783 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1784 printk(KERN_ERR "Invalid chain id\n");
1788 /* Check if the chain exists */
1789 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1790 printk(KERN_ERR "Chain doesn't exists\n");
1794 channels = dma_linked_lch[chain_id].linked_dmach_q;
1796 /* Get the current channel */
1797 lch = channels[dma_linked_lch[chain_id].q_head];
1799 return dma_read(CDAC(lch));
1801 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1804 * @brief omap_get_dma_chain_src_pos - Get the source position
1805 * of the ongoing DMA in chain
1808 * @return - Success : Destination position
1811 int omap_get_dma_chain_src_pos(int chain_id)
1816 /* Check for input params */
1817 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1818 printk(KERN_ERR "Invalid chain id\n");
1822 /* Check if the chain exists */
1823 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1824 printk(KERN_ERR "Chain doesn't exists\n");
1828 channels = dma_linked_lch[chain_id].linked_dmach_q;
1830 /* Get the current channel */
1831 lch = channels[dma_linked_lch[chain_id].q_head];
1833 return dma_read(CSAC(lch));
1835 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1836 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1838 /*----------------------------------------------------------------------------*/
1840 #ifdef CONFIG_ARCH_OMAP1
1842 static int omap1_dma_handle_ch(int ch)
1846 if (enable_1510_mode && ch >= 6) {
1847 csr = dma_chan[ch].saved_csr;
1848 dma_chan[ch].saved_csr = 0;
1850 csr = dma_read(CSR(ch));
1851 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1852 dma_chan[ch + 6].saved_csr = csr >> 7;
1855 if ((csr & 0x3f) == 0)
1857 if (unlikely(dma_chan[ch].dev_id == -1)) {
1858 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1859 "%d (CSR %04x)\n", ch, csr);
1862 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1863 printk(KERN_WARNING "DMA timeout with device %d\n",
1864 dma_chan[ch].dev_id);
1865 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1866 printk(KERN_WARNING "DMA synchronization event drop occurred "
1867 "with device %d\n", dma_chan[ch].dev_id);
1868 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1869 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1870 if (likely(dma_chan[ch].callback != NULL))
1871 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1876 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1878 int ch = ((int) dev_id) - 1;
1882 int handled_now = 0;
1884 handled_now += omap1_dma_handle_ch(ch);
1885 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1886 handled_now += omap1_dma_handle_ch(ch + 6);
1889 handled += handled_now;
1892 return handled ? IRQ_HANDLED : IRQ_NONE;
1896 #define omap1_dma_irq_handler NULL
1899 #ifdef CONFIG_ARCH_OMAP2PLUS
1901 static int omap2_dma_handle_ch(int ch)
1903 u32 status = dma_read(CSR(ch));
1906 if (printk_ratelimit())
1907 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1909 dma_write(1 << ch, IRQSTATUS_L0);
1912 if (unlikely(dma_chan[ch].dev_id == -1)) {
1913 if (printk_ratelimit())
1914 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1915 "channel %d\n", status, ch);
1918 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1920 "DMA synchronization event drop occurred with device "
1921 "%d\n", dma_chan[ch].dev_id);
1922 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1923 printk(KERN_INFO "DMA transaction error with device %d\n",
1924 dma_chan[ch].dev_id);
1925 if (cpu_class_is_omap2()) {
1927 * Errata: sDMA Channel is not disabled
1928 * after a transaction error. So we explicitely
1929 * disable the channel
1933 ccr = dma_read(CCR(ch));
1934 ccr &= ~OMAP_DMA_CCR_EN;
1935 dma_write(ccr, CCR(ch));
1936 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1939 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1940 printk(KERN_INFO "DMA secure error with device %d\n",
1941 dma_chan[ch].dev_id);
1942 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1943 printk(KERN_INFO "DMA misaligned error with device %d\n",
1944 dma_chan[ch].dev_id);
1946 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1947 dma_write(1 << ch, IRQSTATUS_L0);
1949 /* If the ch is not chained then chain_id will be -1 */
1950 if (dma_chan[ch].chain_id != -1) {
1951 int chain_id = dma_chan[ch].chain_id;
1952 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1953 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1954 dma_chan[dma_chan[ch].next_linked_ch].state =
1956 if (dma_linked_lch[chain_id].chain_mode ==
1957 OMAP_DMA_DYNAMIC_CHAIN)
1960 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1961 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1963 status = dma_read(CSR(ch));
1966 dma_write(status, CSR(ch));
1968 if (likely(dma_chan[ch].callback != NULL))
1969 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1974 /* STATUS register count is from 1-32 while our is 0-31 */
1975 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1977 u32 val, enable_reg;
1980 val = dma_read(IRQSTATUS_L0);
1982 if (printk_ratelimit())
1983 printk(KERN_WARNING "Spurious DMA IRQ\n");
1986 enable_reg = dma_read(IRQENABLE_L0);
1987 val &= enable_reg; /* Dispatch only relevant interrupts */
1988 for (i = 0; i < dma_lch_count && val != 0; i++) {
1990 omap2_dma_handle_ch(i);
1997 static struct irqaction omap24xx_dma_irq = {
1999 .handler = omap2_dma_irq_handler,
2000 .flags = IRQF_DISABLED
2004 static struct irqaction omap24xx_dma_irq;
2007 /*----------------------------------------------------------------------------*/
2009 void omap_dma_global_context_save(void)
2011 omap_dma_global_context.dma_irqenable_l0 =
2012 dma_read(IRQENABLE_L0);
2013 omap_dma_global_context.dma_ocp_sysconfig =
2014 dma_read(OCP_SYSCONFIG);
2015 omap_dma_global_context.dma_gcr = dma_read(GCR);
2018 void omap_dma_global_context_restore(void)
2022 dma_write(omap_dma_global_context.dma_gcr, GCR);
2023 dma_write(omap_dma_global_context.dma_ocp_sysconfig,
2025 dma_write(omap_dma_global_context.dma_irqenable_l0,
2029 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
2030 * after secure sram context save and restore. Hence we need to
2031 * manually clear those IRQs to avoid spurious interrupts. This
2032 * affects only secure devices.
2034 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
2035 dma_write(0x3 , IRQSTATUS_L0);
2037 for (ch = 0; ch < dma_chan_count; ch++)
2038 if (dma_chan[ch].dev_id != -1)
2042 /*----------------------------------------------------------------------------*/
2044 static int __init omap_init_dma(void)
2049 if (cpu_class_is_omap1()) {
2050 base = OMAP1_DMA_BASE;
2051 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2052 } else if (cpu_is_omap24xx()) {
2053 base = OMAP24XX_DMA4_BASE;
2054 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2055 } else if (cpu_is_omap34xx()) {
2056 base = OMAP34XX_DMA4_BASE;
2057 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2058 } else if (cpu_is_omap44xx()) {
2059 base = OMAP44XX_DMA4_BASE;
2060 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2062 pr_err("DMA init failed for unsupported omap\n");
2066 omap_dma_base = ioremap(base, SZ_4K);
2067 BUG_ON(!omap_dma_base);
2069 if (cpu_class_is_omap2() && omap_dma_reserve_channels
2070 && (omap_dma_reserve_channels <= dma_lch_count))
2071 dma_lch_count = omap_dma_reserve_channels;
2073 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2080 if (cpu_class_is_omap2()) {
2081 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2082 dma_lch_count, GFP_KERNEL);
2083 if (!dma_linked_lch) {
2089 if (cpu_is_omap15xx()) {
2090 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2092 enable_1510_mode = 1;
2093 } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2094 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2096 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2097 (dma_read(CAPS_0_U) << 16) |
2099 (dma_read(CAPS_1_U) << 16) |
2101 dma_read(CAPS_2), dma_read(CAPS_3),
2103 if (!enable_1510_mode) {
2106 /* Disable OMAP 3.0/3.1 compatibility mode. */
2110 dma_chan_count = 16;
2113 } else if (cpu_class_is_omap2()) {
2114 u8 revision = dma_read(REVISION) & 0xff;
2115 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2116 revision >> 4, revision & 0xf);
2117 dma_chan_count = dma_lch_count;
2123 spin_lock_init(&dma_chan_lock);
2125 for (ch = 0; ch < dma_chan_count; ch++) {
2127 if (cpu_class_is_omap2())
2128 omap2_disable_irq_lch(ch);
2130 dma_chan[ch].dev_id = -1;
2131 dma_chan[ch].next_lch = -1;
2133 if (ch >= 6 && enable_1510_mode)
2136 if (cpu_class_is_omap1()) {
2138 * request_irq() doesn't like dev_id (ie. ch) being
2139 * zero, so we have to kludge around this.
2141 r = request_irq(omap1_dma_irq[ch],
2142 omap1_dma_irq_handler, 0, "DMA",
2147 printk(KERN_ERR "unable to request IRQ %d "
2148 "for DMA (error %d)\n",
2149 omap1_dma_irq[ch], r);
2150 for (i = 0; i < ch; i++)
2151 free_irq(omap1_dma_irq[i],
2158 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2159 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2160 DMA_DEFAULT_FIFO_DEPTH, 0);
2162 if (cpu_class_is_omap2()) {
2164 if (cpu_is_omap44xx())
2165 irq = OMAP44XX_IRQ_SDMA_0;
2167 irq = INT_24XX_SDMA_IRQ0;
2168 setup_irq(irq, &omap24xx_dma_irq);
2171 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
2172 /* Enable smartidle idlemodes and autoidle */
2173 u32 v = dma_read(OCP_SYSCONFIG);
2174 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2175 DMA_SYSCONFIG_SIDLEMODE_MASK |
2176 DMA_SYSCONFIG_AUTOIDLE);
2177 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2178 DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2179 DMA_SYSCONFIG_AUTOIDLE);
2180 dma_write(v , OCP_SYSCONFIG);
2181 /* reserve dma channels 0 and 1 in high security devices */
2182 if (cpu_is_omap34xx() &&
2183 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2184 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2186 dma_chan[0].dev_id = 0;
2187 dma_chan[1].dev_id = 1;
2197 iounmap(omap_dma_base);
2202 arch_initcall(omap_init_dma);
2205 * Reserve the omap SDMA channels using cmdline bootarg
2206 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2208 static int __init omap_dma_cmdline_reserve_ch(char *str)
2210 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2211 omap_dma_reserve_channels = 0;
2215 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);