arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15  *
  16  * Support functions for the OMAP internal DMA channels.
  17  *
  18  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  19  * Converted DMA library into DMA platform driver.
  20  *      - G, Manjunath Kondaiah <manjugk@ti.com>
  21  *
  22  * This program is free software; you can redistribute it and/or modify
  23  * it under the terms of the GNU General Public License version 2 as
  24  * published by the Free Software Foundation.
  25  *
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/sched.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/errno.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/irq.h>
  35 #include <linux/io.h>
  36 #include <linux/slab.h>
  37 #include <linux/delay.h>
  38
  39 #include <asm/system.h>
  40 #include <mach/hardware.h>
  41 #include <plat/dma.h>
  42
  43 #include <plat/tc.h>
  44
  45 #undef DEBUG
  46
  47 #ifndef CONFIG_ARCH_OMAP1
  48 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  49         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  50 };
  51
  52 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  53 #endif
  54
  55 #define OMAP_DMA_ACTIVE                 0x01
  56 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffffffff
  57
  58 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  59
  60 static struct omap_system_dma_plat_info *p;
  61 static struct omap_dma_dev_attr *d;
  62
  63 static int enable_1510_mode;
  64 static u32 errata;
  65
  66 static struct omap_dma_global_context_registers {
  67         u32 dma_irqenable_l0;
  68         u32 dma_ocp_sysconfig;
  69         u32 dma_gcr;
  70 } omap_dma_global_context;
  71
  72 struct dma_link_info {
  73         int *linked_dmach_q;
  74         int no_of_lchs_linked;
  75
  76         int q_count;
  77         int q_tail;
  78         int q_head;
  79
  80         int chain_state;
  81         int chain_mode;
  82
  83 };
  84
  85 static struct dma_link_info *dma_linked_lch;
  86
  87 #ifndef CONFIG_ARCH_OMAP1
  88
  89 /* Chain handling macros */
  90 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  91         do {                                                            \
  92                 dma_linked_lch[chain_id].q_head =                       \
  93                 dma_linked_lch[chain_id].q_tail =                       \
  94                 dma_linked_lch[chain_id].q_count = 0;                   \
  95         } while (0)
  96 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
  97                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
  98                 dma_linked_lch[chain_id].q_count)
  99 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 100         do {                                                            \
 101                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 102                 dma_linked_lch[chain_id].q_count)                       \
 103         } while (0)
 104 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 105                 (0 == dma_linked_lch[chain_id].q_count)
 106 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 107         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 108 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 109         do {                                                            \
 110                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 111                 dma_linked_lch[chain_id].q_count--;                     \
 112         } while (0)
 113
 114 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 115         do {                                                            \
 116                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 117                 dma_linked_lch[chain_id].q_count++; \
 118         } while (0)
 119 #endif
 120
 121 static int dma_lch_count;
 122 static int dma_chan_count;
 123 static int omap_dma_reserve_channels;
 124
 125 static spinlock_t dma_chan_lock;
 126 static struct omap_dma_lch *dma_chan;
 127
 128 static inline void disable_lnk(int lch);
 129 static void omap_disable_channel_irq(int lch);
 130 static inline void omap_enable_channel_irq(int lch);
 131
 132 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 133                                                 __func__);
 134
 135 #ifdef CONFIG_ARCH_OMAP15XX
 136 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 137 static int omap_dma_in_1510_mode(void)
 138 {
 139         return enable_1510_mode;
 140 }
 141 #else
 142 #define omap_dma_in_1510_mode()         0
 143 #endif
 144
 145 #ifdef CONFIG_ARCH_OMAP1
 146 static inline int get_gdma_dev(int req)
 147 {
 148         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 149         int shift = ((req - 1) % 5) * 6;
 150
 151         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 152 }
 153
 154 static inline void set_gdma_dev(int req, int dev)
 155 {
 156         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 157         int shift = ((req - 1) % 5) * 6;
 158         u32 l;
 159
 160         l = omap_readl(reg);
 161         l &= ~(0x3f << shift);
 162         l |= (dev - 1) << shift;
 163         omap_writel(l, reg);
 164 }
 165 #else
 166 #define set_gdma_dev(req, dev)  do {} while (0)
 167 #define omap_readl(reg)         0
 168 #define omap_writel(val, reg)   do {} while (0)
 169 #endif
 170
 171 void omap_set_dma_priority(int lch, int dst_port, int priority)
 172 {
 173         unsigned long reg;
 174         u32 l;
 175
 176         if (cpu_class_is_omap1()) {
 177                 switch (dst_port) {
 178                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 179                         reg = OMAP_TC_OCPT1_PRIOR;
 180                         break;
 181                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 182                         reg = OMAP_TC_OCPT2_PRIOR;
 183                         break;
 184                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 185                         reg = OMAP_TC_EMIFF_PRIOR;
 186                         break;
 187                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 188                         reg = OMAP_TC_EMIFS_PRIOR;
 189                         break;
 190                 default:
 191                         BUG();
 192                         return;
 193                 }
 194                 l = omap_readl(reg);
 195                 l &= ~(0xf << 8);
 196                 l |= (priority & 0xf) << 8;
 197                 omap_writel(l, reg);
 198         }
 199
 200         if (cpu_class_is_omap2()) {
 201                 u32 ccr;
 202
 203                 ccr = p->dma_read(CCR, lch);
 204                 if (priority)
 205                         ccr |= (1 << 6);
 206                 else
 207                         ccr &= ~(1 << 6);
 208                 p->dma_write(ccr, CCR, lch);
 209         }
 210 }
 211 EXPORT_SYMBOL(omap_set_dma_priority);
 212
 213 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 214                                   int frame_count, int sync_mode,
 215                                   int dma_trigger, int src_or_dst_synch)
 216 {
 217         u32 l;
 218
 219         l = p->dma_read(CSDP, lch);
 220         l &= ~0x03;
 221         l |= data_type;
 222         p->dma_write(l, CSDP, lch);
 223
 224         if (cpu_class_is_omap1()) {
 225                 u16 ccr;
 226
 227                 ccr = p->dma_read(CCR, lch);
 228                 ccr &= ~(1 << 5);
 229                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 230                         ccr |= 1 << 5;
 231                 p->dma_write(ccr, CCR, lch);
 232
 233                 ccr = p->dma_read(CCR2, lch);
 234                 ccr &= ~(1 << 2);
 235                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 236                         ccr |= 1 << 2;
 237                 p->dma_write(ccr, CCR2, lch);
 238         }
 239
 240         if (cpu_class_is_omap2() && dma_trigger) {
 241                 u32 val;
 242
 243                 val = p->dma_read(CCR, lch);
 244
 245                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 246                 val &= ~((1 << 23) | (3 << 19) | 0x1f);
 247                 val |= (dma_trigger & ~0x1f) << 14;
 248                 val |= dma_trigger & 0x1f;
 249
 250                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 251                         val |= 1 << 5;
 252                 else
 253                         val &= ~(1 << 5);
 254
 255                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 256                         val |= 1 << 18;
 257                 else
 258                         val &= ~(1 << 18);
 259
 260                 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
 261                         val &= ~(1 << 24);      /* dest synch */
 262                         val |= (1 << 23);       /* Prefetch */
 263                 } else if (src_or_dst_synch) {
 264                         val |= 1 << 24;         /* source synch */
 265                 } else {
 266                         val &= ~(1 << 24);      /* dest synch */
 267                 }
 268                 p->dma_write(val, CCR, lch);
 269         }
 270
 271         p->dma_write(elem_count, CEN, lch);
 272         p->dma_write(frame_count, CFN, lch);
 273 }
 274 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 275
 276 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 277 {
 278         BUG_ON(omap_dma_in_1510_mode());
 279
 280         if (cpu_class_is_omap1()) {
 281                 u16 w;
 282
 283                 w = p->dma_read(CCR2, lch);
 284                 w &= ~0x03;
 285
 286                 switch (mode) {
 287                 case OMAP_DMA_CONSTANT_FILL:
 288                         w |= 0x01;
 289                         break;
 290                 case OMAP_DMA_TRANSPARENT_COPY:
 291                         w |= 0x02;
 292                         break;
 293                 case OMAP_DMA_COLOR_DIS:
 294                         break;
 295                 default:
 296                         BUG();
 297                 }
 298                 p->dma_write(w, CCR2, lch);
 299
 300                 w = p->dma_read(LCH_CTRL, lch);
 301                 w &= ~0x0f;
 302                 /* Default is channel type 2D */
 303                 if (mode) {
 304                         p->dma_write(color, COLOR, lch);
 305                         w |= 1;         /* Channel type G */
 306                 }
 307                 p->dma_write(w, LCH_CTRL, lch);
 308         }
 309
 310         if (cpu_class_is_omap2()) {
 311                 u32 val;
 312
 313                 val = p->dma_read(CCR, lch);
 314                 val &= ~((1 << 17) | (1 << 16));
 315
 316                 switch (mode) {
 317                 case OMAP_DMA_CONSTANT_FILL:
 318                         val |= 1 << 16;
 319                         break;
 320                 case OMAP_DMA_TRANSPARENT_COPY:
 321                         val |= 1 << 17;
 322                         break;
 323                 case OMAP_DMA_COLOR_DIS:
 324                         break;
 325                 default:
 326                         BUG();
 327                 }
 328                 p->dma_write(val, CCR, lch);
 329
 330                 color &= 0xffffff;
 331                 p->dma_write(color, COLOR, lch);
 332         }
 333 }
 334 EXPORT_SYMBOL(omap_set_dma_color_mode);
 335
 336 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 337 {
 338         if (cpu_class_is_omap2()) {
 339                 u32 csdp;
 340
 341                 csdp = p->dma_read(CSDP, lch);
 342                 csdp &= ~(0x3 << 16);
 343                 csdp |= (mode << 16);
 344                 p->dma_write(csdp, CSDP, lch);
 345         }
 346 }
 347 EXPORT_SYMBOL(omap_set_dma_write_mode);
 348
 349 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 350 {
 351         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
 352                 u32 l;
 353
 354                 l = p->dma_read(LCH_CTRL, lch);
 355                 l &= ~0x7;
 356                 l |= mode;
 357                 p->dma_write(l, LCH_CTRL, lch);
 358         }
 359 }
 360 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 361
 362 /* Note that src_port is only for omap1 */
 363 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 364                              unsigned long src_start,
 365                              int src_ei, int src_fi)
 366 {
 367         u32 l;
 368
 369         if (cpu_class_is_omap1()) {
 370                 u16 w;
 371
 372                 w = p->dma_read(CSDP, lch);
 373                 w &= ~(0x1f << 2);
 374                 w |= src_port << 2;
 375                 p->dma_write(w, CSDP, lch);
 376         }
 377
 378         l = p->dma_read(CCR, lch);
 379         l &= ~(0x03 << 12);
 380         l |= src_amode << 12;
 381         p->dma_write(l, CCR, lch);
 382
 383         p->dma_write(src_start, CSSA, lch);
 384
 385         p->dma_write(src_ei, CSEI, lch);
 386         p->dma_write(src_fi, CSFI, lch);
 387 }
 388 EXPORT_SYMBOL(omap_set_dma_src_params);
 389
 390 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 391 {
 392         omap_set_dma_transfer_params(lch, params->data_type,
 393                                      params->elem_count, params->frame_count,
 394                                      params->sync_mode, params->trigger,
 395                                      params->src_or_dst_synch);
 396         omap_set_dma_src_params(lch, params->src_port,
 397                                 params->src_amode, params->src_start,
 398                                 params->src_ei, params->src_fi);
 399
 400         omap_set_dma_dest_params(lch, params->dst_port,
 401                                  params->dst_amode, params->dst_start,
 402                                  params->dst_ei, params->dst_fi);
 403         if (params->read_prio || params->write_prio)
 404                 omap_dma_set_prio_lch(lch, params->read_prio,
 405                                       params->write_prio);
 406 }
 407 EXPORT_SYMBOL(omap_set_dma_params);
 408
 409 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 410 {
 411         if (cpu_class_is_omap2())
 412                 return;
 413
 414         p->dma_write(eidx, CSEI, lch);
 415         p->dma_write(fidx, CSFI, lch);
 416 }
 417 EXPORT_SYMBOL(omap_set_dma_src_index);
 418
 419 void omap_set_dma_src_data_pack(int lch, int enable)
 420 {
 421         u32 l;
 422
 423         l = p->dma_read(CSDP, lch);
 424         l &= ~(1 << 6);
 425         if (enable)
 426                 l |= (1 << 6);
 427         p->dma_write(l, CSDP, lch);
 428 }
 429 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 430
 431 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 432 {
 433         unsigned int burst = 0;
 434         u32 l;
 435
 436         l = p->dma_read(CSDP, lch);
 437         l &= ~(0x03 << 7);
 438
 439         switch (burst_mode) {
 440         case OMAP_DMA_DATA_BURST_DIS:
 441                 break;
 442         case OMAP_DMA_DATA_BURST_4:
 443                 if (cpu_class_is_omap2())
 444                         burst = 0x1;
 445                 else
 446                         burst = 0x2;
 447                 break;
 448         case OMAP_DMA_DATA_BURST_8:
 449                 if (cpu_class_is_omap2()) {
 450                         burst = 0x2;
 451                         break;
 452                 }
 453                 /*
 454                  * not supported by current hardware on OMAP1
 455                  * w |= (0x03 << 7);
 456                  * fall through
 457                  */
 458         case OMAP_DMA_DATA_BURST_16:
 459                 if (cpu_class_is_omap2()) {
 460                         burst = 0x3;
 461                         break;
 462                 }
 463                 /*
 464                  * OMAP1 don't support burst 16
 465                  * fall through
 466                  */
 467         default:
 468                 BUG();
 469         }
 470
 471         l |= (burst << 7);
 472         p->dma_write(l, CSDP, lch);
 473 }
 474 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 475
 476 /* Note that dest_port is only for OMAP1 */
 477 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 478                               unsigned long dest_start,
 479                               int dst_ei, int dst_fi)
 480 {
 481         u32 l;
 482
 483         if (cpu_class_is_omap1()) {
 484                 l = p->dma_read(CSDP, lch);
 485                 l &= ~(0x1f << 9);
 486                 l |= dest_port << 9;
 487                 p->dma_write(l, CSDP, lch);
 488         }
 489
 490         l = p->dma_read(CCR, lch);
 491         l &= ~(0x03 << 14);
 492         l |= dest_amode << 14;
 493         p->dma_write(l, CCR, lch);
 494
 495         p->dma_write(dest_start, CDSA, lch);
 496
 497         p->dma_write(dst_ei, CDEI, lch);
 498         p->dma_write(dst_fi, CDFI, lch);
 499 }
 500 EXPORT_SYMBOL(omap_set_dma_dest_params);
 501
 502 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 503 {
 504         if (cpu_class_is_omap2())
 505                 return;
 506
 507         p->dma_write(eidx, CDEI, lch);
 508         p->dma_write(fidx, CDFI, lch);
 509 }
 510 EXPORT_SYMBOL(omap_set_dma_dest_index);
 511
 512 void omap_set_dma_dest_data_pack(int lch, int enable)
 513 {
 514         u32 l;
 515
 516         l = p->dma_read(CSDP, lch);
 517         l &= ~(1 << 13);
 518         if (enable)
 519                 l |= 1 << 13;
 520         p->dma_write(l, CSDP, lch);
 521 }
 522 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 523
 524 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 525 {
 526         unsigned int burst = 0;
 527         u32 l;
 528
 529         l = p->dma_read(CSDP, lch);
 530         l &= ~(0x03 << 14);
 531
 532         switch (burst_mode) {
 533         case OMAP_DMA_DATA_BURST_DIS:
 534                 break;
 535         case OMAP_DMA_DATA_BURST_4:
 536                 if (cpu_class_is_omap2())
 537                         burst = 0x1;
 538                 else
 539                         burst = 0x2;
 540                 break;
 541         case OMAP_DMA_DATA_BURST_8:
 542                 if (cpu_class_is_omap2())
 543                         burst = 0x2;
 544                 else
 545                         burst = 0x3;
 546                 break;
 547         case OMAP_DMA_DATA_BURST_16:
 548                 if (cpu_class_is_omap2()) {
 549                         burst = 0x3;
 550                         break;
 551                 }
 552                 /*
 553                  * OMAP1 don't support burst 16
 554                  * fall through
 555                  */
 556         default:
 557                 printk(KERN_ERR "Invalid DMA burst mode\n");
 558                 BUG();
 559                 return;
 560         }
 561         l |= (burst << 14);
 562         p->dma_write(l, CSDP, lch);
 563 }
 564 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 565
 566 static inline void omap_enable_channel_irq(int lch)
 567 {
 568         u32 status;
 569
 570         /* Clear CSR */
 571         if (cpu_class_is_omap1())
 572                 status = p->dma_read(CSR, lch);
 573         else if (cpu_class_is_omap2())
 574                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 575
 576         /* Enable some nice interrupts. */
 577         p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
 578 }
 579
 580 static void omap_disable_channel_irq(int lch)
 581 {
 582         if (cpu_class_is_omap2())
 583                 p->dma_write(0, CICR, lch);
 584 }
 585
 586 void omap_enable_dma_irq(int lch, u16 bits)
 587 {
 588         dma_chan[lch].enabled_irqs |= bits;
 589 }
 590 EXPORT_SYMBOL(omap_enable_dma_irq);
 591
 592 void omap_disable_dma_irq(int lch, u16 bits)
 593 {
 594         dma_chan[lch].enabled_irqs &= ~bits;
 595 }
 596 EXPORT_SYMBOL(omap_disable_dma_irq);
 597
 598 static inline void enable_lnk(int lch)
 599 {
 600         u32 l;
 601
 602         l = p->dma_read(CLNK_CTRL, lch);
 603
 604         if (cpu_class_is_omap1())
 605                 l &= ~(1 << 14);
 606
 607         /* Set the ENABLE_LNK bits */
 608         if (dma_chan[lch].next_lch != -1)
 609                 l = dma_chan[lch].next_lch | (1 << 15);
 610
 611 #ifndef CONFIG_ARCH_OMAP1
 612         if (cpu_class_is_omap2())
 613                 if (dma_chan[lch].next_linked_ch != -1)
 614                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 615 #endif
 616
 617         p->dma_write(l, CLNK_CTRL, lch);
 618 }
 619
 620 static inline void disable_lnk(int lch)
 621 {
 622         u32 l;
 623
 624         l = p->dma_read(CLNK_CTRL, lch);
 625
 626         /* Disable interrupts */
 627         if (cpu_class_is_omap1()) {
 628                 p->dma_write(0, CICR, lch);
 629                 /* Set the STOP_LNK bit */
 630                 l |= 1 << 14;
 631         }
 632
 633         if (cpu_class_is_omap2()) {
 634                 omap_disable_channel_irq(lch);
 635                 /* Clear the ENABLE_LNK bit */
 636                 l &= ~(1 << 15);
 637         }
 638
 639         p->dma_write(l, CLNK_CTRL, lch);
 640         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 641 }
 642
 643 static inline void omap2_enable_irq_lch(int lch)
 644 {
 645         u32 val;
 646         unsigned long flags;
 647
 648         if (!cpu_class_is_omap2())
 649                 return;
 650
 651         spin_lock_irqsave(&dma_chan_lock, flags);
 652         val = p->dma_read(IRQENABLE_L0, lch);
 653         val |= 1 << lch;
 654         p->dma_write(val, IRQENABLE_L0, lch);
 655         spin_unlock_irqrestore(&dma_chan_lock, flags);
 656 }
 657
 658 static inline void omap2_disable_irq_lch(int lch)
 659 {
 660         u32 val;
 661         unsigned long flags;
 662
 663         if (!cpu_class_is_omap2())
 664                 return;
 665
 666         spin_lock_irqsave(&dma_chan_lock, flags);
 667         val = p->dma_read(IRQENABLE_L0, lch);
 668         val &= ~(1 << lch);
 669         p->dma_write(val, IRQENABLE_L0, lch);
 670         spin_unlock_irqrestore(&dma_chan_lock, flags);
 671 }
 672
 673 int omap_request_dma(int dev_id, const char *dev_name,
 674                      void (*callback)(int lch, u16 ch_status, void *data),
 675                      void *data, int *dma_ch_out)
 676 {
 677         int ch, free_ch = -1;
 678         unsigned long flags;
 679         struct omap_dma_lch *chan;
 680
 681         spin_lock_irqsave(&dma_chan_lock, flags);
 682         for (ch = 0; ch < dma_chan_count; ch++) {
 683                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 684                         free_ch = ch;
 685                         if (dev_id == 0)
 686                                 break;
 687                 }
 688         }
 689         if (free_ch == -1) {
 690                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 691                 return -EBUSY;
 692         }
 693         chan = dma_chan + free_ch;
 694         chan->dev_id = dev_id;
 695
 696         if (p->clear_lch_regs)
 697                 p->clear_lch_regs(free_ch);
 698
 699         if (cpu_class_is_omap2())
 700                 omap_clear_dma(free_ch);
 701
 702         spin_unlock_irqrestore(&dma_chan_lock, flags);
 703
 704         chan->dev_name = dev_name;
 705         chan->callback = callback;
 706         chan->data = data;
 707         chan->flags = 0;
 708
 709 #ifndef CONFIG_ARCH_OMAP1
 710         if (cpu_class_is_omap2()) {
 711                 chan->chain_id = -1;
 712                 chan->next_linked_ch = -1;
 713         }
 714 #endif
 715
 716         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 717
 718         if (cpu_class_is_omap1())
 719                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 720         else if (cpu_class_is_omap2())
 721                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 722                         OMAP2_DMA_TRANS_ERR_IRQ;
 723
 724         if (cpu_is_omap16xx()) {
 725                 /* If the sync device is set, configure it dynamically. */
 726                 if (dev_id != 0) {
 727                         set_gdma_dev(free_ch + 1, dev_id);
 728                         dev_id = free_ch + 1;
 729                 }
 730                 /*
 731                  * Disable the 1510 compatibility mode and set the sync device
 732                  * id.
 733                  */
 734                 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
 735         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
 736                 p->dma_write(dev_id, CCR, free_ch);
 737         }
 738
 739         if (cpu_class_is_omap2()) {
 740                 omap2_enable_irq_lch(free_ch);
 741                 omap_enable_channel_irq(free_ch);
 742                 /* Clear the CSR register and IRQ status register */
 743                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
 744                 p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
 745         }
 746
 747         *dma_ch_out = free_ch;
 748
 749         return 0;
 750 }
 751 EXPORT_SYMBOL(omap_request_dma);
 752
 753 void omap_free_dma(int lch)
 754 {
 755         unsigned long flags;
 756
 757         if (dma_chan[lch].dev_id == -1) {
 758                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 759                        lch);
 760                 return;
 761         }
 762
 763         if (cpu_class_is_omap1()) {
 764                 /* Disable all DMA interrupts for the channel. */
 765                 p->dma_write(0, CICR, lch);
 766                 /* Make sure the DMA transfer is stopped. */
 767                 p->dma_write(0, CCR, lch);
 768         }
 769
 770         if (cpu_class_is_omap2()) {
 771                 omap2_disable_irq_lch(lch);
 772
 773                 /* Clear the CSR register and IRQ status register */
 774                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 775                 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
 776
 777                 /* Disable all DMA interrupts for the channel. */
 778                 p->dma_write(0, CICR, lch);
 779
 780                 /* Make sure the DMA transfer is stopped. */
 781                 p->dma_write(0, CCR, lch);
 782                 omap_clear_dma(lch);
 783         }
 784
 785         spin_lock_irqsave(&dma_chan_lock, flags);
 786         dma_chan[lch].dev_id = -1;
 787         dma_chan[lch].next_lch = -1;
 788         dma_chan[lch].callback = NULL;
 789         spin_unlock_irqrestore(&dma_chan_lock, flags);
 790 }
 791 EXPORT_SYMBOL(omap_free_dma);
 792
 793 /**
 794  * @brief omap_dma_set_global_params : Set global priority settings for dma
 795  *
 796  * @param arb_rate
 797  * @param max_fifo_depth
 798  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
 799  *                                                 DMA_THREAD_RESERVE_ONET
 800  *                                                 DMA_THREAD_RESERVE_TWOT
 801  *                                                 DMA_THREAD_RESERVE_THREET
 802  */
 803 void
 804 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 805 {
 806         u32 reg;
 807
 808         if (!cpu_class_is_omap2()) {
 809                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 810                 return;
 811         }
 812
 813         if (max_fifo_depth == 0)
 814                 max_fifo_depth = 1;
 815         if (arb_rate == 0)
 816                 arb_rate = 1;
 817
 818         reg = 0xff & max_fifo_depth;
 819         reg |= (0x3 & tparams) << 12;
 820         reg |= (arb_rate & 0xff) << 16;
 821
 822         p->dma_write(reg, GCR, 0);
 823 }
 824 EXPORT_SYMBOL(omap_dma_set_global_params);
 825
 826 /**
 827  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 828  *
 829  * @param lch
 830  * @param read_prio - Read priority
 831  * @param write_prio - Write priority
 832  * Both of the above can be set with one of the following values :
 833  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 834  */
 835 int
 836 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 837                       unsigned char write_prio)
 838 {
 839         u32 l;
 840
 841         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 842                 printk(KERN_ERR "Invalid channel id\n");
 843                 return -EINVAL;
 844         }
 845         l = p->dma_read(CCR, lch);
 846         l &= ~((1 << 6) | (1 << 26));
 847         if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
 848                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 849         else
 850                 l |= ((read_prio & 0x1) << 6);
 851
 852         p->dma_write(l, CCR, lch);
 853
 854         return 0;
 855 }
 856 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 857
 858 /*
 859  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 860  * through omap_start_dma(). Any buffers in flight are discarded.
 861  */
 862 void omap_clear_dma(int lch)
 863 {
 864         unsigned long flags;
 865
 866         local_irq_save(flags);
 867         p->clear_dma(lch);
 868         local_irq_restore(flags);
 869 }
 870 EXPORT_SYMBOL(omap_clear_dma);
 871
 872 void omap_start_dma(int lch)
 873 {
 874         u32 l;
 875
 876         /*
 877          * The CPC/CDAC register needs to be initialized to zero
 878          * before starting dma transfer.
 879          */
 880         if (cpu_is_omap15xx())
 881                 p->dma_write(0, CPC, lch);
 882         else
 883                 p->dma_write(0, CDAC, lch);
 884
 885         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 886                 int next_lch, cur_lch;
 887                 char dma_chan_link_map[dma_lch_count];
 888
 889                 dma_chan_link_map[lch] = 1;
 890                 /* Set the link register of the first channel */
 891                 enable_lnk(lch);
 892
 893                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 894                 cur_lch = dma_chan[lch].next_lch;
 895                 do {
 896                         next_lch = dma_chan[cur_lch].next_lch;
 897
 898                         /* The loop case: we've been here already */
 899                         if (dma_chan_link_map[cur_lch])
 900                                 break;
 901                         /* Mark the current channel */
 902                         dma_chan_link_map[cur_lch] = 1;
 903
 904                         enable_lnk(cur_lch);
 905                         omap_enable_channel_irq(cur_lch);
 906
 907                         cur_lch = next_lch;
 908                 } while (next_lch != -1);
 909         } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
 910                 p->dma_write(lch, CLNK_CTRL, lch);
 911
 912         omap_enable_channel_irq(lch);
 913
 914         l = p->dma_read(CCR, lch);
 915
 916         if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
 917                         l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
 918         l |= OMAP_DMA_CCR_EN;
 919
 920         p->dma_write(l, CCR, lch);
 921
 922         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 923 }
 924 EXPORT_SYMBOL(omap_start_dma);
 925
 926 void omap_stop_dma(int lch)
 927 {
 928         u32 l;
 929
 930         /* Disable all interrupts on the channel */
 931         if (cpu_class_is_omap1())
 932                 p->dma_write(0, CICR, lch);
 933
 934         l = p->dma_read(CCR, lch);
 935         if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
 936                         (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
 937                 int i = 0;
 938                 u32 sys_cf;
 939
 940                 /* Configure No-Standby */
 941                 l = p->dma_read(OCP_SYSCONFIG, lch);
 942                 sys_cf = l;
 943                 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
 944                 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
 945                 p->dma_write(l , OCP_SYSCONFIG, 0);
 946
 947                 l = p->dma_read(CCR, lch);
 948                 l &= ~OMAP_DMA_CCR_EN;
 949                 p->dma_write(l, CCR, lch);
 950
 951                 /* Wait for sDMA FIFO drain */
 952                 l = p->dma_read(CCR, lch);
 953                 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
 954                                         OMAP_DMA_CCR_WR_ACTIVE))) {
 955                         udelay(5);
 956                         i++;
 957                         l = p->dma_read(CCR, lch);
 958                 }
 959                 if (i >= 100)
 960                         printk(KERN_ERR "DMA drain did not complete on "
 961                                         "lch %d\n", lch);
 962                 /* Restore OCP_SYSCONFIG */
 963                 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
 964         } else {
 965                 l &= ~OMAP_DMA_CCR_EN;
 966                 p->dma_write(l, CCR, lch);
 967         }
 968
 969         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 970                 int next_lch, cur_lch = lch;
 971                 char dma_chan_link_map[dma_lch_count];
 972
 973                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 974                 do {
 975                         /* The loop case: we've been here already */
 976                         if (dma_chan_link_map[cur_lch])
 977                                 break;
 978                         /* Mark the current channel */
 979                         dma_chan_link_map[cur_lch] = 1;
 980
 981                         disable_lnk(cur_lch);
 982
 983                         next_lch = dma_chan[cur_lch].next_lch;
 984                         cur_lch = next_lch;
 985                 } while (next_lch != -1);
 986         }
 987
 988         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 989 }
 990 EXPORT_SYMBOL(omap_stop_dma);
 991
 992 /*
 993  * Allows changing the DMA callback function or data. This may be needed if
 994  * the driver shares a single DMA channel for multiple dma triggers.
 995  */
 996 int omap_set_dma_callback(int lch,
 997                           void (*callback)(int lch, u16 ch_status, void *data),
 998                           void *data)
 999 {
1000         unsigned long flags;
1001
1002         if (lch < 0)
1003                 return -ENODEV;
1004
1005         spin_lock_irqsave(&dma_chan_lock, flags);
1006         if (dma_chan[lch].dev_id == -1) {
1007                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1008                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1009                 return -EINVAL;
1010         }
1011         dma_chan[lch].callback = callback;
1012         dma_chan[lch].data = data;
1013         spin_unlock_irqrestore(&dma_chan_lock, flags);
1014
1015         return 0;
1016 }
1017 EXPORT_SYMBOL(omap_set_dma_callback);
1018
1019 /*
1020  * Returns current physical source address for the given DMA channel.
1021  * If the channel is running the caller must disable interrupts prior calling
1022  * this function and process the returned value before re-enabling interrupt to
1023  * prevent races with the interrupt handler. Note that in continuous mode there
1024  * is a chance for CSSA_L register overflow between the two reads resulting
1025  * in incorrect return value.
1026  */
1027 dma_addr_t omap_get_dma_src_pos(int lch)
1028 {
1029         dma_addr_t offset = 0;
1030
1031         if (cpu_is_omap15xx())
1032                 offset = p->dma_read(CPC, lch);
1033         else
1034                 offset = p->dma_read(CSAC, lch);
1035
1036         if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1037                 offset = p->dma_read(CSAC, lch);
1038
1039         if (!cpu_is_omap15xx()) {
1040                 /*
1041                  * CDAC == 0 indicates that the DMA transfer on the channel has
1042                  * not been started (no data has been transferred so far).
1043                  * Return the programmed source start address in this case.
1044                  */
1045                 if (likely(p->dma_read(CDAC, lch)))
1046                         offset = p->dma_read(CSAC, lch);
1047                 else
1048                         offset = p->dma_read(CSSA, lch);
1049         }
1050
1051         if (cpu_class_is_omap1())
1052                 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1053
1054         return offset;
1055 }
1056 EXPORT_SYMBOL(omap_get_dma_src_pos);
1057
1058 /*
1059  * Returns current physical destination address for the given DMA channel.
1060  * If the channel is running the caller must disable interrupts prior calling
1061  * this function and process the returned value before re-enabling interrupt to
1062  * prevent races with the interrupt handler. Note that in continuous mode there
1063  * is a chance for CDSA_L register overflow between the two reads resulting
1064  * in incorrect return value.
1065  */
1066 dma_addr_t omap_get_dma_dst_pos(int lch)
1067 {
1068         dma_addr_t offset = 0;
1069
1070         if (cpu_is_omap15xx())
1071                 offset = p->dma_read(CPC, lch);
1072         else
1073                 offset = p->dma_read(CDAC, lch);
1074
1075         /*
1076          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1077          * read before the DMA controller finished disabling the channel.
1078          */
1079         if (!cpu_is_omap15xx() && offset == 0) {
1080                 offset = p->dma_read(CDAC, lch);
1081                 /*
1082                  * CDAC == 0 indicates that the DMA transfer on the channel has
1083                  * not been started (no data has been transferred so far).
1084                  * Return the programmed destination start address in this case.
1085                  */
1086                 if (unlikely(!offset))
1087                         offset = p->dma_read(CDSA, lch);
1088         }
1089
1090         if (cpu_class_is_omap1())
1091                 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1092
1093         return offset;
1094 }
1095 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1096
1097 int omap_get_dma_active_status(int lch)
1098 {
1099         return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1100 }
1101 EXPORT_SYMBOL(omap_get_dma_active_status);
1102
1103 int omap_dma_running(void)
1104 {
1105         int lch;
1106
1107         if (cpu_class_is_omap1())
1108                 if (omap_lcd_dma_running())
1109                         return 1;
1110
1111         for (lch = 0; lch < dma_chan_count; lch++)
1112                 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1113                         return 1;
1114
1115         return 0;
1116 }
1117
1118 /*
1119  * lch_queue DMA will start right after lch_head one is finished.
1120  * For this DMA link to start, you still need to start (see omap_start_dma)
1121  * the first one. That will fire up the entire queue.
1122  */
1123 void omap_dma_link_lch(int lch_head, int lch_queue)
1124 {
1125         if (omap_dma_in_1510_mode()) {
1126                 if (lch_head == lch_queue) {
1127                         p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1128                                                                 CCR, lch_head);
1129                         return;
1130                 }
1131                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1132                 BUG();
1133                 return;
1134         }
1135
1136         if ((dma_chan[lch_head].dev_id == -1) ||
1137             (dma_chan[lch_queue].dev_id == -1)) {
1138                 printk(KERN_ERR "omap_dma: trying to link "
1139                        "non requested channels\n");
1140                 dump_stack();
1141         }
1142
1143         dma_chan[lch_head].next_lch = lch_queue;
1144 }
1145 EXPORT_SYMBOL(omap_dma_link_lch);
1146
1147 /*
1148  * Once the DMA queue is stopped, we can destroy it.
1149  */
1150 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1151 {
1152         if (omap_dma_in_1510_mode()) {
1153                 if (lch_head == lch_queue) {
1154                         p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1155                                                                 CCR, lch_head);
1156                         return;
1157                 }
1158                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1159                 BUG();
1160                 return;
1161         }
1162
1163         if (dma_chan[lch_head].next_lch != lch_queue ||
1164             dma_chan[lch_head].next_lch == -1) {
1165                 printk(KERN_ERR "omap_dma: trying to unlink "
1166                        "non linked channels\n");
1167                 dump_stack();
1168         }
1169
1170         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1171             (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1172                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1173                        "before unlinking\n");
1174                 dump_stack();
1175         }
1176
1177         dma_chan[lch_head].next_lch = -1;
1178 }
1179 EXPORT_SYMBOL(omap_dma_unlink_lch);
1180
1181 #ifndef CONFIG_ARCH_OMAP1
1182 /* Create chain of DMA channesls */
1183 static void create_dma_lch_chain(int lch_head, int lch_queue)
1184 {
1185         u32 l;
1186
1187         /* Check if this is the first link in chain */
1188         if (dma_chan[lch_head].next_linked_ch == -1) {
1189                 dma_chan[lch_head].next_linked_ch = lch_queue;
1190                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1191                 dma_chan[lch_queue].next_linked_ch = lch_head;
1192                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1193         }
1194
1195         /* a link exists, link the new channel in circular chain */
1196         else {
1197                 dma_chan[lch_queue].next_linked_ch =
1198                                         dma_chan[lch_head].next_linked_ch;
1199                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1200                 dma_chan[lch_head].next_linked_ch = lch_queue;
1201                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1202                                         lch_queue;
1203         }
1204
1205         l = p->dma_read(CLNK_CTRL, lch_head);
1206         l &= ~(0x1f);
1207         l |= lch_queue;
1208         p->dma_write(l, CLNK_CTRL, lch_head);
1209
1210         l = p->dma_read(CLNK_CTRL, lch_queue);
1211         l &= ~(0x1f);
1212         l |= (dma_chan[lch_queue].next_linked_ch);
1213         p->dma_write(l, CLNK_CTRL, lch_queue);
1214 }
1215
1216 /**
1217  * @brief omap_request_dma_chain : Request a chain of DMA channels
1218  *
1219  * @param dev_id - Device id using the dma channel
1220  * @param dev_name - Device name
1221  * @param callback - Call back function
1222  * @chain_id -
1223  * @no_of_chans - Number of channels requested
1224  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1225  *                                            OMAP_DMA_DYNAMIC_CHAIN
1226  * @params - Channel parameters
1227  *
1228  * @return - Success : 0
1229  *           Failure: -EINVAL/-ENOMEM
1230  */
1231 int omap_request_dma_chain(int dev_id, const char *dev_name,
1232                            void (*callback) (int lch, u16 ch_status,
1233                                              void *data),
1234                            int *chain_id, int no_of_chans, int chain_mode,
1235                            struct omap_dma_channel_params params)
1236 {
1237         int *channels;
1238         int i, err;
1239
1240         /* Is the chain mode valid ? */
1241         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1242                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1243                 printk(KERN_ERR "Invalid chain mode requested\n");
1244                 return -EINVAL;
1245         }
1246
1247         if (unlikely((no_of_chans < 1
1248                         || no_of_chans > dma_lch_count))) {
1249                 printk(KERN_ERR "Invalid Number of channels requested\n");
1250                 return -EINVAL;
1251         }
1252
1253         /*
1254          * Allocate a queue to maintain the status of the channels
1255          * in the chain
1256          */
1257         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1258         if (channels == NULL) {
1259                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1260                 return -ENOMEM;
1261         }
1262
1263         /* request and reserve DMA channels for the chain */
1264         for (i = 0; i < no_of_chans; i++) {
1265                 err = omap_request_dma(dev_id, dev_name,
1266                                         callback, NULL, &channels[i]);
1267                 if (err < 0) {
1268                         int j;
1269                         for (j = 0; j < i; j++)
1270                                 omap_free_dma(channels[j]);
1271                         kfree(channels);
1272                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1273                         return err;
1274                 }
1275                 dma_chan[channels[i]].prev_linked_ch = -1;
1276                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1277
1278                 /*
1279                  * Allowing client drivers to set common parameters now,
1280                  * so that later only relevant (src_start, dest_start
1281                  * and element count) can be set
1282                  */
1283                 omap_set_dma_params(channels[i], &params);
1284         }
1285
1286         *chain_id = channels[0];
1287         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1288         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1289         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1290         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1291
1292         for (i = 0; i < no_of_chans; i++)
1293                 dma_chan[channels[i]].chain_id = *chain_id;
1294
1295         /* Reset the Queue pointers */
1296         OMAP_DMA_CHAIN_QINIT(*chain_id);
1297
1298         /* Set up the chain */
1299         if (no_of_chans == 1)
1300                 create_dma_lch_chain(channels[0], channels[0]);
1301         else {
1302                 for (i = 0; i < (no_of_chans - 1); i++)
1303                         create_dma_lch_chain(channels[i], channels[i + 1]);
1304         }
1305
1306         return 0;
1307 }
1308 EXPORT_SYMBOL(omap_request_dma_chain);
1309
1310 /**
1311  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1312  * params after setting it. Dont do this while dma is running!!
1313  *
1314  * @param chain_id - Chained logical channel id.
1315  * @param params
1316  *
1317  * @return - Success : 0
1318  *           Failure : -EINVAL
1319  */
1320 int omap_modify_dma_chain_params(int chain_id,
1321                                 struct omap_dma_channel_params params)
1322 {
1323         int *channels;
1324         u32 i;
1325
1326         /* Check for input params */
1327         if (unlikely((chain_id < 0
1328                         || chain_id >= dma_lch_count))) {
1329                 printk(KERN_ERR "Invalid chain id\n");
1330                 return -EINVAL;
1331         }
1332
1333         /* Check if the chain exists */
1334         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1335                 printk(KERN_ERR "Chain doesn't exists\n");
1336                 return -EINVAL;
1337         }
1338         channels = dma_linked_lch[chain_id].linked_dmach_q;
1339
1340         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1341                 /*
1342                  * Allowing client drivers to set common parameters now,
1343                  * so that later only relevant (src_start, dest_start
1344                  * and element count) can be set
1345                  */
1346                 omap_set_dma_params(channels[i], &params);
1347         }
1348
1349         return 0;
1350 }
1351 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1352
1353 /**
1354  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1355  *
1356  * @param chain_id
1357  *
1358  * @return - Success : 0
1359  *           Failure : -EINVAL
1360  */
1361 int omap_free_dma_chain(int chain_id)
1362 {
1363         int *channels;
1364         u32 i;
1365
1366         /* Check for input params */
1367         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1368                 printk(KERN_ERR "Invalid chain id\n");
1369                 return -EINVAL;
1370         }
1371
1372         /* Check if the chain exists */
1373         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1374                 printk(KERN_ERR "Chain doesn't exists\n");
1375                 return -EINVAL;
1376         }
1377
1378         channels = dma_linked_lch[chain_id].linked_dmach_q;
1379         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1380                 dma_chan[channels[i]].next_linked_ch = -1;
1381                 dma_chan[channels[i]].prev_linked_ch = -1;
1382                 dma_chan[channels[i]].chain_id = -1;
1383                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1384                 omap_free_dma(channels[i]);
1385         }
1386
1387         kfree(channels);
1388
1389         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1390         dma_linked_lch[chain_id].chain_mode = -1;
1391         dma_linked_lch[chain_id].chain_state = -1;
1392
1393         return (0);
1394 }
1395 EXPORT_SYMBOL(omap_free_dma_chain);
1396
1397 /**
1398  * @brief omap_dma_chain_status - Check if the chain is in
1399  * active / inactive state.
1400  * @param chain_id
1401  *
1402  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1403  *           Failure : -EINVAL
1404  */
1405 int omap_dma_chain_status(int chain_id)
1406 {
1407         /* Check for input params */
1408         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1409                 printk(KERN_ERR "Invalid chain id\n");
1410                 return -EINVAL;
1411         }
1412
1413         /* Check if the chain exists */
1414         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1415                 printk(KERN_ERR "Chain doesn't exists\n");
1416                 return -EINVAL;
1417         }
1418         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1419                         dma_linked_lch[chain_id].q_count);
1420
1421         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1422                 return OMAP_DMA_CHAIN_INACTIVE;
1423
1424         return OMAP_DMA_CHAIN_ACTIVE;
1425 }
1426 EXPORT_SYMBOL(omap_dma_chain_status);
1427
1428 /**
1429  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1430  * set the params and start the transfer.
1431  *
1432  * @param chain_id
1433  * @param src_start - buffer start address
1434  * @param dest_start - Dest address
1435  * @param elem_count
1436  * @param frame_count
1437  * @param callbk_data - channel callback parameter data.
1438  *
1439  * @return  - Success : 0
1440  *            Failure: -EINVAL/-EBUSY
1441  */
1442 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1443                         int elem_count, int frame_count, void *callbk_data)
1444 {
1445         int *channels;
1446         u32 l, lch;
1447         int start_dma = 0;
1448
1449         /*
1450          * if buffer size is less than 1 then there is
1451          * no use of starting the chain
1452          */
1453         if (elem_count < 1) {
1454                 printk(KERN_ERR "Invalid buffer size\n");
1455                 return -EINVAL;
1456         }
1457
1458         /* Check for input params */
1459         if (unlikely((chain_id < 0
1460                         || chain_id >= dma_lch_count))) {
1461                 printk(KERN_ERR "Invalid chain id\n");
1462                 return -EINVAL;
1463         }
1464
1465         /* Check if the chain exists */
1466         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1467                 printk(KERN_ERR "Chain doesn't exist\n");
1468                 return -EINVAL;
1469         }
1470
1471         /* Check if all the channels in chain are in use */
1472         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1473                 return -EBUSY;
1474
1475         /* Frame count may be negative in case of indexed transfers */
1476         channels = dma_linked_lch[chain_id].linked_dmach_q;
1477
1478         /* Get a free channel */
1479         lch = channels[dma_linked_lch[chain_id].q_tail];
1480
1481         /* Store the callback data */
1482         dma_chan[lch].data = callbk_data;
1483
1484         /* Increment the q_tail */
1485         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1486
1487         /* Set the params to the free channel */
1488         if (src_start != 0)
1489                 p->dma_write(src_start, CSSA, lch);
1490         if (dest_start != 0)
1491                 p->dma_write(dest_start, CDSA, lch);
1492
1493         /* Write the buffer size */
1494         p->dma_write(elem_count, CEN, lch);
1495         p->dma_write(frame_count, CFN, lch);
1496
1497         /*
1498          * If the chain is dynamically linked,
1499          * then we may have to start the chain if its not active
1500          */
1501         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1502
1503                 /*
1504                  * In Dynamic chain, if the chain is not started,
1505                  * queue the channel
1506                  */
1507                 if (dma_linked_lch[chain_id].chain_state ==
1508                                                 DMA_CHAIN_NOTSTARTED) {
1509                         /* Enable the link in previous channel */
1510                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1511                                                                 DMA_CH_QUEUED)
1512                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1513                         dma_chan[lch].state = DMA_CH_QUEUED;
1514                 }
1515
1516                 /*
1517                  * Chain is already started, make sure its active,
1518                  * if not then start the chain
1519                  */
1520                 else {
1521                         start_dma = 1;
1522
1523                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1524                                                         DMA_CH_STARTED) {
1525                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1526                                 dma_chan[lch].state = DMA_CH_QUEUED;
1527                                 start_dma = 0;
1528                                 if (0 == ((1 << 7) & p->dma_read(
1529                                         CCR, dma_chan[lch].prev_linked_ch))) {
1530                                         disable_lnk(dma_chan[lch].
1531                                                     prev_linked_ch);
1532                                         pr_debug("\n prev ch is stopped\n");
1533                                         start_dma = 1;
1534                                 }
1535                         }
1536
1537                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1538                                                         == DMA_CH_QUEUED) {
1539                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1540                                 dma_chan[lch].state = DMA_CH_QUEUED;
1541                                 start_dma = 0;
1542                         }
1543                         omap_enable_channel_irq(lch);
1544
1545                         l = p->dma_read(CCR, lch);
1546
1547                         if ((0 == (l & (1 << 24))))
1548                                 l &= ~(1 << 25);
1549                         else
1550                                 l |= (1 << 25);
1551                         if (start_dma == 1) {
1552                                 if (0 == (l & (1 << 7))) {
1553                                         l |= (1 << 7);
1554                                         dma_chan[lch].state = DMA_CH_STARTED;
1555                                         pr_debug("starting %d\n", lch);
1556                                         p->dma_write(l, CCR, lch);
1557                                 } else
1558                                         start_dma = 0;
1559                         } else {
1560                                 if (0 == (l & (1 << 7)))
1561                                         p->dma_write(l, CCR, lch);
1562                         }
1563                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1564                 }
1565         }
1566
1567         return 0;
1568 }
1569 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1570
1571 /**
1572  * @brief omap_start_dma_chain_transfers - Start the chain
1573  *
1574  * @param chain_id
1575  *
1576  * @return - Success : 0
1577  *           Failure : -EINVAL/-EBUSY
1578  */
1579 int omap_start_dma_chain_transfers(int chain_id)
1580 {
1581         int *channels;
1582         u32 l, i;
1583
1584         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1585                 printk(KERN_ERR "Invalid chain id\n");
1586                 return -EINVAL;
1587         }
1588
1589         channels = dma_linked_lch[chain_id].linked_dmach_q;
1590
1591         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1592                 printk(KERN_ERR "Chain is already started\n");
1593                 return -EBUSY;
1594         }
1595
1596         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1597                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1598                                                                         i++) {
1599                         enable_lnk(channels[i]);
1600                         omap_enable_channel_irq(channels[i]);
1601                 }
1602         } else {
1603                 omap_enable_channel_irq(channels[0]);
1604         }
1605
1606         l = p->dma_read(CCR, channels[0]);
1607         l |= (1 << 7);
1608         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1609         dma_chan[channels[0]].state = DMA_CH_STARTED;
1610
1611         if ((0 == (l & (1 << 24))))
1612                 l &= ~(1 << 25);
1613         else
1614                 l |= (1 << 25);
1615         p->dma_write(l, CCR, channels[0]);
1616
1617         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1618
1619         return 0;
1620 }
1621 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1622
1623 /**
1624  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1625  *
1626  * @param chain_id
1627  *
1628  * @return - Success : 0
1629  *           Failure : EINVAL
1630  */
1631 int omap_stop_dma_chain_transfers(int chain_id)
1632 {
1633         int *channels;
1634         u32 l, i;
1635         u32 sys_cf = 0;
1636
1637         /* Check for input params */
1638         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1639                 printk(KERN_ERR "Invalid chain id\n");
1640                 return -EINVAL;
1641         }
1642
1643         /* Check if the chain exists */
1644         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1645                 printk(KERN_ERR "Chain doesn't exists\n");
1646                 return -EINVAL;
1647         }
1648         channels = dma_linked_lch[chain_id].linked_dmach_q;
1649
1650         if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1651                 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1652                 l = sys_cf;
1653                 /* Middle mode reg set no Standby */
1654                 l &= ~((1 << 12)|(1 << 13));
1655                 p->dma_write(l, OCP_SYSCONFIG, 0);
1656         }
1657
1658         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1659
1660                 /* Stop the Channel transmission */
1661                 l = p->dma_read(CCR, channels[i]);
1662                 l &= ~(1 << 7);
1663                 p->dma_write(l, CCR, channels[i]);
1664
1665                 /* Disable the link in all the channels */
1666                 disable_lnk(channels[i]);
1667                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1668
1669         }
1670         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1671
1672         /* Reset the Queue pointers */
1673         OMAP_DMA_CHAIN_QINIT(chain_id);
1674
1675         if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1676                 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1677
1678         return 0;
1679 }
1680 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1681
1682 /* Get the index of the ongoing DMA in chain */
1683 /**
1684  * @brief omap_get_dma_chain_index - Get the element and frame index
1685  * of the ongoing DMA in chain
1686  *
1687  * @param chain_id
1688  * @param ei - Element index
1689  * @param fi - Frame index
1690  *
1691  * @return - Success : 0
1692  *           Failure : -EINVAL
1693  */
1694 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1695 {
1696         int lch;
1697         int *channels;
1698
1699         /* Check for input params */
1700         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1701                 printk(KERN_ERR "Invalid chain id\n");
1702                 return -EINVAL;
1703         }
1704
1705         /* Check if the chain exists */
1706         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1707                 printk(KERN_ERR "Chain doesn't exists\n");
1708                 return -EINVAL;
1709         }
1710         if ((!ei) || (!fi))
1711                 return -EINVAL;
1712
1713         channels = dma_linked_lch[chain_id].linked_dmach_q;
1714
1715         /* Get the current channel */
1716         lch = channels[dma_linked_lch[chain_id].q_head];
1717
1718         *ei = p->dma_read(CCEN, lch);
1719         *fi = p->dma_read(CCFN, lch);
1720
1721         return 0;
1722 }
1723 EXPORT_SYMBOL(omap_get_dma_chain_index);
1724
1725 /**
1726  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1727  * ongoing DMA in chain
1728  *
1729  * @param chain_id
1730  *
1731  * @return - Success : Destination position
1732  *           Failure : -EINVAL
1733  */
1734 int omap_get_dma_chain_dst_pos(int chain_id)
1735 {
1736         int lch;
1737         int *channels;
1738
1739         /* Check for input params */
1740         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1741                 printk(KERN_ERR "Invalid chain id\n");
1742                 return -EINVAL;
1743         }
1744
1745         /* Check if the chain exists */
1746         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1747                 printk(KERN_ERR "Chain doesn't exists\n");
1748                 return -EINVAL;
1749         }
1750
1751         channels = dma_linked_lch[chain_id].linked_dmach_q;
1752
1753         /* Get the current channel */
1754         lch = channels[dma_linked_lch[chain_id].q_head];
1755
1756         return p->dma_read(CDAC, lch);
1757 }
1758 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1759
1760 /**
1761  * @brief omap_get_dma_chain_src_pos - Get the source position
1762  * of the ongoing DMA in chain
1763  * @param chain_id
1764  *
1765  * @return - Success : Destination position
1766  *           Failure : -EINVAL
1767  */
1768 int omap_get_dma_chain_src_pos(int chain_id)
1769 {
1770         int lch;
1771         int *channels;
1772
1773         /* Check for input params */
1774         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1775                 printk(KERN_ERR "Invalid chain id\n");
1776                 return -EINVAL;
1777         }
1778
1779         /* Check if the chain exists */
1780         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1781                 printk(KERN_ERR "Chain doesn't exists\n");
1782                 return -EINVAL;
1783         }
1784
1785         channels = dma_linked_lch[chain_id].linked_dmach_q;
1786
1787         /* Get the current channel */
1788         lch = channels[dma_linked_lch[chain_id].q_head];
1789
1790         return p->dma_read(CSAC, lch);
1791 }
1792 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1793 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1794
1795 /*----------------------------------------------------------------------------*/
1796
1797 #ifdef CONFIG_ARCH_OMAP1
1798
1799 static int omap1_dma_handle_ch(int ch)
1800 {
1801         u32 csr;
1802
1803         if (enable_1510_mode && ch >= 6) {
1804                 csr = dma_chan[ch].saved_csr;
1805                 dma_chan[ch].saved_csr = 0;
1806         } else
1807                 csr = p->dma_read(CSR, ch);
1808         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1809                 dma_chan[ch + 6].saved_csr = csr >> 7;
1810                 csr &= 0x7f;
1811         }
1812         if ((csr & 0x3f) == 0)
1813                 return 0;
1814         if (unlikely(dma_chan[ch].dev_id == -1)) {
1815                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1816                        "%d (CSR %04x)\n", ch, csr);
1817                 return 0;
1818         }
1819         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1820                 printk(KERN_WARNING "DMA timeout with device %d\n",
1821                        dma_chan[ch].dev_id);
1822         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1823                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1824                        "with device %d\n", dma_chan[ch].dev_id);
1825         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1826                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1827         if (likely(dma_chan[ch].callback != NULL))
1828                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1829
1830         return 1;
1831 }
1832
1833 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1834 {
1835         int ch = ((int) dev_id) - 1;
1836         int handled = 0;
1837
1838         for (;;) {
1839                 int handled_now = 0;
1840
1841                 handled_now += omap1_dma_handle_ch(ch);
1842                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1843                         handled_now += omap1_dma_handle_ch(ch + 6);
1844                 if (!handled_now)
1845                         break;
1846                 handled += handled_now;
1847         }
1848
1849         return handled ? IRQ_HANDLED : IRQ_NONE;
1850 }
1851
1852 #else
1853 #define omap1_dma_irq_handler   NULL
1854 #endif
1855
1856 #ifdef CONFIG_ARCH_OMAP2PLUS
1857
1858 static int omap2_dma_handle_ch(int ch)
1859 {
1860         u32 status = p->dma_read(CSR, ch);
1861
1862         if (!status) {
1863                 if (printk_ratelimit())
1864                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1865                                 ch);
1866                 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1867                 return 0;
1868         }
1869         if (unlikely(dma_chan[ch].dev_id == -1)) {
1870                 if (printk_ratelimit())
1871                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1872                                         "channel %d\n", status, ch);
1873                 return 0;
1874         }
1875         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1876                 printk(KERN_INFO
1877                        "DMA synchronization event drop occurred with device "
1878                        "%d\n", dma_chan[ch].dev_id);
1879         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1880                 printk(KERN_INFO "DMA transaction error with device %d\n",
1881                        dma_chan[ch].dev_id);
1882                 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1883                         u32 ccr;
1884
1885                         ccr = p->dma_read(CCR, ch);
1886                         ccr &= ~OMAP_DMA_CCR_EN;
1887                         p->dma_write(ccr, CCR, ch);
1888                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1889                 }
1890         }
1891         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1892                 printk(KERN_INFO "DMA secure error with device %d\n",
1893                        dma_chan[ch].dev_id);
1894         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1895                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1896                        dma_chan[ch].dev_id);
1897
1898         p->dma_write(status, CSR, ch);
1899         p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1900         /* read back the register to flush the write */
1901         p->dma_read(IRQSTATUS_L0, ch);
1902
1903         /* If the ch is not chained then chain_id will be -1 */
1904         if (dma_chan[ch].chain_id != -1) {
1905                 int chain_id = dma_chan[ch].chain_id;
1906                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1907                 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1908                         dma_chan[dma_chan[ch].next_linked_ch].state =
1909                                                         DMA_CH_STARTED;
1910                 if (dma_linked_lch[chain_id].chain_mode ==
1911                                                 OMAP_DMA_DYNAMIC_CHAIN)
1912                         disable_lnk(ch);
1913
1914                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1915                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1916
1917                 status = p->dma_read(CSR, ch);
1918                 p->dma_write(status, CSR, ch);
1919         }
1920
1921         if (likely(dma_chan[ch].callback != NULL))
1922                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1923
1924         return 0;
1925 }
1926
1927 /* STATUS register count is from 1-32 while our is 0-31 */
1928 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1929 {
1930         u32 val, enable_reg;
1931         int i;
1932
1933         val = p->dma_read(IRQSTATUS_L0, 0);
1934         if (val == 0) {
1935                 if (printk_ratelimit())
1936                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1937                 return IRQ_HANDLED;
1938         }
1939         enable_reg = p->dma_read(IRQENABLE_L0, 0);
1940         val &= enable_reg; /* Dispatch only relevant interrupts */
1941         for (i = 0; i < dma_lch_count && val != 0; i++) {
1942                 if (val & 1)
1943                         omap2_dma_handle_ch(i);
1944                 val >>= 1;
1945         }
1946
1947         return IRQ_HANDLED;
1948 }
1949
1950 static struct irqaction omap24xx_dma_irq = {
1951         .name = "DMA",
1952         .handler = omap2_dma_irq_handler,
1953         .flags = IRQF_DISABLED
1954 };
1955
1956 #else
1957 static struct irqaction omap24xx_dma_irq;
1958 #endif
1959
1960 /*----------------------------------------------------------------------------*/
1961
1962 void omap_dma_global_context_save(void)
1963 {
1964         omap_dma_global_context.dma_irqenable_l0 =
1965                 p->dma_read(IRQENABLE_L0, 0);
1966         omap_dma_global_context.dma_ocp_sysconfig =
1967                 p->dma_read(OCP_SYSCONFIG, 0);
1968         omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1969 }
1970
1971 void omap_dma_global_context_restore(void)
1972 {
1973         int ch;
1974
1975         p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1976         p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1977                 OCP_SYSCONFIG, 0);
1978         p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1979                 IRQENABLE_L0, 0);
1980
1981         if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1982                 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1983
1984         for (ch = 0; ch < dma_chan_count; ch++)
1985                 if (dma_chan[ch].dev_id != -1)
1986                         omap_clear_dma(ch);
1987 }
1988
1989 static int __devinit omap_system_dma_probe(struct platform_device *pdev)
1990 {
1991         int ch, ret = 0;
1992         int dma_irq;
1993         char irq_name[4];
1994         int irq_rel;
1995
1996         p = pdev->dev.platform_data;
1997         if (!p) {
1998                 dev_err(&pdev->dev, "%s: System DMA initialized without"
1999                         "platform data\n", __func__);
2000                 return -EINVAL;
2001         }
2002
2003         d                       = p->dma_attr;
2004         errata                  = p->errata;
2005
2006         if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
2007                         && (omap_dma_reserve_channels <= dma_lch_count))
2008                 d->lch_count    = omap_dma_reserve_channels;
2009
2010         dma_lch_count           = d->lch_count;
2011         dma_chan_count          = dma_lch_count;
2012         dma_chan                = d->chan;
2013         enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
2014
2015         if (cpu_class_is_omap2()) {
2016                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2017                                                 dma_lch_count, GFP_KERNEL);
2018                 if (!dma_linked_lch) {
2019                         ret = -ENOMEM;
2020                         goto exit_dma_lch_fail;
2021                 }
2022         }
2023
2024         spin_lock_init(&dma_chan_lock);
2025         for (ch = 0; ch < dma_chan_count; ch++) {
2026                 omap_clear_dma(ch);
2027                 if (cpu_class_is_omap2())
2028                         omap2_disable_irq_lch(ch);
2029
2030                 dma_chan[ch].dev_id = -1;
2031                 dma_chan[ch].next_lch = -1;
2032
2033                 if (ch >= 6 && enable_1510_mode)
2034                         continue;
2035
2036                 if (cpu_class_is_omap1()) {
2037                         /*
2038                          * request_irq() doesn't like dev_id (ie. ch) being
2039                          * zero, so we have to kludge around this.
2040                          */
2041                         sprintf(&irq_name[0], "%d", ch);
2042                         dma_irq = platform_get_irq_byname(pdev, irq_name);
2043
2044                         if (dma_irq < 0) {
2045                                 ret = dma_irq;
2046                                 goto exit_dma_irq_fail;
2047                         }
2048
2049                         /* INT_DMA_LCD is handled in lcd_dma.c */
2050                         if (dma_irq == INT_DMA_LCD)
2051                                 continue;
2052
2053                         ret = request_irq(dma_irq,
2054                                         omap1_dma_irq_handler, 0, "DMA",
2055                                         (void *) (ch + 1));
2056                         if (ret != 0)
2057                                 goto exit_dma_irq_fail;
2058                 }
2059         }
2060
2061         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2062                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2063                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2064
2065         if (cpu_class_is_omap2()) {
2066                 strcpy(irq_name, "0");
2067                 dma_irq = platform_get_irq_byname(pdev, irq_name);
2068                 if (dma_irq < 0) {
2069                         dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2070                         goto exit_dma_lch_fail;
2071                 }
2072                 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2073                 if (ret) {
2074                         dev_err(&pdev->dev, "set_up failed for IRQ %d"
2075                                 "for DMA (error %d)\n", dma_irq, ret);
2076                         goto exit_dma_lch_fail;
2077                 }
2078         }
2079
2080         /* reserve dma channels 0 and 1 in high security devices */
2081         if (cpu_is_omap34xx() &&
2082                 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2083                 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2084                                 "HS ROM code\n");
2085                 dma_chan[0].dev_id = 0;
2086                 dma_chan[1].dev_id = 1;
2087         }
2088         p->show_dma_caps();
2089         return 0;
2090
2091 exit_dma_irq_fail:
2092         dev_err(&pdev->dev, "unable to request IRQ %d"
2093                         "for DMA (error %d)\n", dma_irq, ret);
2094         for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2095                 dma_irq = platform_get_irq(pdev, irq_rel);
2096                 free_irq(dma_irq, (void *)(irq_rel + 1));
2097         }
2098
2099 exit_dma_lch_fail:
2100         kfree(p);
2101         kfree(d);
2102         kfree(dma_chan);
2103         return ret;
2104 }
2105
2106 static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2107 {
2108         int dma_irq;
2109
2110         if (cpu_class_is_omap2()) {
2111                 char irq_name[4];
2112                 strcpy(irq_name, "0");
2113                 dma_irq = platform_get_irq_byname(pdev, irq_name);
2114                 remove_irq(dma_irq, &omap24xx_dma_irq);
2115         } else {
2116                 int irq_rel = 0;
2117                 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2118                         dma_irq = platform_get_irq(pdev, irq_rel);
2119                         free_irq(dma_irq, (void *)(irq_rel + 1));
2120                 }
2121         }
2122         kfree(p);
2123         kfree(d);
2124         kfree(dma_chan);
2125         return 0;
2126 }
2127
2128 static struct platform_driver omap_system_dma_driver = {
2129         .probe          = omap_system_dma_probe,
2130         .remove         = __devexit_p(omap_system_dma_remove),
2131         .driver         = {
2132                 .name   = "omap_dma_system"
2133         },
2134 };
2135
2136 static int __init omap_system_dma_init(void)
2137 {
2138         return platform_driver_register(&omap_system_dma_driver);
2139 }
2140 arch_initcall(omap_system_dma_init);
2141
2142 static void __exit omap_system_dma_exit(void)
2143 {
2144         platform_driver_unregister(&omap_system_dma_driver);
2145 }
2146
2147 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2148 MODULE_LICENSE("GPL");
2149 MODULE_ALIAS("platform:" DRIVER_NAME);
2150 MODULE_AUTHOR("Texas Instruments Inc");
2151
2152 /*
2153  * Reserve the omap SDMA channels using cmdline bootarg
2154  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2155  */
2156 static int __init omap_dma_cmdline_reserve_ch(char *str)
2157 {
2158         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2159                 omap_dma_reserve_channels = 0;
2160         return 1;
2161 }
2162
2163 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2164
2165