2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Support functions for the OMAP internal DMA channels.
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <mach/hardware.h>
46 #ifndef CONFIG_ARCH_OMAP1
47 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
48 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
51 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
54 #define OMAP_DMA_ACTIVE 0x01
55 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
57 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
59 static struct omap_system_dma_plat_info *p;
60 static struct omap_dma_dev_attr *d;
62 static int enable_1510_mode;
65 static struct omap_dma_global_context_registers {
67 u32 dma_ocp_sysconfig;
69 } omap_dma_global_context;
71 struct dma_link_info {
73 int no_of_lchs_linked;
84 static struct dma_link_info *dma_linked_lch;
86 #ifndef CONFIG_ARCH_OMAP1
88 /* Chain handling macros */
89 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
91 dma_linked_lch[chain_id].q_head = \
92 dma_linked_lch[chain_id].q_tail = \
93 dma_linked_lch[chain_id].q_count = 0; \
95 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
96 (dma_linked_lch[chain_id].no_of_lchs_linked == \
97 dma_linked_lch[chain_id].q_count)
98 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
100 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
101 dma_linked_lch[chain_id].q_count) \
103 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
104 (0 == dma_linked_lch[chain_id].q_count)
105 #define __OMAP_DMA_CHAIN_INCQ(end) \
106 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
107 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
109 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
110 dma_linked_lch[chain_id].q_count--; \
113 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
115 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
116 dma_linked_lch[chain_id].q_count++; \
120 static int dma_lch_count;
121 static int dma_chan_count;
122 static int omap_dma_reserve_channels;
124 static spinlock_t dma_chan_lock;
125 static struct omap_dma_lch *dma_chan;
127 static inline void disable_lnk(int lch);
128 static void omap_disable_channel_irq(int lch);
129 static inline void omap_enable_channel_irq(int lch);
131 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
134 #ifdef CONFIG_ARCH_OMAP15XX
135 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
136 static int omap_dma_in_1510_mode(void)
138 return enable_1510_mode;
141 #define omap_dma_in_1510_mode() 0
144 #ifdef CONFIG_ARCH_OMAP1
145 static inline int get_gdma_dev(int req)
147 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
148 int shift = ((req - 1) % 5) * 6;
150 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
153 static inline void set_gdma_dev(int req, int dev)
155 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
156 int shift = ((req - 1) % 5) * 6;
160 l &= ~(0x3f << shift);
161 l |= (dev - 1) << shift;
165 #define set_gdma_dev(req, dev) do {} while (0)
166 #define omap_readl(reg) 0
167 #define omap_writel(val, reg) do {} while (0)
170 void omap_set_dma_priority(int lch, int dst_port, int priority)
175 if (cpu_class_is_omap1()) {
177 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
178 reg = OMAP_TC_OCPT1_PRIOR;
180 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
181 reg = OMAP_TC_OCPT2_PRIOR;
183 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
184 reg = OMAP_TC_EMIFF_PRIOR;
186 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
187 reg = OMAP_TC_EMIFS_PRIOR;
195 l |= (priority & 0xf) << 8;
199 if (cpu_class_is_omap2()) {
202 ccr = p->dma_read(CCR, lch);
207 p->dma_write(ccr, CCR, lch);
210 EXPORT_SYMBOL(omap_set_dma_priority);
212 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
213 int frame_count, int sync_mode,
214 int dma_trigger, int src_or_dst_synch)
218 l = p->dma_read(CSDP, lch);
221 p->dma_write(l, CSDP, lch);
223 if (cpu_class_is_omap1()) {
226 ccr = p->dma_read(CCR, lch);
228 if (sync_mode == OMAP_DMA_SYNC_FRAME)
230 p->dma_write(ccr, CCR, lch);
232 ccr = p->dma_read(CCR2, lch);
234 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
236 p->dma_write(ccr, CCR2, lch);
239 if (cpu_class_is_omap2() && dma_trigger) {
242 val = p->dma_read(CCR, lch);
244 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
245 val &= ~((1 << 23) | (3 << 19) | 0x1f);
246 val |= (dma_trigger & ~0x1f) << 14;
247 val |= dma_trigger & 0x1f;
249 if (sync_mode & OMAP_DMA_SYNC_FRAME)
254 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
259 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
260 val &= ~(1 << 24); /* dest synch */
261 val |= (1 << 23); /* Prefetch */
262 } else if (src_or_dst_synch) {
263 val |= 1 << 24; /* source synch */
265 val &= ~(1 << 24); /* dest synch */
267 p->dma_write(val, CCR, lch);
270 p->dma_write(elem_count, CEN, lch);
271 p->dma_write(frame_count, CFN, lch);
273 EXPORT_SYMBOL(omap_set_dma_transfer_params);
275 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
277 BUG_ON(omap_dma_in_1510_mode());
279 if (cpu_class_is_omap1()) {
282 w = p->dma_read(CCR2, lch);
286 case OMAP_DMA_CONSTANT_FILL:
289 case OMAP_DMA_TRANSPARENT_COPY:
292 case OMAP_DMA_COLOR_DIS:
297 p->dma_write(w, CCR2, lch);
299 w = p->dma_read(LCH_CTRL, lch);
301 /* Default is channel type 2D */
303 p->dma_write(color, COLOR, lch);
304 w |= 1; /* Channel type G */
306 p->dma_write(w, LCH_CTRL, lch);
309 if (cpu_class_is_omap2()) {
312 val = p->dma_read(CCR, lch);
313 val &= ~((1 << 17) | (1 << 16));
316 case OMAP_DMA_CONSTANT_FILL:
319 case OMAP_DMA_TRANSPARENT_COPY:
322 case OMAP_DMA_COLOR_DIS:
327 p->dma_write(val, CCR, lch);
330 p->dma_write(color, COLOR, lch);
333 EXPORT_SYMBOL(omap_set_dma_color_mode);
335 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
337 if (cpu_class_is_omap2()) {
340 csdp = p->dma_read(CSDP, lch);
341 csdp &= ~(0x3 << 16);
342 csdp |= (mode << 16);
343 p->dma_write(csdp, CSDP, lch);
346 EXPORT_SYMBOL(omap_set_dma_write_mode);
348 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
350 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
353 l = p->dma_read(LCH_CTRL, lch);
356 p->dma_write(l, LCH_CTRL, lch);
359 EXPORT_SYMBOL(omap_set_dma_channel_mode);
361 /* Note that src_port is only for omap1 */
362 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
363 unsigned long src_start,
364 int src_ei, int src_fi)
368 if (cpu_class_is_omap1()) {
371 w = p->dma_read(CSDP, lch);
374 p->dma_write(w, CSDP, lch);
377 l = p->dma_read(CCR, lch);
379 l |= src_amode << 12;
380 p->dma_write(l, CCR, lch);
382 p->dma_write(src_start, CSSA, lch);
384 p->dma_write(src_ei, CSEI, lch);
385 p->dma_write(src_fi, CSFI, lch);
387 EXPORT_SYMBOL(omap_set_dma_src_params);
389 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
391 omap_set_dma_transfer_params(lch, params->data_type,
392 params->elem_count, params->frame_count,
393 params->sync_mode, params->trigger,
394 params->src_or_dst_synch);
395 omap_set_dma_src_params(lch, params->src_port,
396 params->src_amode, params->src_start,
397 params->src_ei, params->src_fi);
399 omap_set_dma_dest_params(lch, params->dst_port,
400 params->dst_amode, params->dst_start,
401 params->dst_ei, params->dst_fi);
402 if (params->read_prio || params->write_prio)
403 omap_dma_set_prio_lch(lch, params->read_prio,
406 EXPORT_SYMBOL(omap_set_dma_params);
408 void omap_set_dma_src_index(int lch, int eidx, int fidx)
410 if (cpu_class_is_omap2())
413 p->dma_write(eidx, CSEI, lch);
414 p->dma_write(fidx, CSFI, lch);
416 EXPORT_SYMBOL(omap_set_dma_src_index);
418 void omap_set_dma_src_data_pack(int lch, int enable)
422 l = p->dma_read(CSDP, lch);
426 p->dma_write(l, CSDP, lch);
428 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
430 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
432 unsigned int burst = 0;
435 l = p->dma_read(CSDP, lch);
438 switch (burst_mode) {
439 case OMAP_DMA_DATA_BURST_DIS:
441 case OMAP_DMA_DATA_BURST_4:
442 if (cpu_class_is_omap2())
447 case OMAP_DMA_DATA_BURST_8:
448 if (cpu_class_is_omap2()) {
453 * not supported by current hardware on OMAP1
457 case OMAP_DMA_DATA_BURST_16:
458 if (cpu_class_is_omap2()) {
463 * OMAP1 don't support burst 16
471 p->dma_write(l, CSDP, lch);
473 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
475 /* Note that dest_port is only for OMAP1 */
476 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
477 unsigned long dest_start,
478 int dst_ei, int dst_fi)
482 if (cpu_class_is_omap1()) {
483 l = p->dma_read(CSDP, lch);
486 p->dma_write(l, CSDP, lch);
489 l = p->dma_read(CCR, lch);
491 l |= dest_amode << 14;
492 p->dma_write(l, CCR, lch);
494 p->dma_write(dest_start, CDSA, lch);
496 p->dma_write(dst_ei, CDEI, lch);
497 p->dma_write(dst_fi, CDFI, lch);
499 EXPORT_SYMBOL(omap_set_dma_dest_params);
501 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
503 if (cpu_class_is_omap2())
506 p->dma_write(eidx, CDEI, lch);
507 p->dma_write(fidx, CDFI, lch);
509 EXPORT_SYMBOL(omap_set_dma_dest_index);
511 void omap_set_dma_dest_data_pack(int lch, int enable)
515 l = p->dma_read(CSDP, lch);
519 p->dma_write(l, CSDP, lch);
521 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
523 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
525 unsigned int burst = 0;
528 l = p->dma_read(CSDP, lch);
531 switch (burst_mode) {
532 case OMAP_DMA_DATA_BURST_DIS:
534 case OMAP_DMA_DATA_BURST_4:
535 if (cpu_class_is_omap2())
540 case OMAP_DMA_DATA_BURST_8:
541 if (cpu_class_is_omap2())
546 case OMAP_DMA_DATA_BURST_16:
547 if (cpu_class_is_omap2()) {
552 * OMAP1 don't support burst 16
556 printk(KERN_ERR "Invalid DMA burst mode\n");
561 p->dma_write(l, CSDP, lch);
563 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
565 static inline void omap_enable_channel_irq(int lch)
570 if (cpu_class_is_omap1())
571 status = p->dma_read(CSR, lch);
572 else if (cpu_class_is_omap2())
573 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
575 /* Enable some nice interrupts. */
576 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
579 static void omap_disable_channel_irq(int lch)
581 if (cpu_class_is_omap2())
582 p->dma_write(0, CICR, lch);
585 void omap_enable_dma_irq(int lch, u16 bits)
587 dma_chan[lch].enabled_irqs |= bits;
589 EXPORT_SYMBOL(omap_enable_dma_irq);
591 void omap_disable_dma_irq(int lch, u16 bits)
593 dma_chan[lch].enabled_irqs &= ~bits;
595 EXPORT_SYMBOL(omap_disable_dma_irq);
597 static inline void enable_lnk(int lch)
601 l = p->dma_read(CLNK_CTRL, lch);
603 if (cpu_class_is_omap1())
606 /* Set the ENABLE_LNK bits */
607 if (dma_chan[lch].next_lch != -1)
608 l = dma_chan[lch].next_lch | (1 << 15);
610 #ifndef CONFIG_ARCH_OMAP1
611 if (cpu_class_is_omap2())
612 if (dma_chan[lch].next_linked_ch != -1)
613 l = dma_chan[lch].next_linked_ch | (1 << 15);
616 p->dma_write(l, CLNK_CTRL, lch);
619 static inline void disable_lnk(int lch)
623 l = p->dma_read(CLNK_CTRL, lch);
625 /* Disable interrupts */
626 if (cpu_class_is_omap1()) {
627 p->dma_write(0, CICR, lch);
628 /* Set the STOP_LNK bit */
632 if (cpu_class_is_omap2()) {
633 omap_disable_channel_irq(lch);
634 /* Clear the ENABLE_LNK bit */
638 p->dma_write(l, CLNK_CTRL, lch);
639 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
642 static inline void omap2_enable_irq_lch(int lch)
647 if (!cpu_class_is_omap2())
650 spin_lock_irqsave(&dma_chan_lock, flags);
651 val = p->dma_read(IRQENABLE_L0, lch);
653 p->dma_write(val, IRQENABLE_L0, lch);
654 spin_unlock_irqrestore(&dma_chan_lock, flags);
657 static inline void omap2_disable_irq_lch(int lch)
662 if (!cpu_class_is_omap2())
665 spin_lock_irqsave(&dma_chan_lock, flags);
666 val = p->dma_read(IRQENABLE_L0, lch);
668 p->dma_write(val, IRQENABLE_L0, lch);
669 spin_unlock_irqrestore(&dma_chan_lock, flags);
672 int omap_request_dma(int dev_id, const char *dev_name,
673 void (*callback)(int lch, u16 ch_status, void *data),
674 void *data, int *dma_ch_out)
676 int ch, free_ch = -1;
678 struct omap_dma_lch *chan;
680 spin_lock_irqsave(&dma_chan_lock, flags);
681 for (ch = 0; ch < dma_chan_count; ch++) {
682 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
689 spin_unlock_irqrestore(&dma_chan_lock, flags);
692 chan = dma_chan + free_ch;
693 chan->dev_id = dev_id;
695 if (p->clear_lch_regs)
696 p->clear_lch_regs(free_ch);
698 if (cpu_class_is_omap2())
699 omap_clear_dma(free_ch);
701 spin_unlock_irqrestore(&dma_chan_lock, flags);
703 chan->dev_name = dev_name;
704 chan->callback = callback;
708 #ifndef CONFIG_ARCH_OMAP1
709 if (cpu_class_is_omap2()) {
711 chan->next_linked_ch = -1;
715 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
717 if (cpu_class_is_omap1())
718 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
719 else if (cpu_class_is_omap2())
720 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
721 OMAP2_DMA_TRANS_ERR_IRQ;
723 if (cpu_is_omap16xx()) {
724 /* If the sync device is set, configure it dynamically. */
726 set_gdma_dev(free_ch + 1, dev_id);
727 dev_id = free_ch + 1;
730 * Disable the 1510 compatibility mode and set the sync device
733 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
734 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
735 p->dma_write(dev_id, CCR, free_ch);
738 if (cpu_class_is_omap2()) {
739 omap2_enable_irq_lch(free_ch);
740 omap_enable_channel_irq(free_ch);
741 /* Clear the CSR register and IRQ status register */
742 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
743 p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
746 *dma_ch_out = free_ch;
750 EXPORT_SYMBOL(omap_request_dma);
752 void omap_free_dma(int lch)
756 if (dma_chan[lch].dev_id == -1) {
757 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
762 if (cpu_class_is_omap1()) {
763 /* Disable all DMA interrupts for the channel. */
764 p->dma_write(0, CICR, lch);
765 /* Make sure the DMA transfer is stopped. */
766 p->dma_write(0, CCR, lch);
769 if (cpu_class_is_omap2()) {
770 omap2_disable_irq_lch(lch);
772 /* Clear the CSR register and IRQ status register */
773 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
774 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
776 /* Disable all DMA interrupts for the channel. */
777 p->dma_write(0, CICR, lch);
779 /* Make sure the DMA transfer is stopped. */
780 p->dma_write(0, CCR, lch);
784 spin_lock_irqsave(&dma_chan_lock, flags);
785 dma_chan[lch].dev_id = -1;
786 dma_chan[lch].next_lch = -1;
787 dma_chan[lch].callback = NULL;
788 spin_unlock_irqrestore(&dma_chan_lock, flags);
790 EXPORT_SYMBOL(omap_free_dma);
793 * @brief omap_dma_set_global_params : Set global priority settings for dma
796 * @param max_fifo_depth
797 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
798 * DMA_THREAD_RESERVE_ONET
799 * DMA_THREAD_RESERVE_TWOT
800 * DMA_THREAD_RESERVE_THREET
803 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
807 if (!cpu_class_is_omap2()) {
808 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
812 if (max_fifo_depth == 0)
817 reg = 0xff & max_fifo_depth;
818 reg |= (0x3 & tparams) << 12;
819 reg |= (arb_rate & 0xff) << 16;
821 p->dma_write(reg, GCR, 0);
823 EXPORT_SYMBOL(omap_dma_set_global_params);
826 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
829 * @param read_prio - Read priority
830 * @param write_prio - Write priority
831 * Both of the above can be set with one of the following values :
832 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
835 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
836 unsigned char write_prio)
840 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
841 printk(KERN_ERR "Invalid channel id\n");
844 l = p->dma_read(CCR, lch);
845 l &= ~((1 << 6) | (1 << 26));
846 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
847 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
849 l |= ((read_prio & 0x1) << 6);
851 p->dma_write(l, CCR, lch);
855 EXPORT_SYMBOL(omap_dma_set_prio_lch);
858 * Clears any DMA state so the DMA engine is ready to restart with new buffers
859 * through omap_start_dma(). Any buffers in flight are discarded.
861 void omap_clear_dma(int lch)
865 local_irq_save(flags);
867 local_irq_restore(flags);
869 EXPORT_SYMBOL(omap_clear_dma);
871 void omap_start_dma(int lch)
876 * The CPC/CDAC register needs to be initialized to zero
877 * before starting dma transfer.
879 if (cpu_is_omap15xx())
880 p->dma_write(0, CPC, lch);
882 p->dma_write(0, CDAC, lch);
884 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
885 int next_lch, cur_lch;
886 char dma_chan_link_map[dma_lch_count];
888 dma_chan_link_map[lch] = 1;
889 /* Set the link register of the first channel */
892 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
893 cur_lch = dma_chan[lch].next_lch;
895 next_lch = dma_chan[cur_lch].next_lch;
897 /* The loop case: we've been here already */
898 if (dma_chan_link_map[cur_lch])
900 /* Mark the current channel */
901 dma_chan_link_map[cur_lch] = 1;
904 omap_enable_channel_irq(cur_lch);
907 } while (next_lch != -1);
908 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
909 p->dma_write(lch, CLNK_CTRL, lch);
911 omap_enable_channel_irq(lch);
913 l = p->dma_read(CCR, lch);
915 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
916 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
917 l |= OMAP_DMA_CCR_EN;
919 p->dma_write(l, CCR, lch);
921 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
923 EXPORT_SYMBOL(omap_start_dma);
925 void omap_stop_dma(int lch)
929 /* Disable all interrupts on the channel */
930 if (cpu_class_is_omap1())
931 p->dma_write(0, CICR, lch);
933 l = p->dma_read(CCR, lch);
934 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
935 (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
939 /* Configure No-Standby */
940 l = p->dma_read(OCP_SYSCONFIG, lch);
942 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
943 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
944 p->dma_write(l , OCP_SYSCONFIG, 0);
946 l = p->dma_read(CCR, lch);
947 l &= ~OMAP_DMA_CCR_EN;
948 p->dma_write(l, CCR, lch);
950 /* Wait for sDMA FIFO drain */
951 l = p->dma_read(CCR, lch);
952 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
953 OMAP_DMA_CCR_WR_ACTIVE))) {
956 l = p->dma_read(CCR, lch);
959 printk(KERN_ERR "DMA drain did not complete on "
961 /* Restore OCP_SYSCONFIG */
962 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
964 l &= ~OMAP_DMA_CCR_EN;
965 p->dma_write(l, CCR, lch);
968 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
969 int next_lch, cur_lch = lch;
970 char dma_chan_link_map[dma_lch_count];
972 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
974 /* The loop case: we've been here already */
975 if (dma_chan_link_map[cur_lch])
977 /* Mark the current channel */
978 dma_chan_link_map[cur_lch] = 1;
980 disable_lnk(cur_lch);
982 next_lch = dma_chan[cur_lch].next_lch;
984 } while (next_lch != -1);
987 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
989 EXPORT_SYMBOL(omap_stop_dma);
992 * Allows changing the DMA callback function or data. This may be needed if
993 * the driver shares a single DMA channel for multiple dma triggers.
995 int omap_set_dma_callback(int lch,
996 void (*callback)(int lch, u16 ch_status, void *data),
1004 spin_lock_irqsave(&dma_chan_lock, flags);
1005 if (dma_chan[lch].dev_id == -1) {
1006 printk(KERN_ERR "DMA callback for not set for free channel\n");
1007 spin_unlock_irqrestore(&dma_chan_lock, flags);
1010 dma_chan[lch].callback = callback;
1011 dma_chan[lch].data = data;
1012 spin_unlock_irqrestore(&dma_chan_lock, flags);
1016 EXPORT_SYMBOL(omap_set_dma_callback);
1019 * Returns current physical source address for the given DMA channel.
1020 * If the channel is running the caller must disable interrupts prior calling
1021 * this function and process the returned value before re-enabling interrupt to
1022 * prevent races with the interrupt handler. Note that in continuous mode there
1023 * is a chance for CSSA_L register overflow between the two reads resulting
1024 * in incorrect return value.
1026 dma_addr_t omap_get_dma_src_pos(int lch)
1028 dma_addr_t offset = 0;
1030 if (cpu_is_omap15xx())
1031 offset = p->dma_read(CPC, lch);
1033 offset = p->dma_read(CSAC, lch);
1035 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1036 offset = p->dma_read(CSAC, lch);
1038 if (!cpu_is_omap15xx()) {
1040 * CDAC == 0 indicates that the DMA transfer on the channel has
1041 * not been started (no data has been transferred so far).
1042 * Return the programmed source start address in this case.
1044 if (likely(p->dma_read(CDAC, lch)))
1045 offset = p->dma_read(CSAC, lch);
1047 offset = p->dma_read(CSSA, lch);
1050 if (cpu_class_is_omap1())
1051 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1055 EXPORT_SYMBOL(omap_get_dma_src_pos);
1058 * Returns current physical destination address for the given DMA channel.
1059 * If the channel is running the caller must disable interrupts prior calling
1060 * this function and process the returned value before re-enabling interrupt to
1061 * prevent races with the interrupt handler. Note that in continuous mode there
1062 * is a chance for CDSA_L register overflow between the two reads resulting
1063 * in incorrect return value.
1065 dma_addr_t omap_get_dma_dst_pos(int lch)
1067 dma_addr_t offset = 0;
1069 if (cpu_is_omap15xx())
1070 offset = p->dma_read(CPC, lch);
1072 offset = p->dma_read(CDAC, lch);
1075 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1076 * read before the DMA controller finished disabling the channel.
1078 if (!cpu_is_omap15xx() && offset == 0) {
1079 offset = p->dma_read(CDAC, lch);
1081 * CDAC == 0 indicates that the DMA transfer on the channel has
1082 * not been started (no data has been transferred so far).
1083 * Return the programmed destination start address in this case.
1085 if (unlikely(!offset))
1086 offset = p->dma_read(CDSA, lch);
1089 if (cpu_class_is_omap1())
1090 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1094 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1096 int omap_get_dma_active_status(int lch)
1098 return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1100 EXPORT_SYMBOL(omap_get_dma_active_status);
1102 int omap_dma_running(void)
1106 if (cpu_class_is_omap1())
1107 if (omap_lcd_dma_running())
1110 for (lch = 0; lch < dma_chan_count; lch++)
1111 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1118 * lch_queue DMA will start right after lch_head one is finished.
1119 * For this DMA link to start, you still need to start (see omap_start_dma)
1120 * the first one. That will fire up the entire queue.
1122 void omap_dma_link_lch(int lch_head, int lch_queue)
1124 if (omap_dma_in_1510_mode()) {
1125 if (lch_head == lch_queue) {
1126 p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1130 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1135 if ((dma_chan[lch_head].dev_id == -1) ||
1136 (dma_chan[lch_queue].dev_id == -1)) {
1137 printk(KERN_ERR "omap_dma: trying to link "
1138 "non requested channels\n");
1142 dma_chan[lch_head].next_lch = lch_queue;
1144 EXPORT_SYMBOL(omap_dma_link_lch);
1147 * Once the DMA queue is stopped, we can destroy it.
1149 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1151 if (omap_dma_in_1510_mode()) {
1152 if (lch_head == lch_queue) {
1153 p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1157 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1162 if (dma_chan[lch_head].next_lch != lch_queue ||
1163 dma_chan[lch_head].next_lch == -1) {
1164 printk(KERN_ERR "omap_dma: trying to unlink "
1165 "non linked channels\n");
1169 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1170 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1171 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1172 "before unlinking\n");
1176 dma_chan[lch_head].next_lch = -1;
1178 EXPORT_SYMBOL(omap_dma_unlink_lch);
1180 #ifndef CONFIG_ARCH_OMAP1
1181 /* Create chain of DMA channesls */
1182 static void create_dma_lch_chain(int lch_head, int lch_queue)
1186 /* Check if this is the first link in chain */
1187 if (dma_chan[lch_head].next_linked_ch == -1) {
1188 dma_chan[lch_head].next_linked_ch = lch_queue;
1189 dma_chan[lch_head].prev_linked_ch = lch_queue;
1190 dma_chan[lch_queue].next_linked_ch = lch_head;
1191 dma_chan[lch_queue].prev_linked_ch = lch_head;
1194 /* a link exists, link the new channel in circular chain */
1196 dma_chan[lch_queue].next_linked_ch =
1197 dma_chan[lch_head].next_linked_ch;
1198 dma_chan[lch_queue].prev_linked_ch = lch_head;
1199 dma_chan[lch_head].next_linked_ch = lch_queue;
1200 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1204 l = p->dma_read(CLNK_CTRL, lch_head);
1207 p->dma_write(l, CLNK_CTRL, lch_head);
1209 l = p->dma_read(CLNK_CTRL, lch_queue);
1211 l |= (dma_chan[lch_queue].next_linked_ch);
1212 p->dma_write(l, CLNK_CTRL, lch_queue);
1216 * @brief omap_request_dma_chain : Request a chain of DMA channels
1218 * @param dev_id - Device id using the dma channel
1219 * @param dev_name - Device name
1220 * @param callback - Call back function
1222 * @no_of_chans - Number of channels requested
1223 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1224 * OMAP_DMA_DYNAMIC_CHAIN
1225 * @params - Channel parameters
1227 * @return - Success : 0
1228 * Failure: -EINVAL/-ENOMEM
1230 int omap_request_dma_chain(int dev_id, const char *dev_name,
1231 void (*callback) (int lch, u16 ch_status,
1233 int *chain_id, int no_of_chans, int chain_mode,
1234 struct omap_dma_channel_params params)
1239 /* Is the chain mode valid ? */
1240 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1241 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1242 printk(KERN_ERR "Invalid chain mode requested\n");
1246 if (unlikely((no_of_chans < 1
1247 || no_of_chans > dma_lch_count))) {
1248 printk(KERN_ERR "Invalid Number of channels requested\n");
1253 * Allocate a queue to maintain the status of the channels
1256 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1257 if (channels == NULL) {
1258 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1262 /* request and reserve DMA channels for the chain */
1263 for (i = 0; i < no_of_chans; i++) {
1264 err = omap_request_dma(dev_id, dev_name,
1265 callback, NULL, &channels[i]);
1268 for (j = 0; j < i; j++)
1269 omap_free_dma(channels[j]);
1271 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1274 dma_chan[channels[i]].prev_linked_ch = -1;
1275 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1278 * Allowing client drivers to set common parameters now,
1279 * so that later only relevant (src_start, dest_start
1280 * and element count) can be set
1282 omap_set_dma_params(channels[i], ¶ms);
1285 *chain_id = channels[0];
1286 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1287 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1288 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1289 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1291 for (i = 0; i < no_of_chans; i++)
1292 dma_chan[channels[i]].chain_id = *chain_id;
1294 /* Reset the Queue pointers */
1295 OMAP_DMA_CHAIN_QINIT(*chain_id);
1297 /* Set up the chain */
1298 if (no_of_chans == 1)
1299 create_dma_lch_chain(channels[0], channels[0]);
1301 for (i = 0; i < (no_of_chans - 1); i++)
1302 create_dma_lch_chain(channels[i], channels[i + 1]);
1307 EXPORT_SYMBOL(omap_request_dma_chain);
1310 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1311 * params after setting it. Dont do this while dma is running!!
1313 * @param chain_id - Chained logical channel id.
1316 * @return - Success : 0
1319 int omap_modify_dma_chain_params(int chain_id,
1320 struct omap_dma_channel_params params)
1325 /* Check for input params */
1326 if (unlikely((chain_id < 0
1327 || chain_id >= dma_lch_count))) {
1328 printk(KERN_ERR "Invalid chain id\n");
1332 /* Check if the chain exists */
1333 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1334 printk(KERN_ERR "Chain doesn't exists\n");
1337 channels = dma_linked_lch[chain_id].linked_dmach_q;
1339 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1341 * Allowing client drivers to set common parameters now,
1342 * so that later only relevant (src_start, dest_start
1343 * and element count) can be set
1345 omap_set_dma_params(channels[i], ¶ms);
1350 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1353 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1357 * @return - Success : 0
1360 int omap_free_dma_chain(int chain_id)
1365 /* Check for input params */
1366 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1367 printk(KERN_ERR "Invalid chain id\n");
1371 /* Check if the chain exists */
1372 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1373 printk(KERN_ERR "Chain doesn't exists\n");
1377 channels = dma_linked_lch[chain_id].linked_dmach_q;
1378 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1379 dma_chan[channels[i]].next_linked_ch = -1;
1380 dma_chan[channels[i]].prev_linked_ch = -1;
1381 dma_chan[channels[i]].chain_id = -1;
1382 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1383 omap_free_dma(channels[i]);
1388 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1389 dma_linked_lch[chain_id].chain_mode = -1;
1390 dma_linked_lch[chain_id].chain_state = -1;
1394 EXPORT_SYMBOL(omap_free_dma_chain);
1397 * @brief omap_dma_chain_status - Check if the chain is in
1398 * active / inactive state.
1401 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1404 int omap_dma_chain_status(int chain_id)
1406 /* Check for input params */
1407 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1408 printk(KERN_ERR "Invalid chain id\n");
1412 /* Check if the chain exists */
1413 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1414 printk(KERN_ERR "Chain doesn't exists\n");
1417 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1418 dma_linked_lch[chain_id].q_count);
1420 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1421 return OMAP_DMA_CHAIN_INACTIVE;
1423 return OMAP_DMA_CHAIN_ACTIVE;
1425 EXPORT_SYMBOL(omap_dma_chain_status);
1428 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1429 * set the params and start the transfer.
1432 * @param src_start - buffer start address
1433 * @param dest_start - Dest address
1435 * @param frame_count
1436 * @param callbk_data - channel callback parameter data.
1438 * @return - Success : 0
1439 * Failure: -EINVAL/-EBUSY
1441 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1442 int elem_count, int frame_count, void *callbk_data)
1449 * if buffer size is less than 1 then there is
1450 * no use of starting the chain
1452 if (elem_count < 1) {
1453 printk(KERN_ERR "Invalid buffer size\n");
1457 /* Check for input params */
1458 if (unlikely((chain_id < 0
1459 || chain_id >= dma_lch_count))) {
1460 printk(KERN_ERR "Invalid chain id\n");
1464 /* Check if the chain exists */
1465 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1466 printk(KERN_ERR "Chain doesn't exist\n");
1470 /* Check if all the channels in chain are in use */
1471 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1474 /* Frame count may be negative in case of indexed transfers */
1475 channels = dma_linked_lch[chain_id].linked_dmach_q;
1477 /* Get a free channel */
1478 lch = channels[dma_linked_lch[chain_id].q_tail];
1480 /* Store the callback data */
1481 dma_chan[lch].data = callbk_data;
1483 /* Increment the q_tail */
1484 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1486 /* Set the params to the free channel */
1488 p->dma_write(src_start, CSSA, lch);
1489 if (dest_start != 0)
1490 p->dma_write(dest_start, CDSA, lch);
1492 /* Write the buffer size */
1493 p->dma_write(elem_count, CEN, lch);
1494 p->dma_write(frame_count, CFN, lch);
1497 * If the chain is dynamically linked,
1498 * then we may have to start the chain if its not active
1500 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1503 * In Dynamic chain, if the chain is not started,
1506 if (dma_linked_lch[chain_id].chain_state ==
1507 DMA_CHAIN_NOTSTARTED) {
1508 /* Enable the link in previous channel */
1509 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1511 enable_lnk(dma_chan[lch].prev_linked_ch);
1512 dma_chan[lch].state = DMA_CH_QUEUED;
1516 * Chain is already started, make sure its active,
1517 * if not then start the chain
1522 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1524 enable_lnk(dma_chan[lch].prev_linked_ch);
1525 dma_chan[lch].state = DMA_CH_QUEUED;
1527 if (0 == ((1 << 7) & p->dma_read(
1528 CCR, dma_chan[lch].prev_linked_ch))) {
1529 disable_lnk(dma_chan[lch].
1531 pr_debug("\n prev ch is stopped\n");
1536 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1538 enable_lnk(dma_chan[lch].prev_linked_ch);
1539 dma_chan[lch].state = DMA_CH_QUEUED;
1542 omap_enable_channel_irq(lch);
1544 l = p->dma_read(CCR, lch);
1546 if ((0 == (l & (1 << 24))))
1550 if (start_dma == 1) {
1551 if (0 == (l & (1 << 7))) {
1553 dma_chan[lch].state = DMA_CH_STARTED;
1554 pr_debug("starting %d\n", lch);
1555 p->dma_write(l, CCR, lch);
1559 if (0 == (l & (1 << 7)))
1560 p->dma_write(l, CCR, lch);
1562 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1568 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1571 * @brief omap_start_dma_chain_transfers - Start the chain
1575 * @return - Success : 0
1576 * Failure : -EINVAL/-EBUSY
1578 int omap_start_dma_chain_transfers(int chain_id)
1583 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1584 printk(KERN_ERR "Invalid chain id\n");
1588 channels = dma_linked_lch[chain_id].linked_dmach_q;
1590 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1591 printk(KERN_ERR "Chain is already started\n");
1595 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1596 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1598 enable_lnk(channels[i]);
1599 omap_enable_channel_irq(channels[i]);
1602 omap_enable_channel_irq(channels[0]);
1605 l = p->dma_read(CCR, channels[0]);
1607 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1608 dma_chan[channels[0]].state = DMA_CH_STARTED;
1610 if ((0 == (l & (1 << 24))))
1614 p->dma_write(l, CCR, channels[0]);
1616 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1620 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1623 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1627 * @return - Success : 0
1630 int omap_stop_dma_chain_transfers(int chain_id)
1636 /* Check for input params */
1637 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1638 printk(KERN_ERR "Invalid chain id\n");
1642 /* Check if the chain exists */
1643 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1644 printk(KERN_ERR "Chain doesn't exists\n");
1647 channels = dma_linked_lch[chain_id].linked_dmach_q;
1649 if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1650 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1652 /* Middle mode reg set no Standby */
1653 l &= ~((1 << 12)|(1 << 13));
1654 p->dma_write(l, OCP_SYSCONFIG, 0);
1657 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1659 /* Stop the Channel transmission */
1660 l = p->dma_read(CCR, channels[i]);
1662 p->dma_write(l, CCR, channels[i]);
1664 /* Disable the link in all the channels */
1665 disable_lnk(channels[i]);
1666 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1669 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1671 /* Reset the Queue pointers */
1672 OMAP_DMA_CHAIN_QINIT(chain_id);
1674 if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1675 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1679 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1681 /* Get the index of the ongoing DMA in chain */
1683 * @brief omap_get_dma_chain_index - Get the element and frame index
1684 * of the ongoing DMA in chain
1687 * @param ei - Element index
1688 * @param fi - Frame index
1690 * @return - Success : 0
1693 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1698 /* Check for input params */
1699 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1700 printk(KERN_ERR "Invalid chain id\n");
1704 /* Check if the chain exists */
1705 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1706 printk(KERN_ERR "Chain doesn't exists\n");
1712 channels = dma_linked_lch[chain_id].linked_dmach_q;
1714 /* Get the current channel */
1715 lch = channels[dma_linked_lch[chain_id].q_head];
1717 *ei = p->dma_read(CCEN, lch);
1718 *fi = p->dma_read(CCFN, lch);
1722 EXPORT_SYMBOL(omap_get_dma_chain_index);
1725 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1726 * ongoing DMA in chain
1730 * @return - Success : Destination position
1733 int omap_get_dma_chain_dst_pos(int chain_id)
1738 /* Check for input params */
1739 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1740 printk(KERN_ERR "Invalid chain id\n");
1744 /* Check if the chain exists */
1745 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1746 printk(KERN_ERR "Chain doesn't exists\n");
1750 channels = dma_linked_lch[chain_id].linked_dmach_q;
1752 /* Get the current channel */
1753 lch = channels[dma_linked_lch[chain_id].q_head];
1755 return p->dma_read(CDAC, lch);
1757 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1760 * @brief omap_get_dma_chain_src_pos - Get the source position
1761 * of the ongoing DMA in chain
1764 * @return - Success : Destination position
1767 int omap_get_dma_chain_src_pos(int chain_id)
1772 /* Check for input params */
1773 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1774 printk(KERN_ERR "Invalid chain id\n");
1778 /* Check if the chain exists */
1779 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1780 printk(KERN_ERR "Chain doesn't exists\n");
1784 channels = dma_linked_lch[chain_id].linked_dmach_q;
1786 /* Get the current channel */
1787 lch = channels[dma_linked_lch[chain_id].q_head];
1789 return p->dma_read(CSAC, lch);
1791 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1792 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1794 /*----------------------------------------------------------------------------*/
1796 #ifdef CONFIG_ARCH_OMAP1
1798 static int omap1_dma_handle_ch(int ch)
1802 if (enable_1510_mode && ch >= 6) {
1803 csr = dma_chan[ch].saved_csr;
1804 dma_chan[ch].saved_csr = 0;
1806 csr = p->dma_read(CSR, ch);
1807 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1808 dma_chan[ch + 6].saved_csr = csr >> 7;
1811 if ((csr & 0x3f) == 0)
1813 if (unlikely(dma_chan[ch].dev_id == -1)) {
1814 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1815 "%d (CSR %04x)\n", ch, csr);
1818 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1819 printk(KERN_WARNING "DMA timeout with device %d\n",
1820 dma_chan[ch].dev_id);
1821 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1822 printk(KERN_WARNING "DMA synchronization event drop occurred "
1823 "with device %d\n", dma_chan[ch].dev_id);
1824 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1825 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1826 if (likely(dma_chan[ch].callback != NULL))
1827 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1832 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1834 int ch = ((int) dev_id) - 1;
1838 int handled_now = 0;
1840 handled_now += omap1_dma_handle_ch(ch);
1841 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1842 handled_now += omap1_dma_handle_ch(ch + 6);
1845 handled += handled_now;
1848 return handled ? IRQ_HANDLED : IRQ_NONE;
1852 #define omap1_dma_irq_handler NULL
1855 #ifdef CONFIG_ARCH_OMAP2PLUS
1857 static int omap2_dma_handle_ch(int ch)
1859 u32 status = p->dma_read(CSR, ch);
1862 if (printk_ratelimit())
1863 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1865 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1868 if (unlikely(dma_chan[ch].dev_id == -1)) {
1869 if (printk_ratelimit())
1870 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1871 "channel %d\n", status, ch);
1874 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1876 "DMA synchronization event drop occurred with device "
1877 "%d\n", dma_chan[ch].dev_id);
1878 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1879 printk(KERN_INFO "DMA transaction error with device %d\n",
1880 dma_chan[ch].dev_id);
1881 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1884 ccr = p->dma_read(CCR, ch);
1885 ccr &= ~OMAP_DMA_CCR_EN;
1886 p->dma_write(ccr, CCR, ch);
1887 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1890 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1891 printk(KERN_INFO "DMA secure error with device %d\n",
1892 dma_chan[ch].dev_id);
1893 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1894 printk(KERN_INFO "DMA misaligned error with device %d\n",
1895 dma_chan[ch].dev_id);
1897 p->dma_write(status, CSR, ch);
1898 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1899 /* read back the register to flush the write */
1900 p->dma_read(IRQSTATUS_L0, ch);
1902 /* If the ch is not chained then chain_id will be -1 */
1903 if (dma_chan[ch].chain_id != -1) {
1904 int chain_id = dma_chan[ch].chain_id;
1905 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1906 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1907 dma_chan[dma_chan[ch].next_linked_ch].state =
1909 if (dma_linked_lch[chain_id].chain_mode ==
1910 OMAP_DMA_DYNAMIC_CHAIN)
1913 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1914 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1916 status = p->dma_read(CSR, ch);
1917 p->dma_write(status, CSR, ch);
1920 if (likely(dma_chan[ch].callback != NULL))
1921 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1926 /* STATUS register count is from 1-32 while our is 0-31 */
1927 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1929 u32 val, enable_reg;
1932 val = p->dma_read(IRQSTATUS_L0, 0);
1934 if (printk_ratelimit())
1935 printk(KERN_WARNING "Spurious DMA IRQ\n");
1938 enable_reg = p->dma_read(IRQENABLE_L0, 0);
1939 val &= enable_reg; /* Dispatch only relevant interrupts */
1940 for (i = 0; i < dma_lch_count && val != 0; i++) {
1942 omap2_dma_handle_ch(i);
1949 static struct irqaction omap24xx_dma_irq = {
1951 .handler = omap2_dma_irq_handler,
1952 .flags = IRQF_DISABLED
1956 static struct irqaction omap24xx_dma_irq;
1959 /*----------------------------------------------------------------------------*/
1961 void omap_dma_global_context_save(void)
1963 omap_dma_global_context.dma_irqenable_l0 =
1964 p->dma_read(IRQENABLE_L0, 0);
1965 omap_dma_global_context.dma_ocp_sysconfig =
1966 p->dma_read(OCP_SYSCONFIG, 0);
1967 omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1970 void omap_dma_global_context_restore(void)
1974 p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1975 p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1977 p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1980 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1981 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1983 for (ch = 0; ch < dma_chan_count; ch++)
1984 if (dma_chan[ch].dev_id != -1)
1988 static int __devinit omap_system_dma_probe(struct platform_device *pdev)
1995 p = pdev->dev.platform_data;
1997 dev_err(&pdev->dev, "%s: System DMA initialized without"
1998 "platform data\n", __func__);
2005 if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
2006 && (omap_dma_reserve_channels <= dma_lch_count))
2007 d->lch_count = omap_dma_reserve_channels;
2009 dma_lch_count = d->lch_count;
2010 dma_chan_count = dma_lch_count;
2012 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
2014 if (cpu_class_is_omap2()) {
2015 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2016 dma_lch_count, GFP_KERNEL);
2017 if (!dma_linked_lch) {
2019 goto exit_dma_lch_fail;
2023 spin_lock_init(&dma_chan_lock);
2024 for (ch = 0; ch < dma_chan_count; ch++) {
2026 if (cpu_class_is_omap2())
2027 omap2_disable_irq_lch(ch);
2029 dma_chan[ch].dev_id = -1;
2030 dma_chan[ch].next_lch = -1;
2032 if (ch >= 6 && enable_1510_mode)
2035 if (cpu_class_is_omap1()) {
2037 * request_irq() doesn't like dev_id (ie. ch) being
2038 * zero, so we have to kludge around this.
2040 sprintf(&irq_name[0], "%d", ch);
2041 dma_irq = platform_get_irq_byname(pdev, irq_name);
2045 goto exit_dma_irq_fail;
2048 /* INT_DMA_LCD is handled in lcd_dma.c */
2049 if (dma_irq == INT_DMA_LCD)
2052 ret = request_irq(dma_irq,
2053 omap1_dma_irq_handler, 0, "DMA",
2056 goto exit_dma_irq_fail;
2060 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2061 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2062 DMA_DEFAULT_FIFO_DEPTH, 0);
2064 if (cpu_class_is_omap2()) {
2065 strcpy(irq_name, "0");
2066 dma_irq = platform_get_irq_byname(pdev, irq_name);
2068 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2069 goto exit_dma_lch_fail;
2071 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2073 dev_err(&pdev->dev, "set_up failed for IRQ %d"
2074 "for DMA (error %d)\n", dma_irq, ret);
2075 goto exit_dma_lch_fail;
2079 /* reserve dma channels 0 and 1 in high security devices */
2080 if (cpu_is_omap34xx() &&
2081 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2082 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2084 dma_chan[0].dev_id = 0;
2085 dma_chan[1].dev_id = 1;
2091 dev_err(&pdev->dev, "unable to request IRQ %d"
2092 "for DMA (error %d)\n", dma_irq, ret);
2093 for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2094 dma_irq = platform_get_irq(pdev, irq_rel);
2095 free_irq(dma_irq, (void *)(irq_rel + 1));
2105 static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2109 if (cpu_class_is_omap2()) {
2111 strcpy(irq_name, "0");
2112 dma_irq = platform_get_irq_byname(pdev, irq_name);
2113 remove_irq(dma_irq, &omap24xx_dma_irq);
2116 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2117 dma_irq = platform_get_irq(pdev, irq_rel);
2118 free_irq(dma_irq, (void *)(irq_rel + 1));
2127 static struct platform_driver omap_system_dma_driver = {
2128 .probe = omap_system_dma_probe,
2129 .remove = __devexit_p(omap_system_dma_remove),
2131 .name = "omap_dma_system"
2135 static int __init omap_system_dma_init(void)
2137 return platform_driver_register(&omap_system_dma_driver);
2139 arch_initcall(omap_system_dma_init);
2141 static void __exit omap_system_dma_exit(void)
2143 platform_driver_unregister(&omap_system_dma_driver);
2146 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2147 MODULE_LICENSE("GPL");
2148 MODULE_ALIAS("platform:" DRIVER_NAME);
2149 MODULE_AUTHOR("Texas Instruments Inc");
2152 * Reserve the omap SDMA channels using cmdline bootarg
2153 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2155 static int __init omap_dma_cmdline_reserve_ch(char *str)
2157 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2158 omap_dma_reserve_channels = 0;
2162 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);