2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Support functions for the OMAP internal DMA channels.
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/sched.h>
27 #include <linux/spinlock.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
33 #include <asm/system.h>
34 #include <mach/hardware.h>
41 #ifndef CONFIG_ARCH_OMAP1
42 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
43 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
46 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
49 #define OMAP_DMA_ACTIVE 0x01
50 #define OMAP_DMA_CCR_EN (1 << 7)
51 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
53 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
55 static int enable_1510_mode;
63 void (*callback)(int lch, u16 ch_status, void *data);
66 #ifndef CONFIG_ARCH_OMAP1
67 /* required for Dynamic chaining */
78 struct dma_link_info {
80 int no_of_lchs_linked;
91 static struct dma_link_info *dma_linked_lch;
93 #ifndef CONFIG_ARCH_OMAP1
95 /* Chain handling macros */
96 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
98 dma_linked_lch[chain_id].q_head = \
99 dma_linked_lch[chain_id].q_tail = \
100 dma_linked_lch[chain_id].q_count = 0; \
102 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
103 (dma_linked_lch[chain_id].no_of_lchs_linked == \
104 dma_linked_lch[chain_id].q_count)
105 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
107 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
108 dma_linked_lch[chain_id].q_count) \
110 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
111 (0 == dma_linked_lch[chain_id].q_count)
112 #define __OMAP_DMA_CHAIN_INCQ(end) \
113 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
114 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
116 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
117 dma_linked_lch[chain_id].q_count--; \
120 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
122 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
123 dma_linked_lch[chain_id].q_count++; \
127 static int dma_lch_count;
128 static int dma_chan_count;
129 static int omap_dma_reserve_channels;
131 static spinlock_t dma_chan_lock;
132 static struct omap_dma_lch *dma_chan;
133 static void __iomem *omap_dma_base;
135 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
136 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
137 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
138 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
139 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
140 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
143 static inline void disable_lnk(int lch);
144 static void omap_disable_channel_irq(int lch);
145 static inline void omap_enable_channel_irq(int lch);
147 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
150 #define dma_read(reg) \
153 if (cpu_class_is_omap1()) \
154 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
156 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
160 #define dma_write(val, reg) \
162 if (cpu_class_is_omap1()) \
163 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
165 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
168 #ifdef CONFIG_ARCH_OMAP15XX
169 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
170 int omap_dma_in_1510_mode(void)
172 return enable_1510_mode;
175 #define omap_dma_in_1510_mode() 0
178 #ifdef CONFIG_ARCH_OMAP1
179 static inline int get_gdma_dev(int req)
181 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
182 int shift = ((req - 1) % 5) * 6;
184 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
187 static inline void set_gdma_dev(int req, int dev)
189 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
190 int shift = ((req - 1) % 5) * 6;
194 l &= ~(0x3f << shift);
195 l |= (dev - 1) << shift;
199 #define set_gdma_dev(req, dev) do {} while (0)
203 static void clear_lch_regs(int lch)
206 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
208 for (i = 0; i < 0x2c; i += 2)
209 __raw_writew(0, lch_base + i);
212 void omap_set_dma_priority(int lch, int dst_port, int priority)
217 if (cpu_class_is_omap1()) {
219 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
220 reg = OMAP_TC_OCPT1_PRIOR;
222 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
223 reg = OMAP_TC_OCPT2_PRIOR;
225 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
226 reg = OMAP_TC_EMIFF_PRIOR;
228 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
229 reg = OMAP_TC_EMIFS_PRIOR;
237 l |= (priority & 0xf) << 8;
241 if (cpu_class_is_omap2()) {
244 ccr = dma_read(CCR(lch));
249 dma_write(ccr, CCR(lch));
252 EXPORT_SYMBOL(omap_set_dma_priority);
254 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
255 int frame_count, int sync_mode,
256 int dma_trigger, int src_or_dst_synch)
260 l = dma_read(CSDP(lch));
263 dma_write(l, CSDP(lch));
265 if (cpu_class_is_omap1()) {
268 ccr = dma_read(CCR(lch));
270 if (sync_mode == OMAP_DMA_SYNC_FRAME)
272 dma_write(ccr, CCR(lch));
274 ccr = dma_read(CCR2(lch));
276 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
278 dma_write(ccr, CCR2(lch));
281 if (cpu_class_is_omap2() && dma_trigger) {
284 val = dma_read(CCR(lch));
286 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
287 val &= ~((3 << 19) | 0x1f);
288 val |= (dma_trigger & ~0x1f) << 14;
289 val |= dma_trigger & 0x1f;
291 if (sync_mode & OMAP_DMA_SYNC_FRAME)
296 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
301 if (src_or_dst_synch)
302 val |= 1 << 24; /* source synch */
304 val &= ~(1 << 24); /* dest synch */
306 dma_write(val, CCR(lch));
309 dma_write(elem_count, CEN(lch));
310 dma_write(frame_count, CFN(lch));
312 EXPORT_SYMBOL(omap_set_dma_transfer_params);
314 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
316 BUG_ON(omap_dma_in_1510_mode());
318 if (cpu_class_is_omap1()) {
321 w = dma_read(CCR2(lch));
325 case OMAP_DMA_CONSTANT_FILL:
328 case OMAP_DMA_TRANSPARENT_COPY:
331 case OMAP_DMA_COLOR_DIS:
336 dma_write(w, CCR2(lch));
338 w = dma_read(LCH_CTRL(lch));
340 /* Default is channel type 2D */
342 dma_write((u16)color, COLOR_L(lch));
343 dma_write((u16)(color >> 16), COLOR_U(lch));
344 w |= 1; /* Channel type G */
346 dma_write(w, LCH_CTRL(lch));
349 if (cpu_class_is_omap2()) {
352 val = dma_read(CCR(lch));
353 val &= ~((1 << 17) | (1 << 16));
356 case OMAP_DMA_CONSTANT_FILL:
359 case OMAP_DMA_TRANSPARENT_COPY:
362 case OMAP_DMA_COLOR_DIS:
367 dma_write(val, CCR(lch));
370 dma_write(color, COLOR(lch));
373 EXPORT_SYMBOL(omap_set_dma_color_mode);
375 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
377 if (cpu_class_is_omap2()) {
380 csdp = dma_read(CSDP(lch));
381 csdp &= ~(0x3 << 16);
382 csdp |= (mode << 16);
383 dma_write(csdp, CSDP(lch));
386 EXPORT_SYMBOL(omap_set_dma_write_mode);
388 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
390 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
393 l = dma_read(LCH_CTRL(lch));
396 dma_write(l, LCH_CTRL(lch));
399 EXPORT_SYMBOL(omap_set_dma_channel_mode);
401 /* Note that src_port is only for omap1 */
402 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
403 unsigned long src_start,
404 int src_ei, int src_fi)
408 if (cpu_class_is_omap1()) {
411 w = dma_read(CSDP(lch));
414 dma_write(w, CSDP(lch));
417 l = dma_read(CCR(lch));
419 l |= src_amode << 12;
420 dma_write(l, CCR(lch));
422 if (cpu_class_is_omap1()) {
423 dma_write(src_start >> 16, CSSA_U(lch));
424 dma_write((u16)src_start, CSSA_L(lch));
427 if (cpu_class_is_omap2())
428 dma_write(src_start, CSSA(lch));
430 dma_write(src_ei, CSEI(lch));
431 dma_write(src_fi, CSFI(lch));
433 EXPORT_SYMBOL(omap_set_dma_src_params);
435 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
437 omap_set_dma_transfer_params(lch, params->data_type,
438 params->elem_count, params->frame_count,
439 params->sync_mode, params->trigger,
440 params->src_or_dst_synch);
441 omap_set_dma_src_params(lch, params->src_port,
442 params->src_amode, params->src_start,
443 params->src_ei, params->src_fi);
445 omap_set_dma_dest_params(lch, params->dst_port,
446 params->dst_amode, params->dst_start,
447 params->dst_ei, params->dst_fi);
448 if (params->read_prio || params->write_prio)
449 omap_dma_set_prio_lch(lch, params->read_prio,
452 EXPORT_SYMBOL(omap_set_dma_params);
454 void omap_set_dma_src_index(int lch, int eidx, int fidx)
456 if (cpu_class_is_omap2())
459 dma_write(eidx, CSEI(lch));
460 dma_write(fidx, CSFI(lch));
462 EXPORT_SYMBOL(omap_set_dma_src_index);
464 void omap_set_dma_src_data_pack(int lch, int enable)
468 l = dma_read(CSDP(lch));
472 dma_write(l, CSDP(lch));
474 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
476 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
478 unsigned int burst = 0;
481 l = dma_read(CSDP(lch));
484 switch (burst_mode) {
485 case OMAP_DMA_DATA_BURST_DIS:
487 case OMAP_DMA_DATA_BURST_4:
488 if (cpu_class_is_omap2())
493 case OMAP_DMA_DATA_BURST_8:
494 if (cpu_class_is_omap2()) {
498 /* not supported by current hardware on OMAP1
502 case OMAP_DMA_DATA_BURST_16:
503 if (cpu_class_is_omap2()) {
507 /* OMAP1 don't support burst 16
515 dma_write(l, CSDP(lch));
517 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
519 /* Note that dest_port is only for OMAP1 */
520 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
521 unsigned long dest_start,
522 int dst_ei, int dst_fi)
526 if (cpu_class_is_omap1()) {
527 l = dma_read(CSDP(lch));
530 dma_write(l, CSDP(lch));
533 l = dma_read(CCR(lch));
535 l |= dest_amode << 14;
536 dma_write(l, CCR(lch));
538 if (cpu_class_is_omap1()) {
539 dma_write(dest_start >> 16, CDSA_U(lch));
540 dma_write(dest_start, CDSA_L(lch));
543 if (cpu_class_is_omap2())
544 dma_write(dest_start, CDSA(lch));
546 dma_write(dst_ei, CDEI(lch));
547 dma_write(dst_fi, CDFI(lch));
549 EXPORT_SYMBOL(omap_set_dma_dest_params);
551 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
553 if (cpu_class_is_omap2())
556 dma_write(eidx, CDEI(lch));
557 dma_write(fidx, CDFI(lch));
559 EXPORT_SYMBOL(omap_set_dma_dest_index);
561 void omap_set_dma_dest_data_pack(int lch, int enable)
565 l = dma_read(CSDP(lch));
569 dma_write(l, CSDP(lch));
571 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
573 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
575 unsigned int burst = 0;
578 l = dma_read(CSDP(lch));
581 switch (burst_mode) {
582 case OMAP_DMA_DATA_BURST_DIS:
584 case OMAP_DMA_DATA_BURST_4:
585 if (cpu_class_is_omap2())
590 case OMAP_DMA_DATA_BURST_8:
591 if (cpu_class_is_omap2())
596 case OMAP_DMA_DATA_BURST_16:
597 if (cpu_class_is_omap2()) {
601 /* OMAP1 don't support burst 16
605 printk(KERN_ERR "Invalid DMA burst mode\n");
610 dma_write(l, CSDP(lch));
612 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
614 static inline void omap_enable_channel_irq(int lch)
619 if (cpu_class_is_omap1())
620 status = dma_read(CSR(lch));
621 else if (cpu_class_is_omap2())
622 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
624 /* Enable some nice interrupts. */
625 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
628 static void omap_disable_channel_irq(int lch)
630 if (cpu_class_is_omap2())
631 dma_write(0, CICR(lch));
634 void omap_enable_dma_irq(int lch, u16 bits)
636 dma_chan[lch].enabled_irqs |= bits;
638 EXPORT_SYMBOL(omap_enable_dma_irq);
640 void omap_disable_dma_irq(int lch, u16 bits)
642 dma_chan[lch].enabled_irqs &= ~bits;
644 EXPORT_SYMBOL(omap_disable_dma_irq);
646 static inline void enable_lnk(int lch)
650 l = dma_read(CLNK_CTRL(lch));
652 if (cpu_class_is_omap1())
655 /* Set the ENABLE_LNK bits */
656 if (dma_chan[lch].next_lch != -1)
657 l = dma_chan[lch].next_lch | (1 << 15);
659 #ifndef CONFIG_ARCH_OMAP1
660 if (cpu_class_is_omap2())
661 if (dma_chan[lch].next_linked_ch != -1)
662 l = dma_chan[lch].next_linked_ch | (1 << 15);
665 dma_write(l, CLNK_CTRL(lch));
668 static inline void disable_lnk(int lch)
672 l = dma_read(CLNK_CTRL(lch));
674 /* Disable interrupts */
675 if (cpu_class_is_omap1()) {
676 dma_write(0, CICR(lch));
677 /* Set the STOP_LNK bit */
681 if (cpu_class_is_omap2()) {
682 omap_disable_channel_irq(lch);
683 /* Clear the ENABLE_LNK bit */
687 dma_write(l, CLNK_CTRL(lch));
688 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
691 static inline void omap2_enable_irq_lch(int lch)
695 if (!cpu_class_is_omap2())
698 val = dma_read(IRQENABLE_L0);
700 dma_write(val, IRQENABLE_L0);
703 int omap_request_dma(int dev_id, const char *dev_name,
704 void (*callback)(int lch, u16 ch_status, void *data),
705 void *data, int *dma_ch_out)
707 int ch, free_ch = -1;
709 struct omap_dma_lch *chan;
711 spin_lock_irqsave(&dma_chan_lock, flags);
712 for (ch = 0; ch < dma_chan_count; ch++) {
713 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
720 spin_unlock_irqrestore(&dma_chan_lock, flags);
723 chan = dma_chan + free_ch;
724 chan->dev_id = dev_id;
726 if (cpu_class_is_omap1())
727 clear_lch_regs(free_ch);
729 if (cpu_class_is_omap2())
730 omap_clear_dma(free_ch);
732 spin_unlock_irqrestore(&dma_chan_lock, flags);
734 chan->dev_name = dev_name;
735 chan->callback = callback;
739 #ifndef CONFIG_ARCH_OMAP1
740 if (cpu_class_is_omap2()) {
742 chan->next_linked_ch = -1;
746 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
748 if (cpu_class_is_omap1())
749 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
750 else if (cpu_class_is_omap2())
751 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
752 OMAP2_DMA_TRANS_ERR_IRQ;
754 if (cpu_is_omap16xx()) {
755 /* If the sync device is set, configure it dynamically. */
757 set_gdma_dev(free_ch + 1, dev_id);
758 dev_id = free_ch + 1;
761 * Disable the 1510 compatibility mode and set the sync device
764 dma_write(dev_id | (1 << 10), CCR(free_ch));
765 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
766 dma_write(dev_id, CCR(free_ch));
769 if (cpu_class_is_omap2()) {
770 omap2_enable_irq_lch(free_ch);
771 omap_enable_channel_irq(free_ch);
772 /* Clear the CSR register and IRQ status register */
773 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
774 dma_write(1 << free_ch, IRQSTATUS_L0);
777 *dma_ch_out = free_ch;
781 EXPORT_SYMBOL(omap_request_dma);
783 void omap_free_dma(int lch)
787 if (dma_chan[lch].dev_id == -1) {
788 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
793 if (cpu_class_is_omap1()) {
794 /* Disable all DMA interrupts for the channel. */
795 dma_write(0, CICR(lch));
796 /* Make sure the DMA transfer is stopped. */
797 dma_write(0, CCR(lch));
800 if (cpu_class_is_omap2()) {
802 /* Disable interrupts */
803 val = dma_read(IRQENABLE_L0);
805 dma_write(val, IRQENABLE_L0);
807 /* Clear the CSR register and IRQ status register */
808 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
809 dma_write(1 << lch, IRQSTATUS_L0);
811 /* Disable all DMA interrupts for the channel. */
812 dma_write(0, CICR(lch));
814 /* Make sure the DMA transfer is stopped. */
815 dma_write(0, CCR(lch));
819 spin_lock_irqsave(&dma_chan_lock, flags);
820 dma_chan[lch].dev_id = -1;
821 dma_chan[lch].next_lch = -1;
822 dma_chan[lch].callback = NULL;
823 spin_unlock_irqrestore(&dma_chan_lock, flags);
825 EXPORT_SYMBOL(omap_free_dma);
828 * @brief omap_dma_set_global_params : Set global priority settings for dma
831 * @param max_fifo_depth
832 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
833 * DMA_THREAD_RESERVE_ONET
834 * DMA_THREAD_RESERVE_TWOT
835 * DMA_THREAD_RESERVE_THREET
838 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
842 if (!cpu_class_is_omap2()) {
843 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
847 if (max_fifo_depth == 0)
852 reg = 0xff & max_fifo_depth;
853 reg |= (0x3 & tparams) << 12;
854 reg |= (arb_rate & 0xff) << 16;
858 EXPORT_SYMBOL(omap_dma_set_global_params);
861 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
864 * @param read_prio - Read priority
865 * @param write_prio - Write priority
866 * Both of the above can be set with one of the following values :
867 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
870 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
871 unsigned char write_prio)
875 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
876 printk(KERN_ERR "Invalid channel id\n");
879 l = dma_read(CCR(lch));
880 l &= ~((1 << 6) | (1 << 26));
881 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
882 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
884 l |= ((read_prio & 0x1) << 6);
886 dma_write(l, CCR(lch));
890 EXPORT_SYMBOL(omap_dma_set_prio_lch);
893 * Clears any DMA state so the DMA engine is ready to restart with new buffers
894 * through omap_start_dma(). Any buffers in flight are discarded.
896 void omap_clear_dma(int lch)
900 local_irq_save(flags);
902 if (cpu_class_is_omap1()) {
905 l = dma_read(CCR(lch));
906 l &= ~OMAP_DMA_CCR_EN;
907 dma_write(l, CCR(lch));
909 /* Clear pending interrupts */
910 l = dma_read(CSR(lch));
913 if (cpu_class_is_omap2()) {
915 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
916 for (i = 0; i < 0x44; i += 4)
917 __raw_writel(0, lch_base + i);
920 local_irq_restore(flags);
922 EXPORT_SYMBOL(omap_clear_dma);
924 void omap_start_dma(int lch)
928 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
929 int next_lch, cur_lch;
930 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
932 dma_chan_link_map[lch] = 1;
933 /* Set the link register of the first channel */
936 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
937 cur_lch = dma_chan[lch].next_lch;
939 next_lch = dma_chan[cur_lch].next_lch;
941 /* The loop case: we've been here already */
942 if (dma_chan_link_map[cur_lch])
944 /* Mark the current channel */
945 dma_chan_link_map[cur_lch] = 1;
948 omap_enable_channel_irq(cur_lch);
951 } while (next_lch != -1);
952 } else if (cpu_is_omap242x() ||
953 (cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) {
955 /* Errata: Need to write lch even if not using chaining */
956 dma_write(lch, CLNK_CTRL(lch));
959 omap_enable_channel_irq(lch);
961 l = dma_read(CCR(lch));
964 * Errata: On ES2.0 BUFFERING disable must be set.
965 * This will always fail on ES1.0
967 if (cpu_is_omap24xx())
968 l |= OMAP_DMA_CCR_EN;
970 l |= OMAP_DMA_CCR_EN;
971 dma_write(l, CCR(lch));
973 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
975 EXPORT_SYMBOL(omap_start_dma);
977 void omap_stop_dma(int lch)
981 /* Disable all interrupts on the channel */
982 if (cpu_class_is_omap1())
983 dma_write(0, CICR(lch));
985 l = dma_read(CCR(lch));
986 l &= ~OMAP_DMA_CCR_EN;
987 dma_write(l, CCR(lch));
989 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
990 int next_lch, cur_lch = lch;
991 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
993 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
995 /* The loop case: we've been here already */
996 if (dma_chan_link_map[cur_lch])
998 /* Mark the current channel */
999 dma_chan_link_map[cur_lch] = 1;
1001 disable_lnk(cur_lch);
1003 next_lch = dma_chan[cur_lch].next_lch;
1005 } while (next_lch != -1);
1008 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1010 EXPORT_SYMBOL(omap_stop_dma);
1013 * Allows changing the DMA callback function or data. This may be needed if
1014 * the driver shares a single DMA channel for multiple dma triggers.
1016 int omap_set_dma_callback(int lch,
1017 void (*callback)(int lch, u16 ch_status, void *data),
1020 unsigned long flags;
1025 spin_lock_irqsave(&dma_chan_lock, flags);
1026 if (dma_chan[lch].dev_id == -1) {
1027 printk(KERN_ERR "DMA callback for not set for free channel\n");
1028 spin_unlock_irqrestore(&dma_chan_lock, flags);
1031 dma_chan[lch].callback = callback;
1032 dma_chan[lch].data = data;
1033 spin_unlock_irqrestore(&dma_chan_lock, flags);
1037 EXPORT_SYMBOL(omap_set_dma_callback);
1040 * Returns current physical source address for the given DMA channel.
1041 * If the channel is running the caller must disable interrupts prior calling
1042 * this function and process the returned value before re-enabling interrupt to
1043 * prevent races with the interrupt handler. Note that in continuous mode there
1044 * is a chance for CSSA_L register overflow inbetween the two reads resulting
1045 * in incorrect return value.
1047 dma_addr_t omap_get_dma_src_pos(int lch)
1049 dma_addr_t offset = 0;
1051 if (cpu_is_omap15xx())
1052 offset = dma_read(CPC(lch));
1054 offset = dma_read(CSAC(lch));
1057 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1058 * read before the DMA controller finished disabling the channel.
1060 if (!cpu_is_omap15xx() && offset == 0)
1061 offset = dma_read(CSAC(lch));
1063 if (cpu_class_is_omap1())
1064 offset |= (dma_read(CSSA_U(lch)) << 16);
1068 EXPORT_SYMBOL(omap_get_dma_src_pos);
1071 * Returns current physical destination address for the given DMA channel.
1072 * If the channel is running the caller must disable interrupts prior calling
1073 * this function and process the returned value before re-enabling interrupt to
1074 * prevent races with the interrupt handler. Note that in continuous mode there
1075 * is a chance for CDSA_L register overflow inbetween the two reads resulting
1076 * in incorrect return value.
1078 dma_addr_t omap_get_dma_dst_pos(int lch)
1080 dma_addr_t offset = 0;
1082 if (cpu_is_omap15xx())
1083 offset = dma_read(CPC(lch));
1085 offset = dma_read(CDAC(lch));
1088 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1089 * read before the DMA controller finished disabling the channel.
1091 if (!cpu_is_omap15xx() && offset == 0)
1092 offset = dma_read(CDAC(lch));
1094 if (cpu_class_is_omap1())
1095 offset |= (dma_read(CDSA_U(lch)) << 16);
1099 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1101 int omap_get_dma_active_status(int lch)
1103 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1105 EXPORT_SYMBOL(omap_get_dma_active_status);
1107 int omap_dma_running(void)
1111 /* Check if LCD DMA is running */
1112 if (cpu_is_omap16xx())
1113 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1116 for (lch = 0; lch < dma_chan_count; lch++)
1117 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1124 * lch_queue DMA will start right after lch_head one is finished.
1125 * For this DMA link to start, you still need to start (see omap_start_dma)
1126 * the first one. That will fire up the entire queue.
1128 void omap_dma_link_lch(int lch_head, int lch_queue)
1130 if (omap_dma_in_1510_mode()) {
1131 if (lch_head == lch_queue) {
1132 dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1136 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1141 if ((dma_chan[lch_head].dev_id == -1) ||
1142 (dma_chan[lch_queue].dev_id == -1)) {
1143 printk(KERN_ERR "omap_dma: trying to link "
1144 "non requested channels\n");
1148 dma_chan[lch_head].next_lch = lch_queue;
1150 EXPORT_SYMBOL(omap_dma_link_lch);
1153 * Once the DMA queue is stopped, we can destroy it.
1155 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1157 if (omap_dma_in_1510_mode()) {
1158 if (lch_head == lch_queue) {
1159 dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1163 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1168 if (dma_chan[lch_head].next_lch != lch_queue ||
1169 dma_chan[lch_head].next_lch == -1) {
1170 printk(KERN_ERR "omap_dma: trying to unlink "
1171 "non linked channels\n");
1175 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1176 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1177 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1178 "before unlinking\n");
1182 dma_chan[lch_head].next_lch = -1;
1184 EXPORT_SYMBOL(omap_dma_unlink_lch);
1186 /*----------------------------------------------------------------------------*/
1188 #ifndef CONFIG_ARCH_OMAP1
1189 /* Create chain of DMA channesls */
1190 static void create_dma_lch_chain(int lch_head, int lch_queue)
1194 /* Check if this is the first link in chain */
1195 if (dma_chan[lch_head].next_linked_ch == -1) {
1196 dma_chan[lch_head].next_linked_ch = lch_queue;
1197 dma_chan[lch_head].prev_linked_ch = lch_queue;
1198 dma_chan[lch_queue].next_linked_ch = lch_head;
1199 dma_chan[lch_queue].prev_linked_ch = lch_head;
1202 /* a link exists, link the new channel in circular chain */
1204 dma_chan[lch_queue].next_linked_ch =
1205 dma_chan[lch_head].next_linked_ch;
1206 dma_chan[lch_queue].prev_linked_ch = lch_head;
1207 dma_chan[lch_head].next_linked_ch = lch_queue;
1208 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1212 l = dma_read(CLNK_CTRL(lch_head));
1215 dma_write(l, CLNK_CTRL(lch_head));
1217 l = dma_read(CLNK_CTRL(lch_queue));
1219 l |= (dma_chan[lch_queue].next_linked_ch);
1220 dma_write(l, CLNK_CTRL(lch_queue));
1224 * @brief omap_request_dma_chain : Request a chain of DMA channels
1226 * @param dev_id - Device id using the dma channel
1227 * @param dev_name - Device name
1228 * @param callback - Call back function
1230 * @no_of_chans - Number of channels requested
1231 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1232 * OMAP_DMA_DYNAMIC_CHAIN
1233 * @params - Channel parameters
1235 * @return - Succes : 0
1236 * Failure: -EINVAL/-ENOMEM
1238 int omap_request_dma_chain(int dev_id, const char *dev_name,
1239 void (*callback) (int lch, u16 ch_status,
1241 int *chain_id, int no_of_chans, int chain_mode,
1242 struct omap_dma_channel_params params)
1247 /* Is the chain mode valid ? */
1248 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1249 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1250 printk(KERN_ERR "Invalid chain mode requested\n");
1254 if (unlikely((no_of_chans < 1
1255 || no_of_chans > dma_lch_count))) {
1256 printk(KERN_ERR "Invalid Number of channels requested\n");
1260 /* Allocate a queue to maintain the status of the channels
1262 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1263 if (channels == NULL) {
1264 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1268 /* request and reserve DMA channels for the chain */
1269 for (i = 0; i < no_of_chans; i++) {
1270 err = omap_request_dma(dev_id, dev_name,
1271 callback, NULL, &channels[i]);
1274 for (j = 0; j < i; j++)
1275 omap_free_dma(channels[j]);
1277 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1280 dma_chan[channels[i]].prev_linked_ch = -1;
1281 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1284 * Allowing client drivers to set common parameters now,
1285 * so that later only relevant (src_start, dest_start
1286 * and element count) can be set
1288 omap_set_dma_params(channels[i], ¶ms);
1291 *chain_id = channels[0];
1292 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1293 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1294 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1295 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1297 for (i = 0; i < no_of_chans; i++)
1298 dma_chan[channels[i]].chain_id = *chain_id;
1300 /* Reset the Queue pointers */
1301 OMAP_DMA_CHAIN_QINIT(*chain_id);
1303 /* Set up the chain */
1304 if (no_of_chans == 1)
1305 create_dma_lch_chain(channels[0], channels[0]);
1307 for (i = 0; i < (no_of_chans - 1); i++)
1308 create_dma_lch_chain(channels[i], channels[i + 1]);
1313 EXPORT_SYMBOL(omap_request_dma_chain);
1316 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1317 * params after setting it. Dont do this while dma is running!!
1319 * @param chain_id - Chained logical channel id.
1322 * @return - Success : 0
1325 int omap_modify_dma_chain_params(int chain_id,
1326 struct omap_dma_channel_params params)
1331 /* Check for input params */
1332 if (unlikely((chain_id < 0
1333 || chain_id >= dma_lch_count))) {
1334 printk(KERN_ERR "Invalid chain id\n");
1338 /* Check if the chain exists */
1339 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1340 printk(KERN_ERR "Chain doesn't exists\n");
1343 channels = dma_linked_lch[chain_id].linked_dmach_q;
1345 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1347 * Allowing client drivers to set common parameters now,
1348 * so that later only relevant (src_start, dest_start
1349 * and element count) can be set
1351 omap_set_dma_params(channels[i], ¶ms);
1356 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1359 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1363 * @return - Success : 0
1366 int omap_free_dma_chain(int chain_id)
1371 /* Check for input params */
1372 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1373 printk(KERN_ERR "Invalid chain id\n");
1377 /* Check if the chain exists */
1378 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1379 printk(KERN_ERR "Chain doesn't exists\n");
1383 channels = dma_linked_lch[chain_id].linked_dmach_q;
1384 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1385 dma_chan[channels[i]].next_linked_ch = -1;
1386 dma_chan[channels[i]].prev_linked_ch = -1;
1387 dma_chan[channels[i]].chain_id = -1;
1388 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1389 omap_free_dma(channels[i]);
1394 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1395 dma_linked_lch[chain_id].chain_mode = -1;
1396 dma_linked_lch[chain_id].chain_state = -1;
1400 EXPORT_SYMBOL(omap_free_dma_chain);
1403 * @brief omap_dma_chain_status - Check if the chain is in
1404 * active / inactive state.
1407 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1410 int omap_dma_chain_status(int chain_id)
1412 /* Check for input params */
1413 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1414 printk(KERN_ERR "Invalid chain id\n");
1418 /* Check if the chain exists */
1419 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1420 printk(KERN_ERR "Chain doesn't exists\n");
1423 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1424 dma_linked_lch[chain_id].q_count);
1426 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1427 return OMAP_DMA_CHAIN_INACTIVE;
1429 return OMAP_DMA_CHAIN_ACTIVE;
1431 EXPORT_SYMBOL(omap_dma_chain_status);
1434 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1435 * set the params and start the transfer.
1438 * @param src_start - buffer start address
1439 * @param dest_start - Dest address
1441 * @param frame_count
1442 * @param callbk_data - channel callback parameter data.
1444 * @return - Success : 0
1445 * Failure: -EINVAL/-EBUSY
1447 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1448 int elem_count, int frame_count, void *callbk_data)
1455 * if buffer size is less than 1 then there is
1456 * no use of starting the chain
1458 if (elem_count < 1) {
1459 printk(KERN_ERR "Invalid buffer size\n");
1463 /* Check for input params */
1464 if (unlikely((chain_id < 0
1465 || chain_id >= dma_lch_count))) {
1466 printk(KERN_ERR "Invalid chain id\n");
1470 /* Check if the chain exists */
1471 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1472 printk(KERN_ERR "Chain doesn't exist\n");
1476 /* Check if all the channels in chain are in use */
1477 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1480 /* Frame count may be negative in case of indexed transfers */
1481 channels = dma_linked_lch[chain_id].linked_dmach_q;
1483 /* Get a free channel */
1484 lch = channels[dma_linked_lch[chain_id].q_tail];
1486 /* Store the callback data */
1487 dma_chan[lch].data = callbk_data;
1489 /* Increment the q_tail */
1490 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1492 /* Set the params to the free channel */
1494 dma_write(src_start, CSSA(lch));
1495 if (dest_start != 0)
1496 dma_write(dest_start, CDSA(lch));
1498 /* Write the buffer size */
1499 dma_write(elem_count, CEN(lch));
1500 dma_write(frame_count, CFN(lch));
1503 * If the chain is dynamically linked,
1504 * then we may have to start the chain if its not active
1506 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1509 * In Dynamic chain, if the chain is not started,
1512 if (dma_linked_lch[chain_id].chain_state ==
1513 DMA_CHAIN_NOTSTARTED) {
1514 /* Enable the link in previous channel */
1515 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1517 enable_lnk(dma_chan[lch].prev_linked_ch);
1518 dma_chan[lch].state = DMA_CH_QUEUED;
1522 * Chain is already started, make sure its active,
1523 * if not then start the chain
1528 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1530 enable_lnk(dma_chan[lch].prev_linked_ch);
1531 dma_chan[lch].state = DMA_CH_QUEUED;
1533 if (0 == ((1 << 7) & dma_read(
1534 CCR(dma_chan[lch].prev_linked_ch)))) {
1535 disable_lnk(dma_chan[lch].
1537 pr_debug("\n prev ch is stopped\n");
1542 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1544 enable_lnk(dma_chan[lch].prev_linked_ch);
1545 dma_chan[lch].state = DMA_CH_QUEUED;
1548 omap_enable_channel_irq(lch);
1550 l = dma_read(CCR(lch));
1552 if ((0 == (l & (1 << 24))))
1556 if (start_dma == 1) {
1557 if (0 == (l & (1 << 7))) {
1559 dma_chan[lch].state = DMA_CH_STARTED;
1560 pr_debug("starting %d\n", lch);
1561 dma_write(l, CCR(lch));
1565 if (0 == (l & (1 << 7)))
1566 dma_write(l, CCR(lch));
1568 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1574 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1577 * @brief omap_start_dma_chain_transfers - Start the chain
1581 * @return - Success : 0
1582 * Failure : -EINVAL/-EBUSY
1584 int omap_start_dma_chain_transfers(int chain_id)
1589 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1590 printk(KERN_ERR "Invalid chain id\n");
1594 channels = dma_linked_lch[chain_id].linked_dmach_q;
1596 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1597 printk(KERN_ERR "Chain is already started\n");
1601 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1602 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1604 enable_lnk(channels[i]);
1605 omap_enable_channel_irq(channels[i]);
1608 omap_enable_channel_irq(channels[0]);
1611 l = dma_read(CCR(channels[0]));
1613 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1614 dma_chan[channels[0]].state = DMA_CH_STARTED;
1616 if ((0 == (l & (1 << 24))))
1620 dma_write(l, CCR(channels[0]));
1622 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1626 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1629 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1633 * @return - Success : 0
1636 int omap_stop_dma_chain_transfers(int chain_id)
1642 /* Check for input params */
1643 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1644 printk(KERN_ERR "Invalid chain id\n");
1648 /* Check if the chain exists */
1649 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1650 printk(KERN_ERR "Chain doesn't exists\n");
1653 channels = dma_linked_lch[chain_id].linked_dmach_q;
1657 * Special programming model needed to disable DMA before end of block
1659 sys_cf = dma_read(OCP_SYSCONFIG);
1661 /* Middle mode reg set no Standby */
1662 l &= ~((1 << 12)|(1 << 13));
1663 dma_write(l, OCP_SYSCONFIG);
1665 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1667 /* Stop the Channel transmission */
1668 l = dma_read(CCR(channels[i]));
1670 dma_write(l, CCR(channels[i]));
1672 /* Disable the link in all the channels */
1673 disable_lnk(channels[i]);
1674 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1677 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1679 /* Reset the Queue pointers */
1680 OMAP_DMA_CHAIN_QINIT(chain_id);
1682 /* Errata - put in the old value */
1683 dma_write(sys_cf, OCP_SYSCONFIG);
1687 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1689 /* Get the index of the ongoing DMA in chain */
1691 * @brief omap_get_dma_chain_index - Get the element and frame index
1692 * of the ongoing DMA in chain
1695 * @param ei - Element index
1696 * @param fi - Frame index
1698 * @return - Success : 0
1701 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1706 /* Check for input params */
1707 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1708 printk(KERN_ERR "Invalid chain id\n");
1712 /* Check if the chain exists */
1713 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1714 printk(KERN_ERR "Chain doesn't exists\n");
1720 channels = dma_linked_lch[chain_id].linked_dmach_q;
1722 /* Get the current channel */
1723 lch = channels[dma_linked_lch[chain_id].q_head];
1725 *ei = dma_read(CCEN(lch));
1726 *fi = dma_read(CCFN(lch));
1730 EXPORT_SYMBOL(omap_get_dma_chain_index);
1733 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1734 * ongoing DMA in chain
1738 * @return - Success : Destination position
1741 int omap_get_dma_chain_dst_pos(int chain_id)
1746 /* Check for input params */
1747 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1748 printk(KERN_ERR "Invalid chain id\n");
1752 /* Check if the chain exists */
1753 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1754 printk(KERN_ERR "Chain doesn't exists\n");
1758 channels = dma_linked_lch[chain_id].linked_dmach_q;
1760 /* Get the current channel */
1761 lch = channels[dma_linked_lch[chain_id].q_head];
1763 return dma_read(CDAC(lch));
1765 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1768 * @brief omap_get_dma_chain_src_pos - Get the source position
1769 * of the ongoing DMA in chain
1772 * @return - Success : Destination position
1775 int omap_get_dma_chain_src_pos(int chain_id)
1780 /* Check for input params */
1781 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1782 printk(KERN_ERR "Invalid chain id\n");
1786 /* Check if the chain exists */
1787 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1788 printk(KERN_ERR "Chain doesn't exists\n");
1792 channels = dma_linked_lch[chain_id].linked_dmach_q;
1794 /* Get the current channel */
1795 lch = channels[dma_linked_lch[chain_id].q_head];
1797 return dma_read(CSAC(lch));
1799 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1800 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1802 /*----------------------------------------------------------------------------*/
1804 #ifdef CONFIG_ARCH_OMAP1
1806 static int omap1_dma_handle_ch(int ch)
1810 if (enable_1510_mode && ch >= 6) {
1811 csr = dma_chan[ch].saved_csr;
1812 dma_chan[ch].saved_csr = 0;
1814 csr = dma_read(CSR(ch));
1815 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1816 dma_chan[ch + 6].saved_csr = csr >> 7;
1819 if ((csr & 0x3f) == 0)
1821 if (unlikely(dma_chan[ch].dev_id == -1)) {
1822 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1823 "%d (CSR %04x)\n", ch, csr);
1826 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1827 printk(KERN_WARNING "DMA timeout with device %d\n",
1828 dma_chan[ch].dev_id);
1829 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1830 printk(KERN_WARNING "DMA synchronization event drop occurred "
1831 "with device %d\n", dma_chan[ch].dev_id);
1832 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1833 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1834 if (likely(dma_chan[ch].callback != NULL))
1835 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1840 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1842 int ch = ((int) dev_id) - 1;
1846 int handled_now = 0;
1848 handled_now += omap1_dma_handle_ch(ch);
1849 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1850 handled_now += omap1_dma_handle_ch(ch + 6);
1853 handled += handled_now;
1856 return handled ? IRQ_HANDLED : IRQ_NONE;
1860 #define omap1_dma_irq_handler NULL
1863 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1864 defined(CONFIG_ARCH_OMAP4)
1866 static int omap2_dma_handle_ch(int ch)
1868 u32 status = dma_read(CSR(ch));
1871 if (printk_ratelimit())
1872 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1874 dma_write(1 << ch, IRQSTATUS_L0);
1877 if (unlikely(dma_chan[ch].dev_id == -1)) {
1878 if (printk_ratelimit())
1879 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1880 "channel %d\n", status, ch);
1883 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1885 "DMA synchronization event drop occurred with device "
1886 "%d\n", dma_chan[ch].dev_id);
1887 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1888 printk(KERN_INFO "DMA transaction error with device %d\n",
1889 dma_chan[ch].dev_id);
1890 if (cpu_class_is_omap2()) {
1891 /* Errata: sDMA Channel is not disabled
1892 * after a transaction error. So we explicitely
1893 * disable the channel
1897 ccr = dma_read(CCR(ch));
1898 ccr &= ~OMAP_DMA_CCR_EN;
1899 dma_write(ccr, CCR(ch));
1900 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1903 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1904 printk(KERN_INFO "DMA secure error with device %d\n",
1905 dma_chan[ch].dev_id);
1906 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1907 printk(KERN_INFO "DMA misaligned error with device %d\n",
1908 dma_chan[ch].dev_id);
1910 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1911 dma_write(1 << ch, IRQSTATUS_L0);
1913 /* If the ch is not chained then chain_id will be -1 */
1914 if (dma_chan[ch].chain_id != -1) {
1915 int chain_id = dma_chan[ch].chain_id;
1916 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1917 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1918 dma_chan[dma_chan[ch].next_linked_ch].state =
1920 if (dma_linked_lch[chain_id].chain_mode ==
1921 OMAP_DMA_DYNAMIC_CHAIN)
1924 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1925 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1927 status = dma_read(CSR(ch));
1930 dma_write(status, CSR(ch));
1932 if (likely(dma_chan[ch].callback != NULL))
1933 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1938 /* STATUS register count is from 1-32 while our is 0-31 */
1939 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1941 u32 val, enable_reg;
1944 val = dma_read(IRQSTATUS_L0);
1946 if (printk_ratelimit())
1947 printk(KERN_WARNING "Spurious DMA IRQ\n");
1950 enable_reg = dma_read(IRQENABLE_L0);
1951 val &= enable_reg; /* Dispatch only relevant interrupts */
1952 for (i = 0; i < dma_lch_count && val != 0; i++) {
1954 omap2_dma_handle_ch(i);
1961 static struct irqaction omap24xx_dma_irq = {
1963 .handler = omap2_dma_irq_handler,
1964 .flags = IRQF_DISABLED
1968 static struct irqaction omap24xx_dma_irq;
1971 /*----------------------------------------------------------------------------*/
1973 static struct lcd_dma_info {
1976 void (*callback)(u16 status, void *data);
1980 unsigned long addr, size;
1981 int rotate, data_type, xres, yres;
1987 int single_transfer;
1990 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1993 lcd_dma.addr = addr;
1994 lcd_dma.data_type = data_type;
1995 lcd_dma.xres = fb_xres;
1996 lcd_dma.yres = fb_yres;
1998 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
2000 void omap_set_lcd_dma_src_port(int port)
2002 lcd_dma.src_port = port;
2005 void omap_set_lcd_dma_ext_controller(int external)
2007 lcd_dma.ext_ctrl = external;
2009 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2011 void omap_set_lcd_dma_single_transfer(int single)
2013 lcd_dma.single_transfer = single;
2015 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2017 void omap_set_lcd_dma_b1_rotation(int rotate)
2019 if (omap_dma_in_1510_mode()) {
2020 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
2024 lcd_dma.rotate = rotate;
2026 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2028 void omap_set_lcd_dma_b1_mirror(int mirror)
2030 if (omap_dma_in_1510_mode()) {
2031 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
2034 lcd_dma.mirror = mirror;
2036 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2038 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2040 if (omap_dma_in_1510_mode()) {
2041 printk(KERN_ERR "DMA virtual resulotion is not supported "
2045 lcd_dma.vxres = vxres;
2047 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2049 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2051 if (omap_dma_in_1510_mode()) {
2052 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2055 lcd_dma.xscale = xscale;
2056 lcd_dma.yscale = yscale;
2058 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2060 static void set_b1_regs(void)
2062 unsigned long top, bottom;
2065 unsigned long en, fn;
2067 unsigned long vxres;
2068 unsigned int xscale, yscale;
2070 switch (lcd_dma.data_type) {
2071 case OMAP_DMA_DATA_TYPE_S8:
2074 case OMAP_DMA_DATA_TYPE_S16:
2077 case OMAP_DMA_DATA_TYPE_S32:
2085 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2086 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2087 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2088 BUG_ON(vxres < lcd_dma.xres);
2090 #define PIXADDR(x, y) (lcd_dma.addr + \
2091 ((y) * vxres * yscale + (x) * xscale) * es)
2092 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2094 switch (lcd_dma.rotate) {
2096 if (!lcd_dma.mirror) {
2097 top = PIXADDR(0, 0);
2098 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2099 /* 1510 DMA requires the bottom address to be 2 more
2100 * than the actual last memory access location. */
2101 if (omap_dma_in_1510_mode() &&
2102 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2104 ei = PIXSTEP(0, 0, 1, 0);
2105 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2107 top = PIXADDR(lcd_dma.xres - 1, 0);
2108 bottom = PIXADDR(0, lcd_dma.yres - 1);
2109 ei = PIXSTEP(1, 0, 0, 0);
2110 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2116 if (!lcd_dma.mirror) {
2117 top = PIXADDR(0, lcd_dma.yres - 1);
2118 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2119 ei = PIXSTEP(0, 1, 0, 0);
2120 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2122 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2123 bottom = PIXADDR(0, 0);
2124 ei = PIXSTEP(0, 1, 0, 0);
2125 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2131 if (!lcd_dma.mirror) {
2132 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2133 bottom = PIXADDR(0, 0);
2134 ei = PIXSTEP(1, 0, 0, 0);
2135 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2137 top = PIXADDR(0, lcd_dma.yres - 1);
2138 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2139 ei = PIXSTEP(0, 0, 1, 0);
2140 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2146 if (!lcd_dma.mirror) {
2147 top = PIXADDR(lcd_dma.xres - 1, 0);
2148 bottom = PIXADDR(0, lcd_dma.yres - 1);
2149 ei = PIXSTEP(0, 0, 0, 1);
2150 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2152 top = PIXADDR(0, 0);
2153 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2154 ei = PIXSTEP(0, 0, 0, 1);
2155 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2162 return; /* Suppress warning about uninitialized vars */
2165 if (omap_dma_in_1510_mode()) {
2166 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2167 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2168 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2169 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2175 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2176 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2177 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2178 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2180 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2181 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2183 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2185 w |= lcd_dma.data_type;
2186 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2188 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2189 /* Always set the source port as SDRAM for now*/
2191 if (lcd_dma.callback != NULL)
2192 w |= 1 << 1; /* Block interrupt enable */
2195 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2197 if (!(lcd_dma.rotate || lcd_dma.mirror ||
2198 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2201 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2202 /* Set the double-indexed addressing mode */
2204 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2206 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2207 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2208 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2211 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2215 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2216 if (unlikely(!(w & (1 << 3)))) {
2217 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2222 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2224 if (lcd_dma.callback != NULL)
2225 lcd_dma.callback(w, lcd_dma.cb_data);
2230 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2233 spin_lock_irq(&lcd_dma.lock);
2234 if (lcd_dma.reserved) {
2235 spin_unlock_irq(&lcd_dma.lock);
2236 printk(KERN_ERR "LCD DMA channel already reserved\n");
2240 lcd_dma.reserved = 1;
2241 spin_unlock_irq(&lcd_dma.lock);
2242 lcd_dma.callback = callback;
2243 lcd_dma.cb_data = data;
2245 lcd_dma.single_transfer = 0;
2251 lcd_dma.ext_ctrl = 0;
2252 lcd_dma.src_port = 0;
2256 EXPORT_SYMBOL(omap_request_lcd_dma);
2258 void omap_free_lcd_dma(void)
2260 spin_lock(&lcd_dma.lock);
2261 if (!lcd_dma.reserved) {
2262 spin_unlock(&lcd_dma.lock);
2263 printk(KERN_ERR "LCD DMA is not reserved\n");
2267 if (!enable_1510_mode)
2268 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2269 OMAP1610_DMA_LCD_CCR);
2270 lcd_dma.reserved = 0;
2271 spin_unlock(&lcd_dma.lock);
2273 EXPORT_SYMBOL(omap_free_lcd_dma);
2275 void omap_enable_lcd_dma(void)
2280 * Set the Enable bit only if an external controller is
2281 * connected. Otherwise the OMAP internal controller will
2282 * start the transfer when it gets enabled.
2284 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2287 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2289 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2293 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2295 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2297 EXPORT_SYMBOL(omap_enable_lcd_dma);
2299 void omap_setup_lcd_dma(void)
2301 BUG_ON(lcd_dma.active);
2302 if (!enable_1510_mode) {
2303 /* Set some reasonable defaults */
2304 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2305 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2306 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2309 if (!enable_1510_mode) {
2312 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2314 * If DMA was already active set the end_prog bit to have
2315 * the programmed register set loaded into the active
2318 w |= 1 << 11; /* End_prog */
2319 if (!lcd_dma.single_transfer)
2320 w |= (3 << 8); /* Auto_init, repeat */
2321 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2324 EXPORT_SYMBOL(omap_setup_lcd_dma);
2326 void omap_stop_lcd_dma(void)
2331 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2334 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2336 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2338 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2340 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2342 EXPORT_SYMBOL(omap_stop_lcd_dma);
2344 /*----------------------------------------------------------------------------*/
2346 static int __init omap_init_dma(void)
2350 if (cpu_class_is_omap1()) {
2351 omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE);
2352 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2353 } else if (cpu_is_omap24xx()) {
2354 omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE);
2355 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2356 } else if (cpu_is_omap34xx()) {
2357 omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE);
2358 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2359 } else if (cpu_is_omap44xx()) {
2360 omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE);
2361 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2363 pr_err("DMA init failed for unsupported omap\n");
2367 if (cpu_class_is_omap2() && omap_dma_reserve_channels
2368 && (omap_dma_reserve_channels <= dma_lch_count))
2369 dma_lch_count = omap_dma_reserve_channels;
2371 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2376 if (cpu_class_is_omap2()) {
2377 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2378 dma_lch_count, GFP_KERNEL);
2379 if (!dma_linked_lch) {
2385 if (cpu_is_omap15xx()) {
2386 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2388 enable_1510_mode = 1;
2389 } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2390 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2392 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2393 (dma_read(CAPS_0_U) << 16) |
2395 (dma_read(CAPS_1_U) << 16) |
2397 dma_read(CAPS_2), dma_read(CAPS_3),
2399 if (!enable_1510_mode) {
2402 /* Disable OMAP 3.0/3.1 compatibility mode. */
2406 dma_chan_count = 16;
2409 if (cpu_is_omap16xx()) {
2412 /* this would prevent OMAP sleep */
2413 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2415 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2417 } else if (cpu_class_is_omap2()) {
2418 u8 revision = dma_read(REVISION) & 0xff;
2419 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2420 revision >> 4, revision & 0xf);
2421 dma_chan_count = dma_lch_count;
2427 spin_lock_init(&lcd_dma.lock);
2428 spin_lock_init(&dma_chan_lock);
2430 for (ch = 0; ch < dma_chan_count; ch++) {
2432 dma_chan[ch].dev_id = -1;
2433 dma_chan[ch].next_lch = -1;
2435 if (ch >= 6 && enable_1510_mode)
2438 if (cpu_class_is_omap1()) {
2440 * request_irq() doesn't like dev_id (ie. ch) being
2441 * zero, so we have to kludge around this.
2443 r = request_irq(omap1_dma_irq[ch],
2444 omap1_dma_irq_handler, 0, "DMA",
2449 printk(KERN_ERR "unable to request IRQ %d "
2450 "for DMA (error %d)\n",
2451 omap1_dma_irq[ch], r);
2452 for (i = 0; i < ch; i++)
2453 free_irq(omap1_dma_irq[i],
2460 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2461 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2462 DMA_DEFAULT_FIFO_DEPTH, 0);
2464 if (cpu_class_is_omap2()) {
2466 if (cpu_is_omap44xx())
2467 irq = INT_44XX_SDMA_IRQ0;
2469 irq = INT_24XX_SDMA_IRQ0;
2470 setup_irq(irq, &omap24xx_dma_irq);
2473 /* Enable smartidle idlemodes and autoidle */
2474 if (cpu_is_omap34xx()) {
2475 u32 v = dma_read(OCP_SYSCONFIG);
2476 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2477 DMA_SYSCONFIG_SIDLEMODE_MASK |
2478 DMA_SYSCONFIG_AUTOIDLE);
2479 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2480 DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2481 DMA_SYSCONFIG_AUTOIDLE);
2482 dma_write(v , OCP_SYSCONFIG);
2486 /* FIXME: Update LCD DMA to work on 24xx */
2487 if (cpu_class_is_omap1()) {
2488 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2493 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2495 for (i = 0; i < dma_chan_count; i++)
2496 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2504 arch_initcall(omap_init_dma);
2507 * Reserve the omap SDMA channels using cmdline bootarg
2508 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2510 static int __init omap_dma_cmdline_reserve_ch(char *str)
2512 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2513 omap_dma_reserve_channels = 0;
2517 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);