1 #ifndef ____ASM_ARCH_SDRC_H
2 #define ____ASM_ARCH_SDRC_H
5 * OMAP2/3 SDRC/SMS register definitions
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
21 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
23 #define SDRC_SYSCONFIG 0x010
24 #define SDRC_DLLA_CTRL 0x060
25 #define SDRC_DLLA_STATUS 0x064
26 #define SDRC_DLLB_CTRL 0x068
27 #define SDRC_DLLB_STATUS 0x06C
28 #define SDRC_POWER 0x070
29 #define SDRC_MR_0 0x084
30 #define SDRC_ACTIM_CTRL_A_0 0x09c
31 #define SDRC_ACTIM_CTRL_B_0 0x0a0
32 #define SDRC_RFR_CTRL_0 0x0a4
35 * These values represent the number of memory clock cycles between
36 * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
37 * rows per device, and include a subtraction of a 50 cycle window in the
38 * event that the autorefresh command is delayed due to other SDRC activity.
39 * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
42 * These represent optimal values for common parts, it won't work for all.
43 * As long as you scale down, most parameters are still work, they just
44 * become sub-optimal. The RFR value goes in the opposite direction. If you
45 * don't adjust it down as your clock period increases the refresh interval
46 * will not be met. Setting all parameters for complete worst case may work,
47 * but may cut memory performance by 2x. Due to errata the DLLs need to be
48 * unlocked and their value needs run time calibration. A dynamic call is
49 * need for that as no single right value exists acorss production samples.
51 * Only the FULL speed values are given. Current code is such that rate
52 * changes must be made at DPLLoutx2. The actual value adjustment for low
53 * frequency operation will be handled by omap_set_performance()
55 * By having the boot loader boot up in the fastest L4 speed available likely
56 * will result in something which you can switch between.
58 #define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
59 #define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
60 #define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
61 #define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
62 #define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
69 #define OMAP242X_SMS_REGADDR(reg) \
70 (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
71 #define OMAP243X_SMS_REGADDR(reg) \
72 (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
73 #define OMAP343X_SMS_REGADDR(reg) \
74 (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
76 /* SMS register offsets - read/write with sms_{read,write}_reg() */
78 #define SMS_SYSCONFIG 0x010
79 /* REVISIT: fill in other SMS registers here */
84 void __init omap2_sdrc_init(void);
86 #ifdef CONFIG_ARCH_OMAP2
88 struct memory_timings {
89 u32 m_type; /* ddr = 1, sdr = 0 */
90 u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
91 u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
92 u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
93 u32 base_cs; /* base chip select to use for calculations */
96 extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
98 u32 omap2xxx_sdrc_dll_is_unlocked(void);
99 u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
101 #endif /* CONFIG_ARCH_OMAP2 */
103 #endif /* __ASSEMBLER__ */