arch/arm/plat-omap/include/plat/display.h

   1 /*
   2  * linux/include/asm-arm/arch-omap/display.h
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef __ASM_ARCH_OMAP_DISPLAY_H
  21 #define __ASM_ARCH_OMAP_DISPLAY_H
  22
  23 #include <linux/list.h>
  24 #include <linux/kobject.h>
  25 #include <linux/device.h>
  26 #include <asm/atomic.h>
  27
  28 #define DISPC_IRQ_FRAMEDONE             (1 << 0)
  29 #define DISPC_IRQ_VSYNC                 (1 << 1)
  30 #define DISPC_IRQ_EVSYNC_EVEN           (1 << 2)
  31 #define DISPC_IRQ_EVSYNC_ODD            (1 << 3)
  32 #define DISPC_IRQ_ACBIAS_COUNT_STAT     (1 << 4)
  33 #define DISPC_IRQ_PROG_LINE_NUM         (1 << 5)
  34 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
  35 #define DISPC_IRQ_GFX_END_WIN           (1 << 7)
  36 #define DISPC_IRQ_PAL_GAMMA_MASK        (1 << 8)
  37 #define DISPC_IRQ_OCP_ERR               (1 << 9)
  38 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
  39 #define DISPC_IRQ_VID1_END_WIN          (1 << 11)
  40 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
  41 #define DISPC_IRQ_VID2_END_WIN          (1 << 13)
  42 #define DISPC_IRQ_SYNC_LOST             (1 << 14)
  43 #define DISPC_IRQ_SYNC_LOST_DIGIT       (1 << 15)
  44 #define DISPC_IRQ_WAKEUP                (1 << 16)
  45
  46 struct omap_dss_device;
  47 struct omap_overlay_manager;
  48
  49 enum omap_display_type {
  50         OMAP_DISPLAY_TYPE_NONE          = 0,
  51         OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
  52         OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
  53         OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
  54         OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
  55         OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
  56 };
  57
  58 enum omap_plane {
  59         OMAP_DSS_GFX    = 0,
  60         OMAP_DSS_VIDEO1 = 1,
  61         OMAP_DSS_VIDEO2 = 2
  62 };
  63
  64 enum omap_channel {
  65         OMAP_DSS_CHANNEL_LCD    = 0,
  66         OMAP_DSS_CHANNEL_DIGIT  = 1,
  67 };
  68
  69 enum omap_color_mode {
  70         OMAP_DSS_COLOR_CLUT1    = 1 << 0,  /* BITMAP 1 */
  71         OMAP_DSS_COLOR_CLUT2    = 1 << 1,  /* BITMAP 2 */
  72         OMAP_DSS_COLOR_CLUT4    = 1 << 2,  /* BITMAP 4 */
  73         OMAP_DSS_COLOR_CLUT8    = 1 << 3,  /* BITMAP 8 */
  74         OMAP_DSS_COLOR_RGB12U   = 1 << 4,  /* RGB12, 16-bit container */
  75         OMAP_DSS_COLOR_ARGB16   = 1 << 5,  /* ARGB16 */
  76         OMAP_DSS_COLOR_RGB16    = 1 << 6,  /* RGB16 */
  77         OMAP_DSS_COLOR_RGB24U   = 1 << 7,  /* RGB24, 32-bit container */
  78         OMAP_DSS_COLOR_RGB24P   = 1 << 8,  /* RGB24, 24-bit container */
  79         OMAP_DSS_COLOR_YUV2     = 1 << 9,  /* YUV2 4:2:2 co-sited */
  80         OMAP_DSS_COLOR_UYVY     = 1 << 10, /* UYVY 4:2:2 co-sited */
  81         OMAP_DSS_COLOR_ARGB32   = 1 << 11, /* ARGB32 */
  82         OMAP_DSS_COLOR_RGBA32   = 1 << 12, /* RGBA32 */
  83         OMAP_DSS_COLOR_RGBX32   = 1 << 13, /* RGBx32 */
  84
  85         OMAP_DSS_COLOR_GFX_OMAP2 =
  86                 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
  87                 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
  88                 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
  89                 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
  90
  91         OMAP_DSS_COLOR_VID_OMAP2 =
  92                 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
  93                 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
  94                 OMAP_DSS_COLOR_UYVY,
  95
  96         OMAP_DSS_COLOR_GFX_OMAP3 =
  97                 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
  98                 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
  99                 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
 100                 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
 101                 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
 102                 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
 103
 104         OMAP_DSS_COLOR_VID1_OMAP3 =
 105                 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
 106                 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
 107                 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
 108
 109         OMAP_DSS_COLOR_VID2_OMAP3 =
 110                 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
 111                 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
 112                 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
 113                 OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
 114                 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
 115 };
 116
 117 enum omap_lcd_display_type {
 118         OMAP_DSS_LCD_DISPLAY_STN,
 119         OMAP_DSS_LCD_DISPLAY_TFT,
 120 };
 121
 122 enum omap_dss_load_mode {
 123         OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
 124         OMAP_DSS_LOAD_CLUT_ONLY         = 1,
 125         OMAP_DSS_LOAD_FRAME_ONLY        = 2,
 126         OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
 127 };
 128
 129 enum omap_dss_trans_key_type {
 130         OMAP_DSS_COLOR_KEY_GFX_DST = 0,
 131         OMAP_DSS_COLOR_KEY_VID_SRC = 1,
 132 };
 133
 134 enum omap_rfbi_te_mode {
 135         OMAP_DSS_RFBI_TE_MODE_1 = 1,
 136         OMAP_DSS_RFBI_TE_MODE_2 = 2,
 137 };
 138
 139 enum omap_panel_config {
 140         OMAP_DSS_LCD_IVS                = 1<<0,
 141         OMAP_DSS_LCD_IHS                = 1<<1,
 142         OMAP_DSS_LCD_IPC                = 1<<2,
 143         OMAP_DSS_LCD_IEO                = 1<<3,
 144         OMAP_DSS_LCD_RF                 = 1<<4,
 145         OMAP_DSS_LCD_ONOFF              = 1<<5,
 146
 147         OMAP_DSS_LCD_TFT                = 1<<20,
 148 };
 149
 150 enum omap_dss_venc_type {
 151         OMAP_DSS_VENC_TYPE_COMPOSITE,
 152         OMAP_DSS_VENC_TYPE_SVIDEO,
 153 };
 154
 155 enum omap_display_caps {
 156         OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE      = 1 << 0,
 157         OMAP_DSS_DISPLAY_CAP_TEAR_ELIM          = 1 << 1,
 158 };
 159
 160 enum omap_dss_update_mode {
 161         OMAP_DSS_UPDATE_DISABLED = 0,
 162         OMAP_DSS_UPDATE_AUTO,
 163         OMAP_DSS_UPDATE_MANUAL,
 164 };
 165
 166 enum omap_dss_display_state {
 167         OMAP_DSS_DISPLAY_DISABLED = 0,
 168         OMAP_DSS_DISPLAY_ACTIVE,
 169         OMAP_DSS_DISPLAY_SUSPENDED,
 170 };
 171
 172 /* XXX perhaps this should be removed */
 173 enum omap_dss_overlay_managers {
 174         OMAP_DSS_OVL_MGR_LCD,
 175         OMAP_DSS_OVL_MGR_TV,
 176 };
 177
 178 enum omap_dss_rotation_type {
 179         OMAP_DSS_ROT_DMA = 0,
 180         OMAP_DSS_ROT_VRFB = 1,
 181 };
 182
 183 /* clockwise rotation angle */
 184 enum omap_dss_rotation_angle {
 185         OMAP_DSS_ROT_0   = 0,
 186         OMAP_DSS_ROT_90  = 1,
 187         OMAP_DSS_ROT_180 = 2,
 188         OMAP_DSS_ROT_270 = 3,
 189 };
 190
 191 enum omap_overlay_caps {
 192         OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
 193         OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
 194 };
 195
 196 enum omap_overlay_manager_caps {
 197         OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
 198 };
 199
 200 /* RFBI */
 201
 202 struct rfbi_timings {
 203         int cs_on_time;
 204         int cs_off_time;
 205         int we_on_time;
 206         int we_off_time;
 207         int re_on_time;
 208         int re_off_time;
 209         int we_cycle_time;
 210         int re_cycle_time;
 211         int cs_pulse_width;
 212         int access_time;
 213
 214         int clk_div;
 215
 216         u32 tim[5];             /* set by rfbi_convert_timings() */
 217
 218         int converted;
 219 };
 220
 221 void omap_rfbi_write_command(const void *buf, u32 len);
 222 void omap_rfbi_read_data(void *buf, u32 len);
 223 void omap_rfbi_write_data(const void *buf, u32 len);
 224 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
 225                 u16 x, u16 y,
 226                 u16 w, u16 h);
 227 int omap_rfbi_enable_te(bool enable, unsigned line);
 228 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
 229                              unsigned hs_pulse_time, unsigned vs_pulse_time,
 230                              int hs_pol_inv, int vs_pol_inv, int extif_div);
 231
 232 /* DSI */
 233 void dsi_bus_lock(void);
 234 void dsi_bus_unlock(void);
 235 int dsi_vc_dcs_write(int channel, u8 *data, int len);
 236 int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd);
 237 int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param);
 238 int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
 239 int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
 240 int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data);
 241 int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
 242 int dsi_vc_send_null(int channel);
 243 int dsi_vc_send_bta_sync(int channel);
 244
 245 /* Board specific data */
 246 struct omap_dss_board_info {
 247         int (*get_last_off_on_transaction_id)(struct device *dev);
 248         int num_devices;
 249         struct omap_dss_device **devices;
 250         struct omap_dss_device *default_device;
 251 };
 252
 253 struct omap_video_timings {
 254         /* Unit: pixels */
 255         u16 x_res;
 256         /* Unit: pixels */
 257         u16 y_res;
 258         /* Unit: KHz */
 259         u32 pixel_clock;
 260         /* Unit: pixel clocks */
 261         u16 hsw;        /* Horizontal synchronization pulse width */
 262         /* Unit: pixel clocks */
 263         u16 hfp;        /* Horizontal front porch */
 264         /* Unit: pixel clocks */
 265         u16 hbp;        /* Horizontal back porch */
 266         /* Unit: line clocks */
 267         u16 vsw;        /* Vertical synchronization pulse width */
 268         /* Unit: line clocks */
 269         u16 vfp;        /* Vertical front porch */
 270         /* Unit: line clocks */
 271         u16 vbp;        /* Vertical back porch */
 272 };
 273
 274 #ifdef CONFIG_OMAP2_DSS_VENC
 275 /* Hardcoded timings for tv modes. Venc only uses these to
 276  * identify the mode, and does not actually use the configs
 277  * itself. However, the configs should be something that
 278  * a normal monitor can also show */
 279 const extern struct omap_video_timings omap_dss_pal_timings;
 280 const extern struct omap_video_timings omap_dss_ntsc_timings;
 281 #endif
 282
 283 struct omap_overlay_info {
 284         bool enabled;
 285
 286         u32 paddr;
 287         void __iomem *vaddr;
 288         u16 screen_width;
 289         u16 width;
 290         u16 height;
 291         enum omap_color_mode color_mode;
 292         u8 rotation;
 293         enum omap_dss_rotation_type rotation_type;
 294         bool mirror;
 295
 296         u16 pos_x;
 297         u16 pos_y;
 298         u16 out_width;  /* if 0, out_width == width */
 299         u16 out_height; /* if 0, out_height == height */
 300         u8 global_alpha;
 301 };
 302
 303 struct omap_overlay {
 304         struct kobject kobj;
 305         struct list_head list;
 306
 307         /* static fields */
 308         const char *name;
 309         int id;
 310         enum omap_color_mode supported_modes;
 311         enum omap_overlay_caps caps;
 312
 313         /* dynamic fields */
 314         struct omap_overlay_manager *manager;
 315         struct omap_overlay_info info;
 316
 317         /* if true, info has been changed, but not applied() yet */
 318         bool info_dirty;
 319
 320         int (*set_manager)(struct omap_overlay *ovl,
 321                 struct omap_overlay_manager *mgr);
 322         int (*unset_manager)(struct omap_overlay *ovl);
 323
 324         int (*set_overlay_info)(struct omap_overlay *ovl,
 325                         struct omap_overlay_info *info);
 326         void (*get_overlay_info)(struct omap_overlay *ovl,
 327                         struct omap_overlay_info *info);
 328
 329         int (*wait_for_go)(struct omap_overlay *ovl);
 330 };
 331
 332 struct omap_overlay_manager_info {
 333         u32 default_color;
 334
 335         enum omap_dss_trans_key_type trans_key_type;
 336         u32 trans_key;
 337         bool trans_enabled;
 338
 339         bool alpha_enabled;
 340 };
 341
 342 struct omap_overlay_manager {
 343         struct kobject kobj;
 344         struct list_head list;
 345
 346         /* static fields */
 347         const char *name;
 348         int id;
 349         enum omap_overlay_manager_caps caps;
 350         int num_overlays;
 351         struct omap_overlay **overlays;
 352         enum omap_display_type supported_displays;
 353
 354         /* dynamic fields */
 355         struct omap_dss_device *device;
 356         struct omap_overlay_manager_info info;
 357
 358         bool device_changed;
 359         /* if true, info has been changed but not applied() yet */
 360         bool info_dirty;
 361
 362         int (*set_device)(struct omap_overlay_manager *mgr,
 363                 struct omap_dss_device *dssdev);
 364         int (*unset_device)(struct omap_overlay_manager *mgr);
 365
 366         int (*set_manager_info)(struct omap_overlay_manager *mgr,
 367                         struct omap_overlay_manager_info *info);
 368         void (*get_manager_info)(struct omap_overlay_manager *mgr,
 369                         struct omap_overlay_manager_info *info);
 370
 371         int (*apply)(struct omap_overlay_manager *mgr);
 372         int (*wait_for_go)(struct omap_overlay_manager *mgr);
 373 };
 374
 375 struct omap_dss_device {
 376         struct device dev;
 377
 378         enum omap_display_type type;
 379
 380         union {
 381                 struct {
 382                         u8 data_lines;
 383                 } dpi;
 384
 385                 struct {
 386                         u8 channel;
 387                         u8 data_lines;
 388                 } rfbi;
 389
 390                 struct {
 391                         u8 datapairs;
 392                 } sdi;
 393
 394                 struct {
 395                         u8 clk_lane;
 396                         u8 clk_pol;
 397                         u8 data1_lane;
 398                         u8 data1_pol;
 399                         u8 data2_lane;
 400                         u8 data2_pol;
 401
 402                         struct {
 403                                 u16 regn;
 404                                 u16 regm;
 405                                 u16 regm3;
 406                                 u16 regm4;
 407
 408                                 u16 lp_clk_div;
 409
 410                                 u16 lck_div;
 411                                 u16 pck_div;
 412                         } div;
 413
 414                         bool ext_te;
 415                         u8 ext_te_gpio;
 416                 } dsi;
 417
 418                 struct {
 419                         enum omap_dss_venc_type type;
 420                         bool invert_polarity;
 421                 } venc;
 422         } phy;
 423
 424         struct {
 425                 struct omap_video_timings timings;
 426
 427                 int acbi;       /* ac-bias pin transitions per interrupt */
 428                 /* Unit: line clocks */
 429                 int acb;        /* ac-bias pin frequency */
 430
 431                 enum omap_panel_config config;
 432
 433                 u8 recommended_bpp;
 434         } panel;
 435
 436         struct {
 437                 u8 pixel_size;
 438                 struct rfbi_timings rfbi_timings;
 439         } ctrl;
 440
 441         int reset_gpio;
 442
 443         int max_backlight_level;
 444
 445         const char *name;
 446
 447         /* used to match device to driver */
 448         const char *driver_name;
 449
 450         void *data;
 451
 452         struct omap_dss_driver *driver;
 453
 454         /* helper variable for driver suspend/resume */
 455         bool activate_after_resume;
 456
 457         enum omap_display_caps caps;
 458
 459         struct omap_overlay_manager *manager;
 460
 461         enum omap_dss_display_state state;
 462
 463         int (*enable)(struct omap_dss_device *dssdev);
 464         void (*disable)(struct omap_dss_device *dssdev);
 465
 466         int (*suspend)(struct omap_dss_device *dssdev);
 467         int (*resume)(struct omap_dss_device *dssdev);
 468
 469         void (*get_resolution)(struct omap_dss_device *dssdev,
 470                         u16 *xres, u16 *yres);
 471         int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
 472
 473         int (*check_timings)(struct omap_dss_device *dssdev,
 474                         struct omap_video_timings *timings);
 475         void (*set_timings)(struct omap_dss_device *dssdev,
 476                         struct omap_video_timings *timings);
 477         void (*get_timings)(struct omap_dss_device *dssdev,
 478                         struct omap_video_timings *timings);
 479         int (*update)(struct omap_dss_device *dssdev,
 480                                u16 x, u16 y, u16 w, u16 h);
 481         int (*sync)(struct omap_dss_device *dssdev);
 482         int (*wait_vsync)(struct omap_dss_device *dssdev);
 483
 484         int (*set_update_mode)(struct omap_dss_device *dssdev,
 485                         enum omap_dss_update_mode);
 486         enum omap_dss_update_mode (*get_update_mode)
 487                 (struct omap_dss_device *dssdev);
 488
 489         int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
 490         int (*get_te)(struct omap_dss_device *dssdev);
 491
 492         u8 (*get_rotate)(struct omap_dss_device *dssdev);
 493         int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
 494
 495         bool (*get_mirror)(struct omap_dss_device *dssdev);
 496         int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
 497
 498         int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
 499         u32 (*get_wss)(struct omap_dss_device *dssdev);
 500
 501         /* platform specific  */
 502         int (*platform_enable)(struct omap_dss_device *dssdev);
 503         void (*platform_disable)(struct omap_dss_device *dssdev);
 504         int (*set_backlight)(struct omap_dss_device *dssdev, int level);
 505         int (*get_backlight)(struct omap_dss_device *dssdev);
 506 };
 507
 508 struct omap_dss_driver {
 509         struct device_driver driver;
 510
 511         int (*probe)(struct omap_dss_device *);
 512         void (*remove)(struct omap_dss_device *);
 513
 514         int (*enable)(struct omap_dss_device *display);
 515         void (*disable)(struct omap_dss_device *display);
 516         int (*suspend)(struct omap_dss_device *display);
 517         int (*resume)(struct omap_dss_device *display);
 518         int (*run_test)(struct omap_dss_device *display, int test);
 519
 520         void (*setup_update)(struct omap_dss_device *dssdev,
 521                         u16 x, u16 y, u16 w, u16 h);
 522
 523         int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
 524         int (*wait_for_te)(struct omap_dss_device *dssdev);
 525
 526         u8 (*get_rotate)(struct omap_dss_device *dssdev);
 527         int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
 528
 529         bool (*get_mirror)(struct omap_dss_device *dssdev);
 530         int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
 531
 532         int (*memory_read)(struct omap_dss_device *dssdev,
 533                         void *buf, size_t size,
 534                         u16 x, u16 y, u16 w, u16 h);
 535 };
 536
 537 int omap_dss_register_driver(struct omap_dss_driver *);
 538 void omap_dss_unregister_driver(struct omap_dss_driver *);
 539
 540 int omap_dss_register_device(struct omap_dss_device *);
 541 void omap_dss_unregister_device(struct omap_dss_device *);
 542
 543 void omap_dss_get_device(struct omap_dss_device *dssdev);
 544 void omap_dss_put_device(struct omap_dss_device *dssdev);
 545 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
 546 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
 547 struct omap_dss_device *omap_dss_find_device(void *data,
 548                 int (*match)(struct omap_dss_device *dssdev, void *data));
 549
 550 int omap_dss_start_device(struct omap_dss_device *dssdev);
 551 void omap_dss_stop_device(struct omap_dss_device *dssdev);
 552
 553 int omap_dss_get_num_overlay_managers(void);
 554 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
 555
 556 int omap_dss_get_num_overlays(void);
 557 struct omap_overlay *omap_dss_get_overlay(int num);
 558
 559 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
 560 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 561 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 562
 563 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
 564 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
 565                 unsigned long timeout);
 566
 567 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
 568 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
 569
 570 void omapdss_dsi_vc_enable_hs(int channel, bool enable);
 571
 572 #endif