2 * arch/arm/plat-omap/include/mach/io.h
4 * IO definitions for TI OMAP processors and boards
6 * Copied from arch/arm/mach-sa1100/include/mach/io.h
7 * Copyright (C) 1997-1999 Russell King
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 * 06-12-1997 RMK Created.
34 * 07-04-1999 RMK Major cleanup
37 #ifndef __ASM_ARM_ARCH_IO_H
38 #define __ASM_ARM_ARCH_IO_H
40 #include <mach/hardware.h>
42 #define IO_SPACE_LIMIT 0xffffffff
45 * We don't actually have real ISA nor PCI buses, but there is so many
46 * drivers out there that might just work if we fake them...
48 #define __io(a) __typesafe_io(a)
49 #define __mem_pci(a) (a)
52 * ----------------------------------------------------------------------------
54 * ----------------------------------------------------------------------------
60 #define IOMEM(x) ((void __force __iomem *)(x))
63 #define OMAP2_L3_IO_OFFSET 0x90000000
64 #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
67 #define OMAP2_L4_IO_OFFSET 0xb2000000
68 #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
70 #define OMAP4_L3_IO_OFFSET 0xb4000000
71 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
73 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
74 #define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
76 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
77 #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
79 #define OMAP4_GPMC_IO_OFFSET 0xa9000000
80 #define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
82 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
83 #define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
86 * ----------------------------------------------------------------------------
87 * Omap2 specific IO mapping
88 * ----------------------------------------------------------------------------
91 /* We map both L3 and L4 on OMAP2 */
92 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
93 #define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
94 #define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
95 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
96 #define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
97 #define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
99 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
100 #define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
101 #define L4_WK_243X_SIZE SZ_1M
102 #define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
103 #define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
104 /* 0x6e000000 --> 0xfe000000 */
105 #define OMAP243X_GPMC_SIZE SZ_1M
106 #define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
107 /* 0x6D000000 --> 0xfd000000 */
108 #define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
109 #define OMAP243X_SDRC_SIZE SZ_1M
110 #define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
111 /* 0x6c000000 --> 0xfc000000 */
112 #define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
113 #define OMAP243X_SMS_SIZE SZ_1M
116 #define DSP_MEM_2420_PHYS OMAP2420_DSP_MEM_BASE
117 /* 0x58000000 --> 0xfc100000 */
118 #define DSP_MEM_2420_VIRT 0xfc100000
119 #define DSP_MEM_2420_SIZE 0x28000
120 #define DSP_IPI_2420_PHYS OMAP2420_DSP_IPI_BASE
121 /* 0x59000000 --> 0xfc128000 */
122 #define DSP_IPI_2420_VIRT 0xfc128000
123 #define DSP_IPI_2420_SIZE SZ_4K
124 #define DSP_MMU_2420_PHYS OMAP2420_DSP_MMU_BASE
125 /* 0x5a000000 --> 0xfc129000 */
126 #define DSP_MMU_2420_VIRT 0xfc129000
127 #define DSP_MMU_2420_SIZE SZ_4K
129 /* 2430 IVA2.1 - currently unmapped */
132 * ----------------------------------------------------------------------------
133 * Omap3 specific IO mapping
134 * ----------------------------------------------------------------------------
137 /* We map both L3 and L4 on OMAP3 */
138 #define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */
139 #define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
140 #define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
142 #define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */
143 #define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
144 #define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
147 * ----------------------------------------------------------------------------
148 * AM33XX specific IO mapping
149 * ----------------------------------------------------------------------------
151 #define L4_WK_AM33XX_PHYS L4_WK_AM33XX_BASE
152 #define L4_WK_AM33XX_VIRT (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
153 #define L4_WK_AM33XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
156 * Need to look at the Size 4M for L4.
157 * VPOM3430 was not working for Int controller
160 #define L4_PER_34XX_PHYS L4_PER_34XX_BASE
161 /* 0x49000000 --> 0xfb000000 */
162 #define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
163 #define L4_PER_34XX_SIZE SZ_1M
165 #define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE
166 /* 0x54000000 --> 0xfe800000 */
167 #define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
168 #define L4_EMU_34XX_SIZE SZ_8M
170 #define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE
171 /* 0x6e000000 --> 0xfe000000 */
172 #define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
173 #define OMAP34XX_GPMC_SIZE SZ_1M
175 #define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE
176 /* 0x6c000000 --> 0xfc000000 */
177 #define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
178 #define OMAP343X_SMS_SIZE SZ_1M
180 #define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE
181 /* 0x6D000000 --> 0xfd000000 */
182 #define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
183 #define OMAP343X_SDRC_SIZE SZ_1M
185 /* 3430 IVA - currently unmapped */
188 * ----------------------------------------------------------------------------
189 * Omap4 specific IO mapping
190 * ----------------------------------------------------------------------------
193 /* We map both L3 and L4 on OMAP4 */
194 #define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */
195 #define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
196 #define L3_44XX_SIZE SZ_1M
198 #define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */
199 #define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
200 #define L4_44XX_SIZE SZ_4M
202 #define L4_PER_44XX_PHYS L4_PER_44XX_BASE
203 /* 0x48000000 --> 0xfa000000 */
204 #define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
205 #define L4_PER_44XX_SIZE SZ_4M
207 #define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
208 /* 0x49000000 --> 0xfb000000 */
209 #define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
210 #define L4_ABE_44XX_SIZE SZ_1M
212 #define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
213 /* 0x54000000 --> 0xfe800000 */
214 #define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
215 #define L4_EMU_44XX_SIZE SZ_8M
217 #define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
218 /* 0x50000000 --> 0xf9000000 */
219 #define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
220 #define OMAP44XX_GPMC_SIZE SZ_1M
223 #define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
224 /* 0x4c000000 --> 0xfd100000 */
225 #define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
226 #define OMAP44XX_EMIF1_SIZE SZ_1M
228 #define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
229 /* 0x4d000000 --> 0xfd200000 */
230 #define OMAP44XX_EMIF2_SIZE SZ_1M
231 #define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE)
233 #define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
234 /* 0x4e000000 --> 0xfd300000 */
235 #define OMAP44XX_DMM_SIZE SZ_1M
236 #define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
238 * ----------------------------------------------------------------------------
239 * Omap specific register access
240 * ----------------------------------------------------------------------------
243 #ifndef __ASSEMBLER__
246 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
249 extern u8 omap_readb(u32 pa);
250 extern u16 omap_readw(u32 pa);
251 extern u32 omap_readl(u32 pa);
252 extern void omap_writeb(u8 v, u32 pa);
253 extern void omap_writew(u16 v, u32 pa);
254 extern void omap_writel(u32 v, u32 pa);