2 * arch/arm/plat-omap/include/mach/mcbsp.h
4 * Defines for Multi-Channel Buffered Serial Port
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Author: Steve Johnson
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #ifndef __ASM_ARCH_OMAP_MCBSP_H
25 #define __ASM_ARCH_OMAP_MCBSP_H
27 #include <linux/completion.h>
28 #include <linux/spinlock.h>
30 #include <mach/hardware.h>
31 #include <plat/clock.h>
33 /* macro for building platform_device for McBSP ports */
34 #define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \
35 static struct platform_device omap_mcbsp##port_nr = { \
36 .name = "omap-mcbsp-dai", \
37 .id = OMAP_MCBSP##port_nr, \
40 #define MCBSP_CONFIG_TYPE2 0x2
41 #define MCBSP_CONFIG_TYPE3 0x3
42 #define MCBSP_CONFIG_TYPE4 0x4
44 #define OMAP7XX_MCBSP1_BASE 0xfffb1000
45 #define OMAP7XX_MCBSP2_BASE 0xfffb1800
47 #define OMAP1510_MCBSP1_BASE 0xe1011800
48 #define OMAP1510_MCBSP2_BASE 0xfffb1000
49 #define OMAP1510_MCBSP3_BASE 0xe1017000
51 #define OMAP1610_MCBSP1_BASE 0xe1011800
52 #define OMAP1610_MCBSP2_BASE 0xfffb1000
53 #define OMAP1610_MCBSP3_BASE 0xe1017000
55 #define OMAP24XX_MCBSP1_BASE 0x48074000
56 #define OMAP24XX_MCBSP2_BASE 0x48076000
57 #define OMAP2430_MCBSP3_BASE 0x4808c000
58 #define OMAP2430_MCBSP4_BASE 0x4808e000
59 #define OMAP2430_MCBSP5_BASE 0x48096000
61 #define OMAP34XX_MCBSP1_BASE 0x48074000
62 #define OMAP34XX_MCBSP2_BASE 0x49022000
63 #define OMAP34XX_MCBSP2_ST_BASE 0x49028000
64 #define OMAP34XX_MCBSP3_BASE 0x49024000
65 #define OMAP34XX_MCBSP3_ST_BASE 0x4902A000
66 #define OMAP34XX_MCBSP3_BASE 0x49024000
67 #define OMAP34XX_MCBSP4_BASE 0x49026000
68 #define OMAP34XX_MCBSP5_BASE 0x48096000
70 #define OMAP44XX_MCBSP1_BASE 0x40122000
71 #define OMAP44XX_MCBSP1_DMA_BASE 0x49022000
72 #define OMAP44XX_MCBSP2_BASE 0x40124000
73 #define OMAP44XX_MCBSP2_DMA_BASE 0x49024000
74 #define OMAP44XX_MCBSP3_BASE 0x40126000
75 #define OMAP44XX_MCBSP3_DMA_BASE 0x49026000
76 #define OMAP44XX_MCBSP4_BASE 0x48096000
78 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
80 #define OMAP_MCBSP_REG_DRR2 0x00
81 #define OMAP_MCBSP_REG_DRR1 0x02
82 #define OMAP_MCBSP_REG_DXR2 0x04
83 #define OMAP_MCBSP_REG_DXR1 0x06
84 #define OMAP_MCBSP_REG_SPCR2 0x08
85 #define OMAP_MCBSP_REG_SPCR1 0x0a
86 #define OMAP_MCBSP_REG_RCR2 0x0c
87 #define OMAP_MCBSP_REG_RCR1 0x0e
88 #define OMAP_MCBSP_REG_XCR2 0x10
89 #define OMAP_MCBSP_REG_XCR1 0x12
90 #define OMAP_MCBSP_REG_SRGR2 0x14
91 #define OMAP_MCBSP_REG_SRGR1 0x16
92 #define OMAP_MCBSP_REG_MCR2 0x18
93 #define OMAP_MCBSP_REG_MCR1 0x1a
94 #define OMAP_MCBSP_REG_RCERA 0x1c
95 #define OMAP_MCBSP_REG_RCERB 0x1e
96 #define OMAP_MCBSP_REG_XCERA 0x20
97 #define OMAP_MCBSP_REG_XCERB 0x22
98 #define OMAP_MCBSP_REG_PCR0 0x24
99 #define OMAP_MCBSP_REG_RCERC 0x26
100 #define OMAP_MCBSP_REG_RCERD 0x28
101 #define OMAP_MCBSP_REG_XCERC 0x2A
102 #define OMAP_MCBSP_REG_XCERD 0x2C
103 #define OMAP_MCBSP_REG_RCERE 0x2E
104 #define OMAP_MCBSP_REG_RCERF 0x30
105 #define OMAP_MCBSP_REG_XCERE 0x32
106 #define OMAP_MCBSP_REG_XCERF 0x34
107 #define OMAP_MCBSP_REG_RCERG 0x36
108 #define OMAP_MCBSP_REG_RCERH 0x38
109 #define OMAP_MCBSP_REG_XCERG 0x3A
110 #define OMAP_MCBSP_REG_XCERH 0x3C
112 /* Dummy defines, these are not available on omap1 */
113 #define OMAP_MCBSP_REG_XCCR 0x00
114 #define OMAP_MCBSP_REG_RCCR 0x00
118 #define OMAP_MCBSP_REG_DRR2 0x00
119 #define OMAP_MCBSP_REG_DRR1 0x04
120 #define OMAP_MCBSP_REG_DXR2 0x08
121 #define OMAP_MCBSP_REG_DXR1 0x0C
122 #define OMAP_MCBSP_REG_DRR 0x00
123 #define OMAP_MCBSP_REG_DXR 0x08
124 #define OMAP_MCBSP_REG_SPCR2 0x10
125 #define OMAP_MCBSP_REG_SPCR1 0x14
126 #define OMAP_MCBSP_REG_RCR2 0x18
127 #define OMAP_MCBSP_REG_RCR1 0x1C
128 #define OMAP_MCBSP_REG_XCR2 0x20
129 #define OMAP_MCBSP_REG_XCR1 0x24
130 #define OMAP_MCBSP_REG_SRGR2 0x28
131 #define OMAP_MCBSP_REG_SRGR1 0x2C
132 #define OMAP_MCBSP_REG_MCR2 0x30
133 #define OMAP_MCBSP_REG_MCR1 0x34
134 #define OMAP_MCBSP_REG_RCERA 0x38
135 #define OMAP_MCBSP_REG_RCERB 0x3C
136 #define OMAP_MCBSP_REG_XCERA 0x40
137 #define OMAP_MCBSP_REG_XCERB 0x44
138 #define OMAP_MCBSP_REG_PCR0 0x48
139 #define OMAP_MCBSP_REG_RCERC 0x4C
140 #define OMAP_MCBSP_REG_RCERD 0x50
141 #define OMAP_MCBSP_REG_XCERC 0x54
142 #define OMAP_MCBSP_REG_XCERD 0x58
143 #define OMAP_MCBSP_REG_RCERE 0x5C
144 #define OMAP_MCBSP_REG_RCERF 0x60
145 #define OMAP_MCBSP_REG_XCERE 0x64
146 #define OMAP_MCBSP_REG_XCERF 0x68
147 #define OMAP_MCBSP_REG_RCERG 0x6C
148 #define OMAP_MCBSP_REG_RCERH 0x70
149 #define OMAP_MCBSP_REG_XCERG 0x74
150 #define OMAP_MCBSP_REG_XCERH 0x78
151 #define OMAP_MCBSP_REG_SYSCON 0x8C
152 #define OMAP_MCBSP_REG_THRSH2 0x90
153 #define OMAP_MCBSP_REG_THRSH1 0x94
154 #define OMAP_MCBSP_REG_IRQST 0xA0
155 #define OMAP_MCBSP_REG_IRQEN 0xA4
156 #define OMAP_MCBSP_REG_WAKEUPEN 0xA8
157 #define OMAP_MCBSP_REG_XCCR 0xAC
158 #define OMAP_MCBSP_REG_RCCR 0xB0
159 #define OMAP_MCBSP_REG_XBUFFSTAT 0xB4
160 #define OMAP_MCBSP_REG_RBUFFSTAT 0xB8
161 #define OMAP_MCBSP_REG_SSELCR 0xBC
163 #define OMAP_ST_REG_REV 0x00
164 #define OMAP_ST_REG_SYSCONFIG 0x10
165 #define OMAP_ST_REG_IRQSTATUS 0x18
166 #define OMAP_ST_REG_IRQENABLE 0x1C
167 #define OMAP_ST_REG_SGAINCR 0x24
168 #define OMAP_ST_REG_SFIRCR 0x28
169 #define OMAP_ST_REG_SSELCR 0x2C
173 /************************** McBSP SPCR1 bit definitions ***********************/
177 #define RSYNC_ERR 0x0008
178 #define RINTM(value) ((value)<<4) /* bits 4:5 */
181 #define CLKSTP(value) ((value)<<11) /* bits 11:12 */
182 #define RJUST(value) ((value)<<13) /* bits 13:14 */
186 /************************** McBSP SPCR2 bit definitions ***********************/
189 #define XEMPTY 0x0004
190 #define XSYNC_ERR 0x0008
191 #define XINTM(value) ((value)<<4) /* bits 4:5 */
197 /************************** McBSP PCR bit definitions *************************/
202 #define DR_STAT 0x0010
203 #define DX_STAT 0x0020
204 #define CLKS_STAT 0x0040
205 #define SCLKME 0x0080
212 #define IDLE_EN 0x4000
214 /************************** McBSP RCR1 bit definitions ************************/
215 #define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
216 #define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
218 /************************** McBSP XCR1 bit definitions ************************/
219 #define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
220 #define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
222 /*************************** McBSP RCR2 bit definitions ***********************/
223 #define RDATDLY(value) (value) /* Bits 0:1 */
225 #define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
226 #define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
227 #define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
228 #define RPHASE 0x8000
230 /*************************** McBSP XCR2 bit definitions ***********************/
231 #define XDATDLY(value) (value) /* Bits 0:1 */
233 #define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
234 #define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
235 #define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
236 #define XPHASE 0x8000
238 /************************* McBSP SRGR1 bit definitions ************************/
239 #define CLKGDV(value) (value) /* Bits 0:7 */
240 #define FWID(value) ((value)<<8) /* Bits 8:15 */
242 /************************* McBSP SRGR2 bit definitions ************************/
243 #define FPER(value) (value) /* Bits 0:11 */
249 /************************* McBSP MCR1 bit definitions *************************/
251 #define RCBLK(value) ((value)<<2) /* Bits 2:4 */
252 #define RPABLK(value) ((value)<<5) /* Bits 5:6 */
253 #define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
255 /************************* McBSP MCR2 bit definitions *************************/
256 #define XMCM(value) (value) /* Bits 0:1 */
257 #define XCBLK(value) ((value)<<2) /* Bits 2:4 */
258 #define XPABLK(value) ((value)<<5) /* Bits 5:6 */
259 #define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
261 /*********************** McBSP XCCR bit definitions *************************/
262 #define EXTCLKGATE 0x8000
263 #define PPCONNECT 0x4000
264 #define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
265 #define XFULL_CYCLE 0x0800
267 #define XDMAEN 0x0008
268 #define XDISABLE 0x0001
270 /********************** McBSP RCCR bit definitions *************************/
271 #define RFULL_CYCLE 0x0800
272 #define RDMAEN 0x0008
273 #define RDISABLE 0x0001
275 /********************** McBSP SYSCONFIG bit definitions ********************/
276 #define CLOCKACTIVITY(value) ((value)<<8)
277 #define SIDLEMODE(value) ((value)<<3)
278 #define ENAWAKEUP 0x0004
279 #define SOFTRST 0x0002
281 /********************** McBSP SSELCR bit definitions ***********************/
282 #define SIDETONEEN 0x0400
284 /********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
285 #define ST_AUTOIDLE 0x0001
287 /********************** McBSP Sidetone SGAINCR bit definitions *************/
288 #define ST_CH1GAIN(value) ((value<<16)) /* Bits 16:31 */
289 #define ST_CH0GAIN(value) (value) /* Bits 0:15 */
291 /********************** McBSP Sidetone SFIRCR bit definitions **************/
292 #define ST_FIRCOEFF(value) (value) /* Bits 0:15 */
294 /********************** McBSP Sidetone SSELCR bit definitions **************/
295 #define ST_COEFFWRDONE 0x0004
296 #define ST_COEFFWREN 0x0002
297 #define ST_SIDETONEEN 0x0001
299 /********************** McBSP DMA operating modes **************************/
300 #define MCBSP_DMA_MODE_ELEMENT 0
301 #define MCBSP_DMA_MODE_THRESHOLD 1
302 #define MCBSP_DMA_MODE_FRAME 2
304 /********************** McBSP WAKEUPEN bit definitions *********************/
305 #define XEMPTYEOFEN 0x4000
306 #define XRDYEN 0x0400
307 #define XEOFEN 0x0200
308 #define XFSXEN 0x0100
309 #define XSYNCERREN 0x0080
310 #define RRDYEN 0x0008
311 #define REOFEN 0x0004
312 #define RFSREN 0x0002
313 #define RSYNCERREN 0x0001
315 /* CLKR signal muxing options */
316 #define CLKR_SRC_CLKR 0
317 #define CLKR_SRC_CLKX 1
319 /* FSR signal muxing options */
320 #define FSR_SRC_FSR 0
321 #define FSR_SRC_FSX 1
323 /* McBSP functional clock sources */
324 #define MCBSP_CLKS_PRCM_SRC 0
325 #define MCBSP_CLKS_PAD_SRC 1
327 /* we don't do multichannel for now */
328 struct omap_mcbsp_reg_cfg {
364 typedef int __bitwise omap_mcbsp_io_type_t;
365 #define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
366 #define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
369 OMAP_MCBSP_WORD_8 = 0,
375 } omap_mcbsp_word_length;
378 OMAP_MCBSP_CLK_RISING = 0,
379 OMAP_MCBSP_CLK_FALLING,
380 } omap_mcbsp_clk_polarity;
383 OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
384 OMAP_MCBSP_FS_ACTIVE_LOW,
385 } omap_mcbsp_fs_polarity;
388 OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
389 OMAP_MCBSP_CLK_STP_MODE_DELAY,
390 } omap_mcbsp_clk_stp_mode;
393 /******* SPI specific mode **********/
395 OMAP_MCBSP_SPI_MASTER = 0,
396 OMAP_MCBSP_SPI_SLAVE,
397 } omap_mcbsp_spi_mode;
399 struct omap_mcbsp_spi_cfg {
400 omap_mcbsp_spi_mode spi_mode;
401 omap_mcbsp_clk_polarity rx_clock_polarity;
402 omap_mcbsp_clk_polarity tx_clock_polarity;
403 omap_mcbsp_fs_polarity fsx_polarity;
405 omap_mcbsp_clk_stp_mode clk_stp_mode;
406 omap_mcbsp_word_length word_length;
409 /* Platform specific configuration */
410 struct omap_mcbsp_ops {
411 void (*request)(unsigned int);
412 void (*free)(unsigned int);
413 int (*set_clks_src)(u8, u8);
416 struct omap_mcbsp_platform_data {
417 unsigned long phys_base;
418 u8 dma_rx_sync, dma_tx_sync;
420 struct omap_mcbsp_ops *ops;
421 #ifdef CONFIG_ARCH_OMAP3
422 /* Sidetone block for McBSP 2 and 3 */
423 unsigned long phys_base_st;
428 struct omap_mcbsp_st_data {
429 void __iomem *io_base_st;
432 s16 taps[128]; /* Sidetone filter coefficients */
433 int nr_taps; /* Number of filter coefficients in use */
440 unsigned long phys_base;
441 unsigned long phys_dma_base;
442 void __iomem *io_base;
445 omap_mcbsp_word_length rx_word_length;
446 omap_mcbsp_word_length tx_word_length;
448 omap_mcbsp_io_type_t io_type; /* IRQ or poll */
449 /* IRQ based TX/RX */
459 /* Completion queues */
460 struct completion tx_irq_completion;
461 struct completion rx_irq_completion;
462 struct completion tx_dma_completion;
463 struct completion rx_dma_completion;
465 /* Protect the field .free, while checking if the mcbsp is in use */
467 struct omap_mcbsp_platform_data *pdata;
470 #ifdef CONFIG_ARCH_OMAP3
471 struct omap_mcbsp_st_data *st_data;
480 * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
481 * @sidetone: name of the sidetone device
483 struct omap_mcbsp_dev_attr {
484 const char *sidetone;
487 extern struct omap_mcbsp **mcbsp_ptr;
488 extern int omap_mcbsp_count, omap_mcbsp_cache_size;
490 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
491 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
493 int omap_mcbsp_init(void);
494 void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
495 struct omap_mcbsp_platform_data *config, int size);
496 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
497 #ifdef CONFIG_ARCH_OMAP3
498 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
499 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
500 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
501 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
502 u16 omap_mcbsp_get_fifo_size(unsigned int id);
503 u16 omap_mcbsp_get_tx_delay(unsigned int id);
504 u16 omap_mcbsp_get_rx_delay(unsigned int id);
505 int omap_mcbsp_get_dma_op_mode(unsigned int id);
507 static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
509 static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
511 static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
512 static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
513 static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
514 static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
515 static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
516 static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
518 int omap_mcbsp_request(unsigned int id);
519 void omap_mcbsp_free(unsigned int id);
520 void omap_mcbsp_start(unsigned int id, int tx, int rx);
521 void omap_mcbsp_stop(unsigned int id, int tx, int rx);
522 void omap_mcbsp_xmit_word(unsigned int id, u32 word);
523 u32 omap_mcbsp_recv_word(unsigned int id);
525 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
526 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
527 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
528 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
531 /* McBSP functional clock source changing function */
532 extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
533 /* SPI specific API */
534 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
536 /* Polled read/write functions */
537 int omap_mcbsp_pollread(unsigned int id, u16 * buf);
538 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
539 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
541 /* McBSP signal muxing API */
542 void omap2_mcbsp1_mux_clkr_src(u8 mux);
543 void omap2_mcbsp1_mux_fsr_src(u8 mux);
545 #ifdef CONFIG_ARCH_OMAP3
546 /* Sidetone specific API */
547 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
548 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
549 int omap_st_enable(unsigned int id);
550 int omap_st_disable(unsigned int id);
551 int omap_st_is_enabled(unsigned int id);
553 static inline int omap_st_set_chgain(unsigned int id, int channel,
554 s16 chgain) { return 0; }
555 static inline int omap_st_get_chgain(unsigned int id, int channel,
556 s16 *chgain) { return 0; }
557 static inline int omap_st_enable(unsigned int id) { return 0; }
558 static inline int omap_st_disable(unsigned int id) { return 0; }
559 static inline int omap_st_is_enabled(unsigned int id) { return 0; }