2 * OMAP2/3 powerdomain control
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
7 * Written by Paul Walmsley
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
15 #define ASM_ARM_ARCH_OMAP_POWERDOMAIN
17 #include <linux/types.h>
18 #include <linux/list.h>
20 #include <asm/atomic.h>
25 /* Powerdomain basic power states */
26 #define PWRDM_POWER_OFF 0x0
27 #define PWRDM_POWER_RET 0x1
28 #define PWRDM_POWER_INACTIVE 0x2
29 #define PWRDM_POWER_ON 0x3
31 #define PWRDM_MAX_PWRSTS 4
33 /* Powerdomain allowable state bitfields */
34 #define PWRSTS_ON (1 << PWRDM_POWER_ON)
35 #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
36 (1 << PWRDM_POWER_ON))
38 #define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
39 (1 << PWRDM_POWER_RET))
41 #define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \
42 (1 << PWRDM_POWER_ON))
44 #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
47 /* Powerdomain flags */
48 #define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
49 #define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
50 * in MEM bank 1 position. This is
53 #define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /*
54 * support to transition from a
55 * sleep state to a lower sleep
56 * state without waking up the
61 * Number of memory banks that are power-controllable. On OMAP4430, the
64 #define PWRDM_MAX_MEM_BANKS 5
67 * Maximum number of clockdomains that can be associated with a powerdomain.
68 * CORE powerdomain on OMAP4 is the worst case
70 #define PWRDM_MAX_CLKDMS 9
72 /* XXX A completely arbitrary number. What is reasonable here? */
73 #define PWRDM_TRANSITION_BAILOUT 100000
79 * struct powerdomain - OMAP powerdomain
80 * @name: Powerdomain name
81 * @omap_chip: represents the OMAP chip types containing this pwrdm
82 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
83 * @pwrsts: Possible powerdomain power states
84 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
85 * @flags: Powerdomain flags
86 * @banks: Number of software-controllable memory banks in this powerdomain
87 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
88 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
89 * @pwrdm_clkdms: Clockdomains in this powerdomain
90 * @node: list_head linking all powerdomains
98 const struct omap_chip_id omap_chip;
101 const u8 pwrsts_logic_ret;
104 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
105 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
106 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
107 struct list_head node;
109 unsigned state_counter[PWRDM_MAX_PWRSTS];
110 unsigned ret_logic_off_counter;
111 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
113 #ifdef CONFIG_PM_DEBUG
115 s64 state_timer[PWRDM_MAX_PWRSTS];
120 void pwrdm_init(struct powerdomain **pwrdm_list);
122 struct powerdomain *pwrdm_lookup(const char *name);
124 int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
126 int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
129 int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
130 int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
131 int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
132 int (*fn)(struct powerdomain *pwrdm,
133 struct clockdomain *clkdm));
135 int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
137 int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
138 int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
139 int pwrdm_read_pwrst(struct powerdomain *pwrdm);
140 int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
141 int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
143 int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
144 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
145 int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
147 int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
148 int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
149 int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
150 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
151 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
152 int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
154 int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
155 int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
156 bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
158 int pwrdm_wait_transition(struct powerdomain *pwrdm);
160 int pwrdm_state_switch(struct powerdomain *pwrdm);
161 int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
162 int pwrdm_pre_transition(void);
163 int pwrdm_post_transition(void);