2 * OMAP2/3 powerdomain control
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
7 * Written by Paul Walmsley
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
15 #define ASM_ARM_ARCH_OMAP_POWERDOMAIN
17 #include <linux/types.h>
18 #include <linux/list.h>
20 #include <asm/atomic.h>
25 /* Powerdomain basic power states */
26 #define PWRDM_POWER_OFF 0x0
27 #define PWRDM_POWER_RET 0x1
28 #define PWRDM_POWER_INACTIVE 0x2
29 #define PWRDM_POWER_ON 0x3
31 #define PWRDM_MAX_PWRSTS 4
33 /* Powerdomain allowable state bitfields */
34 #define PWRSTS_ON (1 << PWRDM_POWER_ON)
35 #define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
36 #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
37 (1 << PWRDM_POWER_ON))
39 #define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
40 (1 << PWRDM_POWER_RET))
42 #define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \
43 (1 << PWRDM_POWER_ON))
45 #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
48 /* Powerdomain flags */
49 #define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
50 #define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
51 * in MEM bank 1 position. This is
54 #define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /*
55 * support to transition from a
56 * sleep state to a lower sleep
57 * state without waking up the
62 * Number of memory banks that are power-controllable. On OMAP4430, the
65 #define PWRDM_MAX_MEM_BANKS 5
68 * Maximum number of clockdomains that can be associated with a powerdomain.
69 * CORE powerdomain on OMAP4 is the worst case
71 #define PWRDM_MAX_CLKDMS 9
73 /* XXX A completely arbitrary number. What is reasonable here? */
74 #define PWRDM_TRANSITION_BAILOUT 100000
80 * struct powerdomain - OMAP powerdomain
81 * @name: Powerdomain name
82 * @omap_chip: represents the OMAP chip types containing this pwrdm
83 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
84 * @pwrsts: Possible powerdomain power states
85 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
86 * @flags: Powerdomain flags
87 * @banks: Number of software-controllable memory banks in this powerdomain
88 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
89 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
90 * @pwrdm_clkdms: Clockdomains in this powerdomain
91 * @node: list_head linking all powerdomains
99 const struct omap_chip_id omap_chip;
102 const u8 pwrsts_logic_ret;
105 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
106 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
107 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
108 struct list_head node;
110 unsigned state_counter[PWRDM_MAX_PWRSTS];
111 unsigned ret_logic_off_counter;
112 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
114 #ifdef CONFIG_PM_DEBUG
116 s64 state_timer[PWRDM_MAX_PWRSTS];
121 void pwrdm_init(struct powerdomain **pwrdm_list);
123 struct powerdomain *pwrdm_lookup(const char *name);
125 int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
127 int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
130 int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
131 int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
132 int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
133 int (*fn)(struct powerdomain *pwrdm,
134 struct clockdomain *clkdm));
136 int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
138 int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
139 int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
140 int pwrdm_read_pwrst(struct powerdomain *pwrdm);
141 int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
142 int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
144 int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
145 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
146 int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
148 int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
149 int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
150 int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
151 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
152 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
153 int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
155 int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
156 int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
157 bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
159 int pwrdm_wait_transition(struct powerdomain *pwrdm);
161 int pwrdm_state_switch(struct powerdomain *pwrdm);
162 int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
163 int pwrdm_pre_transition(void);
164 int pwrdm_post_transition(void);
165 int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);