2 * linux/arch/arm/plat-omap/mcbsp.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Multichannel mode not supported.
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
28 #include <plat/mcbsp.h>
30 #include "../mach-omap2/cm-regbits-34xx.h"
32 struct omap_mcbsp **mcbsp_ptr;
33 int omap_mcbsp_count, omap_mcbsp_cache_size;
35 void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
37 if (cpu_class_is_omap1()) {
38 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
39 __raw_writew((u16)val, mcbsp->io_base + reg);
40 } else if (cpu_is_omap2420()) {
41 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
42 __raw_writew((u16)val, mcbsp->io_base + reg);
44 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
45 __raw_writel(val, mcbsp->io_base + reg);
49 int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
51 if (cpu_class_is_omap1()) {
52 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
53 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
54 } else if (cpu_is_omap2420()) {
55 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
56 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
58 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
59 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
63 #ifdef CONFIG_ARCH_OMAP3
64 void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
66 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
69 int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
71 return __raw_readl(mcbsp->st_data->io_base_st + reg);
75 #define MCBSP_READ(mcbsp, reg) \
76 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
77 #define MCBSP_WRITE(mcbsp, reg, val) \
78 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
79 #define MCBSP_READ_CACHE(mcbsp, reg) \
80 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
82 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
83 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
85 #define MCBSP_ST_READ(mcbsp, reg) \
86 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
87 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
88 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
90 static void omap_mcbsp_dump_reg(u8 id)
92 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
94 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
95 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
96 MCBSP_READ(mcbsp, DRR2));
97 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
98 MCBSP_READ(mcbsp, DRR1));
99 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
100 MCBSP_READ(mcbsp, DXR2));
101 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
102 MCBSP_READ(mcbsp, DXR1));
103 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
104 MCBSP_READ(mcbsp, SPCR2));
105 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
106 MCBSP_READ(mcbsp, SPCR1));
107 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
108 MCBSP_READ(mcbsp, RCR2));
109 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
110 MCBSP_READ(mcbsp, RCR1));
111 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
112 MCBSP_READ(mcbsp, XCR2));
113 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
114 MCBSP_READ(mcbsp, XCR1));
115 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
116 MCBSP_READ(mcbsp, SRGR2));
117 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
118 MCBSP_READ(mcbsp, SRGR1));
119 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
120 MCBSP_READ(mcbsp, PCR0));
121 dev_dbg(mcbsp->dev, "***********************\n");
124 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
126 struct omap_mcbsp *mcbsp_tx = dev_id;
129 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
130 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
132 if (irqst_spcr2 & XSYNC_ERR) {
133 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
135 /* Writing zero to XSYNC_ERR clears the IRQ */
136 MCBSP_WRITE(mcbsp_tx, SPCR2,
137 MCBSP_READ_CACHE(mcbsp_tx, SPCR2) & ~(XSYNC_ERR));
139 complete(&mcbsp_tx->tx_irq_completion);
145 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
147 struct omap_mcbsp *mcbsp_rx = dev_id;
150 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
151 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
153 if (irqst_spcr1 & RSYNC_ERR) {
154 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
156 /* Writing zero to RSYNC_ERR clears the IRQ */
157 MCBSP_WRITE(mcbsp_rx, SPCR1,
158 MCBSP_READ_CACHE(mcbsp_rx, SPCR1) & ~(RSYNC_ERR));
160 complete(&mcbsp_rx->tx_irq_completion);
166 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
168 struct omap_mcbsp *mcbsp_dma_tx = data;
170 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
171 MCBSP_READ(mcbsp_dma_tx, SPCR2));
173 /* We can free the channels */
174 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
175 mcbsp_dma_tx->dma_tx_lch = -1;
177 complete(&mcbsp_dma_tx->tx_dma_completion);
180 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
182 struct omap_mcbsp *mcbsp_dma_rx = data;
184 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
185 MCBSP_READ(mcbsp_dma_rx, SPCR2));
187 /* We can free the channels */
188 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
189 mcbsp_dma_rx->dma_rx_lch = -1;
191 complete(&mcbsp_dma_rx->rx_dma_completion);
195 * omap_mcbsp_config simply write a config to the
197 * You either call this function or set the McBSP registers
198 * by yourself before calling omap_mcbsp_start().
200 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
202 struct omap_mcbsp *mcbsp;
204 if (!omap_mcbsp_check_valid_id(id)) {
205 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
208 mcbsp = id_to_mcbsp_ptr(id);
210 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
211 mcbsp->id, mcbsp->phys_base);
213 /* We write the given config */
214 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
215 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
216 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
217 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
218 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
219 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
220 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
221 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
222 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
223 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
224 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
225 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
226 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
227 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
230 EXPORT_SYMBOL(omap_mcbsp_config);
232 #ifdef CONFIG_ARCH_OMAP3
233 static void omap_st_on(struct omap_mcbsp *mcbsp)
238 * Sidetone uses McBSP ICLK - which must not idle when sidetones
239 * are enabled or sidetones start sounding ugly.
241 w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
242 w &= ~(1 << (mcbsp->id - 2));
243 cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
245 /* Enable McBSP Sidetone */
246 w = MCBSP_READ(mcbsp, SSELCR);
247 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
249 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
250 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
252 /* Enable Sidetone from Sidetone Core */
253 w = MCBSP_ST_READ(mcbsp, SSELCR);
254 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
257 static void omap_st_off(struct omap_mcbsp *mcbsp)
261 w = MCBSP_ST_READ(mcbsp, SSELCR);
262 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
264 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
265 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
267 w = MCBSP_READ(mcbsp, SSELCR);
268 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
270 w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
271 w |= 1 << (mcbsp->id - 2);
272 cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
275 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
279 val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
280 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
282 val = MCBSP_ST_READ(mcbsp, SSELCR);
284 if (val & ST_COEFFWREN)
285 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
287 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
289 for (i = 0; i < 128; i++)
290 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
294 val = MCBSP_ST_READ(mcbsp, SSELCR);
295 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
296 val = MCBSP_ST_READ(mcbsp, SSELCR);
298 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
301 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
304 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
307 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
309 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
310 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
312 w = MCBSP_ST_READ(mcbsp, SSELCR);
314 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
315 ST_CH1GAIN(st_data->ch1gain));
318 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
320 struct omap_mcbsp *mcbsp;
321 struct omap_mcbsp_st_data *st_data;
324 if (!omap_mcbsp_check_valid_id(id)) {
325 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
329 mcbsp = id_to_mcbsp_ptr(id);
330 st_data = mcbsp->st_data;
335 spin_lock_irq(&mcbsp->lock);
337 st_data->ch0gain = chgain;
338 else if (channel == 1)
339 st_data->ch1gain = chgain;
343 if (st_data->enabled)
344 omap_st_chgain(mcbsp);
345 spin_unlock_irq(&mcbsp->lock);
349 EXPORT_SYMBOL(omap_st_set_chgain);
351 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
353 struct omap_mcbsp *mcbsp;
354 struct omap_mcbsp_st_data *st_data;
357 if (!omap_mcbsp_check_valid_id(id)) {
358 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
362 mcbsp = id_to_mcbsp_ptr(id);
363 st_data = mcbsp->st_data;
368 spin_lock_irq(&mcbsp->lock);
370 *chgain = st_data->ch0gain;
371 else if (channel == 1)
372 *chgain = st_data->ch1gain;
375 spin_unlock_irq(&mcbsp->lock);
379 EXPORT_SYMBOL(omap_st_get_chgain);
381 static int omap_st_start(struct omap_mcbsp *mcbsp)
383 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
385 if (st_data && st_data->enabled && !st_data->running) {
386 omap_st_fir_write(mcbsp, st_data->taps);
387 omap_st_chgain(mcbsp);
391 st_data->running = 1;
398 int omap_st_enable(unsigned int id)
400 struct omap_mcbsp *mcbsp;
401 struct omap_mcbsp_st_data *st_data;
403 if (!omap_mcbsp_check_valid_id(id)) {
404 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
408 mcbsp = id_to_mcbsp_ptr(id);
409 st_data = mcbsp->st_data;
414 spin_lock_irq(&mcbsp->lock);
415 st_data->enabled = 1;
416 omap_st_start(mcbsp);
417 spin_unlock_irq(&mcbsp->lock);
421 EXPORT_SYMBOL(omap_st_enable);
423 static int omap_st_stop(struct omap_mcbsp *mcbsp)
425 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
427 if (st_data && st_data->running) {
430 st_data->running = 0;
437 int omap_st_disable(unsigned int id)
439 struct omap_mcbsp *mcbsp;
440 struct omap_mcbsp_st_data *st_data;
443 if (!omap_mcbsp_check_valid_id(id)) {
444 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
448 mcbsp = id_to_mcbsp_ptr(id);
449 st_data = mcbsp->st_data;
454 spin_lock_irq(&mcbsp->lock);
456 st_data->enabled = 0;
457 spin_unlock_irq(&mcbsp->lock);
461 EXPORT_SYMBOL(omap_st_disable);
463 int omap_st_is_enabled(unsigned int id)
465 struct omap_mcbsp *mcbsp;
466 struct omap_mcbsp_st_data *st_data;
468 if (!omap_mcbsp_check_valid_id(id)) {
469 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
473 mcbsp = id_to_mcbsp_ptr(id);
474 st_data = mcbsp->st_data;
480 return st_data->enabled;
482 EXPORT_SYMBOL(omap_st_is_enabled);
485 * omap_mcbsp_set_tx_threshold configures how to deal
486 * with transmit threshold. the threshold value and handler can be
489 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
491 struct omap_mcbsp *mcbsp;
493 if (!cpu_is_omap34xx())
496 if (!omap_mcbsp_check_valid_id(id)) {
497 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
500 mcbsp = id_to_mcbsp_ptr(id);
502 MCBSP_WRITE(mcbsp, THRSH2, threshold);
504 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
507 * omap_mcbsp_set_rx_threshold configures how to deal
508 * with receive threshold. the threshold value and handler can be
511 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
513 struct omap_mcbsp *mcbsp;
515 if (!cpu_is_omap34xx())
518 if (!omap_mcbsp_check_valid_id(id)) {
519 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
522 mcbsp = id_to_mcbsp_ptr(id);
524 MCBSP_WRITE(mcbsp, THRSH1, threshold);
526 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
529 * omap_mcbsp_get_max_tx_thres just return the current configured
530 * maximum threshold for transmission
532 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
534 struct omap_mcbsp *mcbsp;
536 if (!omap_mcbsp_check_valid_id(id)) {
537 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
540 mcbsp = id_to_mcbsp_ptr(id);
542 return mcbsp->max_tx_thres;
544 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
547 * omap_mcbsp_get_max_rx_thres just return the current configured
548 * maximum threshold for reception
550 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
552 struct omap_mcbsp *mcbsp;
554 if (!omap_mcbsp_check_valid_id(id)) {
555 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
558 mcbsp = id_to_mcbsp_ptr(id);
560 return mcbsp->max_rx_thres;
562 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
565 * omap_mcbsp_get_dma_op_mode just return the current configured
566 * operating mode for the mcbsp channel
568 int omap_mcbsp_get_dma_op_mode(unsigned int id)
570 struct omap_mcbsp *mcbsp;
573 if (!omap_mcbsp_check_valid_id(id)) {
574 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
577 mcbsp = id_to_mcbsp_ptr(id);
579 dma_op_mode = mcbsp->dma_op_mode;
583 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
585 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
588 * Enable wakup behavior, smart idle and all wakeups
589 * REVISIT: some wakeups may be unnecessary
591 if (cpu_is_omap34xx()) {
594 syscon = MCBSP_READ(mcbsp, SYSCON);
595 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
597 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
598 syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
599 CLOCKACTIVITY(0x02));
600 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
602 syscon |= SIDLEMODE(0x01);
605 MCBSP_WRITE(mcbsp, SYSCON, syscon);
609 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
612 * Disable wakup behavior, smart idle and all wakeups
614 if (cpu_is_omap34xx()) {
617 syscon = MCBSP_READ(mcbsp, SYSCON);
618 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
620 * HW bug workaround - If no_idle mode is taken, we need to
621 * go to smart_idle before going to always_idle, or the
622 * device will not hit retention anymore.
624 syscon |= SIDLEMODE(0x02);
625 MCBSP_WRITE(mcbsp, SYSCON, syscon);
627 syscon &= ~(SIDLEMODE(0x03));
628 MCBSP_WRITE(mcbsp, SYSCON, syscon);
630 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
634 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
635 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
636 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
637 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
641 * We can choose between IRQ based or polled IO.
642 * This needs to be called before omap_mcbsp_request().
644 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
646 struct omap_mcbsp *mcbsp;
648 if (!omap_mcbsp_check_valid_id(id)) {
649 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
652 mcbsp = id_to_mcbsp_ptr(id);
654 spin_lock(&mcbsp->lock);
657 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
659 spin_unlock(&mcbsp->lock);
663 mcbsp->io_type = io_type;
665 spin_unlock(&mcbsp->lock);
669 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
671 int omap_mcbsp_request(unsigned int id)
673 struct omap_mcbsp *mcbsp;
677 if (!omap_mcbsp_check_valid_id(id)) {
678 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
681 mcbsp = id_to_mcbsp_ptr(id);
683 reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
688 spin_lock(&mcbsp->lock);
690 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
697 mcbsp->reg_cache = reg_cache;
698 spin_unlock(&mcbsp->lock);
700 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
701 mcbsp->pdata->ops->request(id);
703 clk_enable(mcbsp->iclk);
704 clk_enable(mcbsp->fclk);
706 /* Do procedure specific to omap34xx arch, if applicable */
707 omap34xx_mcbsp_request(mcbsp);
710 * Make sure that transmitter, receiver and sample-rate generator are
711 * not running before activating IRQs.
713 MCBSP_WRITE(mcbsp, SPCR1, 0);
714 MCBSP_WRITE(mcbsp, SPCR2, 0);
716 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
717 /* We need to get IRQs here */
718 init_completion(&mcbsp->tx_irq_completion);
719 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
720 0, "McBSP", (void *)mcbsp);
722 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
723 "for McBSP%d\n", mcbsp->tx_irq,
725 goto err_clk_disable;
728 init_completion(&mcbsp->rx_irq_completion);
729 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
730 0, "McBSP", (void *)mcbsp);
732 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
733 "for McBSP%d\n", mcbsp->rx_irq,
741 free_irq(mcbsp->tx_irq, (void *)mcbsp);
743 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
744 mcbsp->pdata->ops->free(id);
746 /* Do procedure specific to omap34xx arch, if applicable */
747 omap34xx_mcbsp_free(mcbsp);
749 clk_disable(mcbsp->fclk);
750 clk_disable(mcbsp->iclk);
752 spin_lock(&mcbsp->lock);
754 mcbsp->reg_cache = NULL;
756 spin_unlock(&mcbsp->lock);
761 EXPORT_SYMBOL(omap_mcbsp_request);
763 void omap_mcbsp_free(unsigned int id)
765 struct omap_mcbsp *mcbsp;
768 if (!omap_mcbsp_check_valid_id(id)) {
769 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
772 mcbsp = id_to_mcbsp_ptr(id);
774 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
775 mcbsp->pdata->ops->free(id);
777 /* Do procedure specific to omap34xx arch, if applicable */
778 omap34xx_mcbsp_free(mcbsp);
780 clk_disable(mcbsp->fclk);
781 clk_disable(mcbsp->iclk);
783 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
785 free_irq(mcbsp->rx_irq, (void *)mcbsp);
786 free_irq(mcbsp->tx_irq, (void *)mcbsp);
789 reg_cache = mcbsp->reg_cache;
791 spin_lock(&mcbsp->lock);
793 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
796 mcbsp->reg_cache = NULL;
797 spin_unlock(&mcbsp->lock);
802 EXPORT_SYMBOL(omap_mcbsp_free);
805 * Here we start the McBSP, by enabling transmitter, receiver or both.
806 * If no transmitter or receiver is active prior calling, then sample-rate
807 * generator and frame sync are started.
809 void omap_mcbsp_start(unsigned int id, int tx, int rx)
811 struct omap_mcbsp *mcbsp;
815 if (!omap_mcbsp_check_valid_id(id)) {
816 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
819 mcbsp = id_to_mcbsp_ptr(id);
821 if (cpu_is_omap34xx())
822 omap_st_start(mcbsp);
824 mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
825 mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
827 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
828 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
831 /* Start the sample generator */
832 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
833 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
836 /* Enable transmitter and receiver */
838 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
839 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
842 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
843 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
846 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
847 * REVISIT: 100us may give enough time for two CLKSRG, however
848 * due to some unknown PM related, clock gating etc. reason it
854 /* Start frame sync */
855 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
856 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
859 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
860 /* Release the transmitter and receiver */
861 w = MCBSP_READ_CACHE(mcbsp, XCCR);
862 w &= ~(tx ? XDISABLE : 0);
863 MCBSP_WRITE(mcbsp, XCCR, w);
864 w = MCBSP_READ_CACHE(mcbsp, RCCR);
865 w &= ~(rx ? RDISABLE : 0);
866 MCBSP_WRITE(mcbsp, RCCR, w);
869 /* Dump McBSP Regs */
870 omap_mcbsp_dump_reg(id);
872 EXPORT_SYMBOL(omap_mcbsp_start);
874 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
876 struct omap_mcbsp *mcbsp;
880 if (!omap_mcbsp_check_valid_id(id)) {
881 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
885 mcbsp = id_to_mcbsp_ptr(id);
887 /* Reset transmitter */
889 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
890 w = MCBSP_READ_CACHE(mcbsp, XCCR);
891 w |= (tx ? XDISABLE : 0);
892 MCBSP_WRITE(mcbsp, XCCR, w);
894 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
895 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
899 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
900 w = MCBSP_READ_CACHE(mcbsp, RCCR);
901 w |= (rx ? RDISABLE : 0);
902 MCBSP_WRITE(mcbsp, RCCR, w);
904 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
905 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
907 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
908 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
911 /* Reset the sample rate generator */
912 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
913 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
916 if (cpu_is_omap34xx())
919 EXPORT_SYMBOL(omap_mcbsp_stop);
921 /* polled mcbsp i/o operations */
922 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
924 struct omap_mcbsp *mcbsp;
926 if (!omap_mcbsp_check_valid_id(id)) {
927 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
931 mcbsp = id_to_mcbsp_ptr(id);
933 MCBSP_WRITE(mcbsp, DXR1, buf);
934 /* if frame sync error - clear the error */
935 if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
937 MCBSP_WRITE(mcbsp, SPCR2,
938 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XSYNC_ERR));
942 /* wait for transmit confirmation */
944 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
945 if (attemps++ > 1000) {
946 MCBSP_WRITE(mcbsp, SPCR2,
947 MCBSP_READ_CACHE(mcbsp, SPCR2) &
950 MCBSP_WRITE(mcbsp, SPCR2,
951 MCBSP_READ_CACHE(mcbsp, SPCR2) |
954 dev_err(mcbsp->dev, "Could not write to"
955 " McBSP%d Register\n", mcbsp->id);
963 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
965 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
967 struct omap_mcbsp *mcbsp;
969 if (!omap_mcbsp_check_valid_id(id)) {
970 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
973 mcbsp = id_to_mcbsp_ptr(id);
975 /* if frame sync error - clear the error */
976 if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
978 MCBSP_WRITE(mcbsp, SPCR1,
979 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RSYNC_ERR));
983 /* wait for recieve confirmation */
985 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
986 if (attemps++ > 1000) {
987 MCBSP_WRITE(mcbsp, SPCR1,
988 MCBSP_READ_CACHE(mcbsp, SPCR1) &
991 MCBSP_WRITE(mcbsp, SPCR1,
992 MCBSP_READ_CACHE(mcbsp, SPCR1) |
995 dev_err(mcbsp->dev, "Could not read from"
996 " McBSP%d Register\n", mcbsp->id);
1001 *buf = MCBSP_READ(mcbsp, DRR1);
1005 EXPORT_SYMBOL(omap_mcbsp_pollread);
1008 * IRQ based word transmission.
1010 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1012 struct omap_mcbsp *mcbsp;
1013 omap_mcbsp_word_length word_length;
1015 if (!omap_mcbsp_check_valid_id(id)) {
1016 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1020 mcbsp = id_to_mcbsp_ptr(id);
1021 word_length = mcbsp->tx_word_length;
1023 wait_for_completion(&mcbsp->tx_irq_completion);
1025 if (word_length > OMAP_MCBSP_WORD_16)
1026 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1027 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1029 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1031 u32 omap_mcbsp_recv_word(unsigned int id)
1033 struct omap_mcbsp *mcbsp;
1034 u16 word_lsb, word_msb = 0;
1035 omap_mcbsp_word_length word_length;
1037 if (!omap_mcbsp_check_valid_id(id)) {
1038 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1041 mcbsp = id_to_mcbsp_ptr(id);
1043 word_length = mcbsp->rx_word_length;
1045 wait_for_completion(&mcbsp->rx_irq_completion);
1047 if (word_length > OMAP_MCBSP_WORD_16)
1048 word_msb = MCBSP_READ(mcbsp, DRR2);
1049 word_lsb = MCBSP_READ(mcbsp, DRR1);
1051 return (word_lsb | (word_msb << 16));
1053 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1055 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1057 struct omap_mcbsp *mcbsp;
1058 omap_mcbsp_word_length tx_word_length;
1059 omap_mcbsp_word_length rx_word_length;
1060 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1062 if (!omap_mcbsp_check_valid_id(id)) {
1063 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1066 mcbsp = id_to_mcbsp_ptr(id);
1067 tx_word_length = mcbsp->tx_word_length;
1068 rx_word_length = mcbsp->rx_word_length;
1070 if (tx_word_length != rx_word_length)
1073 /* First we wait for the transmitter to be ready */
1074 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1075 while (!(spcr2 & XRDY)) {
1076 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1077 if (attempts++ > 1000) {
1078 /* We must reset the transmitter */
1079 MCBSP_WRITE(mcbsp, SPCR2,
1080 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1082 MCBSP_WRITE(mcbsp, SPCR2,
1083 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1085 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1086 "ready\n", mcbsp->id);
1091 /* Now we can push the data */
1092 if (tx_word_length > OMAP_MCBSP_WORD_16)
1093 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1094 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1096 /* We wait for the receiver to be ready */
1097 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1098 while (!(spcr1 & RRDY)) {
1099 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1100 if (attempts++ > 1000) {
1101 /* We must reset the receiver */
1102 MCBSP_WRITE(mcbsp, SPCR1,
1103 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1105 MCBSP_WRITE(mcbsp, SPCR1,
1106 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1108 dev_err(mcbsp->dev, "McBSP%d receiver not "
1109 "ready\n", mcbsp->id);
1114 /* Receiver is ready, let's read the dummy data */
1115 if (rx_word_length > OMAP_MCBSP_WORD_16)
1116 word_msb = MCBSP_READ(mcbsp, DRR2);
1117 word_lsb = MCBSP_READ(mcbsp, DRR1);
1121 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1123 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1125 struct omap_mcbsp *mcbsp;
1127 omap_mcbsp_word_length tx_word_length;
1128 omap_mcbsp_word_length rx_word_length;
1129 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1131 if (!omap_mcbsp_check_valid_id(id)) {
1132 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1136 mcbsp = id_to_mcbsp_ptr(id);
1138 tx_word_length = mcbsp->tx_word_length;
1139 rx_word_length = mcbsp->rx_word_length;
1141 if (tx_word_length != rx_word_length)
1144 /* First we wait for the transmitter to be ready */
1145 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1146 while (!(spcr2 & XRDY)) {
1147 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1148 if (attempts++ > 1000) {
1149 /* We must reset the transmitter */
1150 MCBSP_WRITE(mcbsp, SPCR2,
1151 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1153 MCBSP_WRITE(mcbsp, SPCR2,
1154 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1156 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1157 "ready\n", mcbsp->id);
1162 /* We first need to enable the bus clock */
1163 if (tx_word_length > OMAP_MCBSP_WORD_16)
1164 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1165 MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1167 /* We wait for the receiver to be ready */
1168 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1169 while (!(spcr1 & RRDY)) {
1170 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1171 if (attempts++ > 1000) {
1172 /* We must reset the receiver */
1173 MCBSP_WRITE(mcbsp, SPCR1,
1174 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1176 MCBSP_WRITE(mcbsp, SPCR1,
1177 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1179 dev_err(mcbsp->dev, "McBSP%d receiver not "
1180 "ready\n", mcbsp->id);
1185 /* Receiver is ready, there is something for us */
1186 if (rx_word_length > OMAP_MCBSP_WORD_16)
1187 word_msb = MCBSP_READ(mcbsp, DRR2);
1188 word_lsb = MCBSP_READ(mcbsp, DRR1);
1190 word[0] = (word_lsb | (word_msb << 16));
1194 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1197 * Simple DMA based buffer rx/tx routines.
1198 * Nothing fancy, just a single buffer tx/rx through DMA.
1199 * The DMA resources are released once the transfer is done.
1200 * For anything fancier, you should use your own customized DMA
1201 * routines and callbacks.
1203 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1204 unsigned int length)
1206 struct omap_mcbsp *mcbsp;
1212 if (!omap_mcbsp_check_valid_id(id)) {
1213 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1216 mcbsp = id_to_mcbsp_ptr(id);
1218 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1219 omap_mcbsp_tx_dma_callback,
1222 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1223 "McBSP%d TX. Trying IRQ based TX\n",
1227 mcbsp->dma_tx_lch = dma_tx_ch;
1229 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1232 init_completion(&mcbsp->tx_dma_completion);
1234 if (cpu_class_is_omap1()) {
1235 src_port = OMAP_DMA_PORT_TIPB;
1236 dest_port = OMAP_DMA_PORT_EMIFF;
1238 if (cpu_class_is_omap2())
1239 sync_dev = mcbsp->dma_tx_sync;
1241 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1242 OMAP_DMA_DATA_TYPE_S16,
1244 OMAP_DMA_SYNC_ELEMENT,
1247 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1249 OMAP_DMA_AMODE_CONSTANT,
1250 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1253 omap_set_dma_src_params(mcbsp->dma_tx_lch,
1255 OMAP_DMA_AMODE_POST_INC,
1259 omap_start_dma(mcbsp->dma_tx_lch);
1260 wait_for_completion(&mcbsp->tx_dma_completion);
1264 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1266 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1267 unsigned int length)
1269 struct omap_mcbsp *mcbsp;
1275 if (!omap_mcbsp_check_valid_id(id)) {
1276 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1279 mcbsp = id_to_mcbsp_ptr(id);
1281 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1282 omap_mcbsp_rx_dma_callback,
1285 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1286 "McBSP%d RX. Trying IRQ based RX\n",
1290 mcbsp->dma_rx_lch = dma_rx_ch;
1292 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1295 init_completion(&mcbsp->rx_dma_completion);
1297 if (cpu_class_is_omap1()) {
1298 src_port = OMAP_DMA_PORT_TIPB;
1299 dest_port = OMAP_DMA_PORT_EMIFF;
1301 if (cpu_class_is_omap2())
1302 sync_dev = mcbsp->dma_rx_sync;
1304 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1305 OMAP_DMA_DATA_TYPE_S16,
1307 OMAP_DMA_SYNC_ELEMENT,
1310 omap_set_dma_src_params(mcbsp->dma_rx_lch,
1312 OMAP_DMA_AMODE_CONSTANT,
1313 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1316 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1318 OMAP_DMA_AMODE_POST_INC,
1322 omap_start_dma(mcbsp->dma_rx_lch);
1323 wait_for_completion(&mcbsp->rx_dma_completion);
1327 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1331 * Since SPI setup is much simpler than the generic McBSP one,
1332 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1333 * Once this is done, you can call omap_mcbsp_start().
1335 void omap_mcbsp_set_spi_mode(unsigned int id,
1336 const struct omap_mcbsp_spi_cfg *spi_cfg)
1338 struct omap_mcbsp *mcbsp;
1339 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1341 if (!omap_mcbsp_check_valid_id(id)) {
1342 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1345 mcbsp = id_to_mcbsp_ptr(id);
1347 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1349 /* SPI has only one frame */
1350 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1351 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1353 /* Clock stop mode */
1354 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1355 mcbsp_cfg.spcr1 |= (1 << 12);
1357 mcbsp_cfg.spcr1 |= (3 << 11);
1359 /* Set clock parities */
1360 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1361 mcbsp_cfg.pcr0 |= CLKRP;
1363 mcbsp_cfg.pcr0 &= ~CLKRP;
1365 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1366 mcbsp_cfg.pcr0 &= ~CLKXP;
1368 mcbsp_cfg.pcr0 |= CLKXP;
1370 /* Set SCLKME to 0 and CLKSM to 1 */
1371 mcbsp_cfg.pcr0 &= ~SCLKME;
1372 mcbsp_cfg.srgr2 |= CLKSM;
1375 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1376 mcbsp_cfg.pcr0 &= ~FSXP;
1378 mcbsp_cfg.pcr0 |= FSXP;
1380 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1381 mcbsp_cfg.pcr0 |= CLKXM;
1382 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1383 mcbsp_cfg.pcr0 |= FSXM;
1384 mcbsp_cfg.srgr2 &= ~FSGM;
1385 mcbsp_cfg.xcr2 |= XDATDLY(1);
1386 mcbsp_cfg.rcr2 |= RDATDLY(1);
1388 mcbsp_cfg.pcr0 &= ~CLKXM;
1389 mcbsp_cfg.srgr1 |= CLKGDV(1);
1390 mcbsp_cfg.pcr0 &= ~FSXM;
1391 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1392 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1395 mcbsp_cfg.xcr2 &= ~XPHASE;
1396 mcbsp_cfg.rcr2 &= ~RPHASE;
1398 omap_mcbsp_config(id, &mcbsp_cfg);
1400 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1402 #ifdef CONFIG_ARCH_OMAP3
1403 #define max_thres(m) (mcbsp->pdata->buffer_size)
1404 #define valid_threshold(m, val) ((val) <= max_thres(m))
1405 #define THRESHOLD_PROP_BUILDER(prop) \
1406 static ssize_t prop##_show(struct device *dev, \
1407 struct device_attribute *attr, char *buf) \
1409 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1411 return sprintf(buf, "%u\n", mcbsp->prop); \
1414 static ssize_t prop##_store(struct device *dev, \
1415 struct device_attribute *attr, \
1416 const char *buf, size_t size) \
1418 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1419 unsigned long val; \
1422 status = strict_strtoul(buf, 0, &val); \
1426 if (!valid_threshold(mcbsp, val)) \
1429 mcbsp->prop = val; \
1433 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1435 THRESHOLD_PROP_BUILDER(max_tx_thres);
1436 THRESHOLD_PROP_BUILDER(max_rx_thres);
1438 static const char *dma_op_modes[] = {
1439 "element", "threshold", "frame",
1442 static ssize_t dma_op_mode_show(struct device *dev,
1443 struct device_attribute *attr, char *buf)
1445 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1446 int dma_op_mode, i = 0;
1448 const char * const *s;
1450 dma_op_mode = mcbsp->dma_op_mode;
1452 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1453 if (dma_op_mode == i)
1454 len += sprintf(buf + len, "[%s] ", *s);
1456 len += sprintf(buf + len, "%s ", *s);
1458 len += sprintf(buf + len, "\n");
1463 static ssize_t dma_op_mode_store(struct device *dev,
1464 struct device_attribute *attr,
1465 const char *buf, size_t size)
1467 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1468 const char * const *s;
1471 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1472 if (sysfs_streq(buf, *s))
1475 if (i == ARRAY_SIZE(dma_op_modes))
1478 spin_lock_irq(&mcbsp->lock);
1483 mcbsp->dma_op_mode = i;
1486 spin_unlock_irq(&mcbsp->lock);
1491 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1493 static ssize_t st_taps_show(struct device *dev,
1494 struct device_attribute *attr, char *buf)
1496 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1497 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1501 spin_lock_irq(&mcbsp->lock);
1502 for (i = 0; i < st_data->nr_taps; i++)
1503 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1506 status += sprintf(&buf[status], "\n");
1507 spin_unlock_irq(&mcbsp->lock);
1512 static ssize_t st_taps_store(struct device *dev,
1513 struct device_attribute *attr,
1514 const char *buf, size_t size)
1516 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1517 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1518 int val, tmp, status, i = 0;
1520 spin_lock_irq(&mcbsp->lock);
1521 memset(st_data->taps, 0, sizeof(st_data->taps));
1522 st_data->nr_taps = 0;
1525 status = sscanf(buf, "%d%n", &val, &tmp);
1526 if (status < 0 || status == 0) {
1530 if (val < -32768 || val > 32767) {
1534 st_data->taps[i++] = val;
1541 st_data->nr_taps = i;
1544 spin_unlock_irq(&mcbsp->lock);
1549 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1551 static const struct attribute *additional_attrs[] = {
1552 &dev_attr_max_tx_thres.attr,
1553 &dev_attr_max_rx_thres.attr,
1554 &dev_attr_dma_op_mode.attr,
1558 static const struct attribute_group additional_attr_group = {
1559 .attrs = (struct attribute **)additional_attrs,
1562 static inline int __devinit omap_additional_add(struct device *dev)
1564 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1567 static inline void __devexit omap_additional_remove(struct device *dev)
1569 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1572 static const struct attribute *sidetone_attrs[] = {
1573 &dev_attr_st_taps.attr,
1577 static const struct attribute_group sidetone_attr_group = {
1578 .attrs = (struct attribute **)sidetone_attrs,
1581 int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1583 struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
1584 struct omap_mcbsp_st_data *st_data;
1587 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1593 st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
1594 if (!st_data->io_base_st) {
1599 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1603 mcbsp->st_data = st_data;
1607 iounmap(st_data->io_base_st);
1615 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1617 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1620 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1621 iounmap(st_data->io_base_st);
1626 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1628 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1629 if (cpu_is_omap34xx()) {
1630 mcbsp->max_tx_thres = max_thres(mcbsp);
1631 mcbsp->max_rx_thres = max_thres(mcbsp);
1633 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1634 * for mcbsp2 instances.
1636 if (omap_additional_add(mcbsp->dev))
1637 dev_warn(mcbsp->dev,
1638 "Unable to create additional controls\n");
1640 if (mcbsp->id == 2 || mcbsp->id == 3)
1641 if (omap_st_add(mcbsp))
1642 dev_warn(mcbsp->dev,
1643 "Unable to create sidetone controls\n");
1646 mcbsp->max_tx_thres = -EINVAL;
1647 mcbsp->max_rx_thres = -EINVAL;
1651 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1653 if (cpu_is_omap34xx()) {
1654 omap_additional_remove(mcbsp->dev);
1656 if (mcbsp->id == 2 || mcbsp->id == 3)
1657 omap_st_remove(mcbsp);
1661 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1662 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1663 #endif /* CONFIG_ARCH_OMAP3 */
1666 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1667 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1669 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1671 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1672 struct omap_mcbsp *mcbsp;
1673 int id = pdev->id - 1;
1677 dev_err(&pdev->dev, "McBSP device initialized without"
1683 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1685 if (id >= omap_mcbsp_count) {
1686 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1691 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1697 spin_lock_init(&mcbsp->lock);
1700 mcbsp->dma_tx_lch = -1;
1701 mcbsp->dma_rx_lch = -1;
1703 mcbsp->phys_base = pdata->phys_base;
1704 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1705 if (!mcbsp->io_base) {
1710 /* Default I/O is IRQ based */
1711 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1712 mcbsp->tx_irq = pdata->tx_irq;
1713 mcbsp->rx_irq = pdata->rx_irq;
1714 mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1715 mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1717 mcbsp->iclk = clk_get(&pdev->dev, "ick");
1718 if (IS_ERR(mcbsp->iclk)) {
1719 ret = PTR_ERR(mcbsp->iclk);
1720 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1724 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1725 if (IS_ERR(mcbsp->fclk)) {
1726 ret = PTR_ERR(mcbsp->fclk);
1727 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1731 mcbsp->pdata = pdata;
1732 mcbsp->dev = &pdev->dev;
1733 mcbsp_ptr[id] = mcbsp;
1734 platform_set_drvdata(pdev, mcbsp);
1736 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1737 omap34xx_device_init(mcbsp);
1742 clk_put(mcbsp->iclk);
1744 iounmap(mcbsp->io_base);
1751 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1753 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1755 platform_set_drvdata(pdev, NULL);
1758 if (mcbsp->pdata && mcbsp->pdata->ops &&
1759 mcbsp->pdata->ops->free)
1760 mcbsp->pdata->ops->free(mcbsp->id);
1762 omap34xx_device_exit(mcbsp);
1764 clk_disable(mcbsp->fclk);
1765 clk_disable(mcbsp->iclk);
1766 clk_put(mcbsp->fclk);
1767 clk_put(mcbsp->iclk);
1769 iounmap(mcbsp->io_base);
1780 static struct platform_driver omap_mcbsp_driver = {
1781 .probe = omap_mcbsp_probe,
1782 .remove = __devexit_p(omap_mcbsp_remove),
1784 .name = "omap-mcbsp",
1788 int __init omap_mcbsp_init(void)
1790 /* Register the McBSP driver */
1791 return platform_driver_register(&omap_mcbsp_driver);