2 * linux/arch/arm/plat-omap/mcbsp.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Multichannel mode not supported.
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
26 #include <linux/slab.h>
29 #include <plat/mcbsp.h>
30 #include <plat/omap_device.h>
31 #include <linux/pm_runtime.h>
33 /* XXX These "sideways" includes are a sign that something is wrong */
34 #include "../mach-omap2/cm2xxx_3xxx.h"
35 #include "../mach-omap2/cm-regbits-34xx.h"
37 struct omap_mcbsp **mcbsp_ptr;
38 int omap_mcbsp_count, omap_mcbsp_cache_size;
40 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
42 if (cpu_class_is_omap1()) {
43 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
44 __raw_writew((u16)val, mcbsp->io_base + reg);
45 } else if (cpu_is_omap2420()) {
46 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
47 __raw_writew((u16)val, mcbsp->io_base + reg);
49 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
50 __raw_writel(val, mcbsp->io_base + reg);
54 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
56 if (cpu_class_is_omap1()) {
57 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
58 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
59 } else if (cpu_is_omap2420()) {
60 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
61 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
63 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
64 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
68 #ifdef CONFIG_ARCH_OMAP3
69 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
71 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
74 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
76 return __raw_readl(mcbsp->st_data->io_base_st + reg);
80 #define MCBSP_READ(mcbsp, reg) \
81 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
82 #define MCBSP_WRITE(mcbsp, reg, val) \
83 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
84 #define MCBSP_READ_CACHE(mcbsp, reg) \
85 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
87 #define MCBSP_ST_READ(mcbsp, reg) \
88 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
89 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
90 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
92 static void omap_mcbsp_dump_reg(u8 id)
94 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
96 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
97 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
98 MCBSP_READ(mcbsp, DRR2));
99 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
100 MCBSP_READ(mcbsp, DRR1));
101 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
102 MCBSP_READ(mcbsp, DXR2));
103 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
104 MCBSP_READ(mcbsp, DXR1));
105 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
106 MCBSP_READ(mcbsp, SPCR2));
107 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
108 MCBSP_READ(mcbsp, SPCR1));
109 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
110 MCBSP_READ(mcbsp, RCR2));
111 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
112 MCBSP_READ(mcbsp, RCR1));
113 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
114 MCBSP_READ(mcbsp, XCR2));
115 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
116 MCBSP_READ(mcbsp, XCR1));
117 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
118 MCBSP_READ(mcbsp, SRGR2));
119 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
120 MCBSP_READ(mcbsp, SRGR1));
121 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
122 MCBSP_READ(mcbsp, PCR0));
123 dev_dbg(mcbsp->dev, "***********************\n");
126 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
128 struct omap_mcbsp *mcbsp_tx = dev_id;
131 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
132 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
134 if (irqst_spcr2 & XSYNC_ERR) {
135 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
137 /* Writing zero to XSYNC_ERR clears the IRQ */
138 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
140 complete(&mcbsp_tx->tx_irq_completion);
146 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
148 struct omap_mcbsp *mcbsp_rx = dev_id;
151 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
152 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
154 if (irqst_spcr1 & RSYNC_ERR) {
155 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
157 /* Writing zero to RSYNC_ERR clears the IRQ */
158 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
160 complete(&mcbsp_rx->rx_irq_completion);
166 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
168 struct omap_mcbsp *mcbsp_dma_tx = data;
170 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
171 MCBSP_READ(mcbsp_dma_tx, SPCR2));
173 /* We can free the channels */
174 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
175 mcbsp_dma_tx->dma_tx_lch = -1;
177 complete(&mcbsp_dma_tx->tx_dma_completion);
180 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
182 struct omap_mcbsp *mcbsp_dma_rx = data;
184 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
185 MCBSP_READ(mcbsp_dma_rx, SPCR2));
187 /* We can free the channels */
188 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
189 mcbsp_dma_rx->dma_rx_lch = -1;
191 complete(&mcbsp_dma_rx->rx_dma_completion);
195 * omap_mcbsp_config simply write a config to the
197 * You either call this function or set the McBSP registers
198 * by yourself before calling omap_mcbsp_start().
200 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
202 struct omap_mcbsp *mcbsp;
204 if (!omap_mcbsp_check_valid_id(id)) {
205 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
208 mcbsp = id_to_mcbsp_ptr(id);
210 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
211 mcbsp->id, mcbsp->phys_base);
213 /* We write the given config */
214 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
215 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
216 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
217 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
218 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
219 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
220 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
221 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
222 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
223 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
224 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
225 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
226 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
227 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
230 EXPORT_SYMBOL(omap_mcbsp_config);
233 * omap_mcbsp_dma_params - returns the dma channel number
235 * @stream - indicates the direction of data flow (rx or tx)
237 * Returns the dma channel number for the rx channel or tx channel
238 * based on the value of @stream for the requested mcbsp given by @id
240 int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
242 struct omap_mcbsp *mcbsp;
244 if (!omap_mcbsp_check_valid_id(id)) {
245 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
248 mcbsp = id_to_mcbsp_ptr(id);
251 return mcbsp->dma_rx_sync;
253 return mcbsp->dma_tx_sync;
255 EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
258 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
260 * @stream - indicates the direction of data flow (rx or tx)
262 * Returns the address of mcbsp data transmit register or data receive register
263 * to be used by DMA for transferring/receiving data based on the value of
264 * @stream for the requested mcbsp given by @id
266 int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
268 struct omap_mcbsp *mcbsp;
271 if (!omap_mcbsp_check_valid_id(id)) {
272 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
275 mcbsp = id_to_mcbsp_ptr(id);
277 data_reg = mcbsp->phys_dma_base;
279 if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
281 data_reg += OMAP_MCBSP_REG_DRR1;
283 data_reg += OMAP_MCBSP_REG_DXR1;
286 data_reg += OMAP_MCBSP_REG_DRR;
288 data_reg += OMAP_MCBSP_REG_DXR;
293 EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
295 #ifdef CONFIG_ARCH_OMAP3
296 static struct omap_device *find_omap_device_by_dev(struct device *dev)
298 struct platform_device *pdev = container_of(dev,
299 struct platform_device, dev);
300 return container_of(pdev, struct omap_device, pdev);
303 static void omap_st_on(struct omap_mcbsp *mcbsp)
306 struct omap_device *od;
308 od = find_omap_device_by_dev(mcbsp->dev);
311 * Sidetone uses McBSP ICLK - which must not idle when sidetones
312 * are enabled or sidetones start sounding ugly.
314 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
315 w &= ~(1 << (mcbsp->id - 2));
316 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
318 /* Enable McBSP Sidetone */
319 w = MCBSP_READ(mcbsp, SSELCR);
320 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
322 /* Enable Sidetone from Sidetone Core */
323 w = MCBSP_ST_READ(mcbsp, SSELCR);
324 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
327 static void omap_st_off(struct omap_mcbsp *mcbsp)
330 struct omap_device *od;
332 od = find_omap_device_by_dev(mcbsp->dev);
334 w = MCBSP_ST_READ(mcbsp, SSELCR);
335 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
337 w = MCBSP_READ(mcbsp, SSELCR);
338 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
340 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
341 w |= 1 << (mcbsp->id - 2);
342 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
345 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
348 struct omap_device *od;
350 od = find_omap_device_by_dev(mcbsp->dev);
352 val = MCBSP_ST_READ(mcbsp, SSELCR);
354 if (val & ST_COEFFWREN)
355 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
357 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
359 for (i = 0; i < 128; i++)
360 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
364 val = MCBSP_ST_READ(mcbsp, SSELCR);
365 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
366 val = MCBSP_ST_READ(mcbsp, SSELCR);
368 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
371 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
374 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
377 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
378 struct omap_device *od;
380 od = find_omap_device_by_dev(mcbsp->dev);
382 w = MCBSP_ST_READ(mcbsp, SSELCR);
384 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
385 ST_CH1GAIN(st_data->ch1gain));
388 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
390 struct omap_mcbsp *mcbsp;
391 struct omap_mcbsp_st_data *st_data;
394 if (!omap_mcbsp_check_valid_id(id)) {
395 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
399 mcbsp = id_to_mcbsp_ptr(id);
400 st_data = mcbsp->st_data;
405 spin_lock_irq(&mcbsp->lock);
407 st_data->ch0gain = chgain;
408 else if (channel == 1)
409 st_data->ch1gain = chgain;
413 if (st_data->enabled)
414 omap_st_chgain(mcbsp);
415 spin_unlock_irq(&mcbsp->lock);
419 EXPORT_SYMBOL(omap_st_set_chgain);
421 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
423 struct omap_mcbsp *mcbsp;
424 struct omap_mcbsp_st_data *st_data;
427 if (!omap_mcbsp_check_valid_id(id)) {
428 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
432 mcbsp = id_to_mcbsp_ptr(id);
433 st_data = mcbsp->st_data;
438 spin_lock_irq(&mcbsp->lock);
440 *chgain = st_data->ch0gain;
441 else if (channel == 1)
442 *chgain = st_data->ch1gain;
445 spin_unlock_irq(&mcbsp->lock);
449 EXPORT_SYMBOL(omap_st_get_chgain);
451 static int omap_st_start(struct omap_mcbsp *mcbsp)
453 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
455 if (st_data && st_data->enabled && !st_data->running) {
456 omap_st_fir_write(mcbsp, st_data->taps);
457 omap_st_chgain(mcbsp);
461 st_data->running = 1;
468 int omap_st_enable(unsigned int id)
470 struct omap_mcbsp *mcbsp;
471 struct omap_mcbsp_st_data *st_data;
473 if (!omap_mcbsp_check_valid_id(id)) {
474 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
478 mcbsp = id_to_mcbsp_ptr(id);
479 st_data = mcbsp->st_data;
484 spin_lock_irq(&mcbsp->lock);
485 st_data->enabled = 1;
486 omap_st_start(mcbsp);
487 spin_unlock_irq(&mcbsp->lock);
491 EXPORT_SYMBOL(omap_st_enable);
493 static int omap_st_stop(struct omap_mcbsp *mcbsp)
495 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
497 if (st_data && st_data->running) {
500 st_data->running = 0;
507 int omap_st_disable(unsigned int id)
509 struct omap_mcbsp *mcbsp;
510 struct omap_mcbsp_st_data *st_data;
513 if (!omap_mcbsp_check_valid_id(id)) {
514 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
518 mcbsp = id_to_mcbsp_ptr(id);
519 st_data = mcbsp->st_data;
524 spin_lock_irq(&mcbsp->lock);
526 st_data->enabled = 0;
527 spin_unlock_irq(&mcbsp->lock);
531 EXPORT_SYMBOL(omap_st_disable);
533 int omap_st_is_enabled(unsigned int id)
535 struct omap_mcbsp *mcbsp;
536 struct omap_mcbsp_st_data *st_data;
538 if (!omap_mcbsp_check_valid_id(id)) {
539 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
543 mcbsp = id_to_mcbsp_ptr(id);
544 st_data = mcbsp->st_data;
550 return st_data->enabled;
552 EXPORT_SYMBOL(omap_st_is_enabled);
555 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
556 * The threshold parameter is 1 based, and it is converted (threshold - 1)
557 * for the THRSH2 register.
559 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
561 struct omap_mcbsp *mcbsp;
563 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
566 if (!omap_mcbsp_check_valid_id(id)) {
567 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
570 mcbsp = id_to_mcbsp_ptr(id);
572 if (threshold && threshold <= mcbsp->max_tx_thres)
573 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
575 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
578 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
579 * The threshold parameter is 1 based, and it is converted (threshold - 1)
580 * for the THRSH1 register.
582 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
584 struct omap_mcbsp *mcbsp;
586 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
589 if (!omap_mcbsp_check_valid_id(id)) {
590 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
593 mcbsp = id_to_mcbsp_ptr(id);
595 if (threshold && threshold <= mcbsp->max_rx_thres)
596 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
598 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
601 * omap_mcbsp_get_max_tx_thres just return the current configured
602 * maximum threshold for transmission
604 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
606 struct omap_mcbsp *mcbsp;
608 if (!omap_mcbsp_check_valid_id(id)) {
609 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
612 mcbsp = id_to_mcbsp_ptr(id);
614 return mcbsp->max_tx_thres;
616 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
619 * omap_mcbsp_get_max_rx_thres just return the current configured
620 * maximum threshold for reception
622 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
624 struct omap_mcbsp *mcbsp;
626 if (!omap_mcbsp_check_valid_id(id)) {
627 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
630 mcbsp = id_to_mcbsp_ptr(id);
632 return mcbsp->max_rx_thres;
634 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
636 u16 omap_mcbsp_get_fifo_size(unsigned int id)
638 struct omap_mcbsp *mcbsp;
640 if (!omap_mcbsp_check_valid_id(id)) {
641 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
644 mcbsp = id_to_mcbsp_ptr(id);
646 return mcbsp->pdata->buffer_size;
648 EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
651 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
653 u16 omap_mcbsp_get_tx_delay(unsigned int id)
655 struct omap_mcbsp *mcbsp;
658 if (!omap_mcbsp_check_valid_id(id)) {
659 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
662 mcbsp = id_to_mcbsp_ptr(id);
664 /* Returns the number of free locations in the buffer */
665 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
667 /* Number of slots are different in McBSP ports */
668 return mcbsp->pdata->buffer_size - buffstat;
670 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
673 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
674 * to reach the threshold value (when the DMA will be triggered to read it)
676 u16 omap_mcbsp_get_rx_delay(unsigned int id)
678 struct omap_mcbsp *mcbsp;
679 u16 buffstat, threshold;
681 if (!omap_mcbsp_check_valid_id(id)) {
682 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
685 mcbsp = id_to_mcbsp_ptr(id);
687 /* Returns the number of used locations in the buffer */
688 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
690 threshold = MCBSP_READ(mcbsp, THRSH1);
692 /* Return the number of location till we reach the threshold limit */
693 if (threshold <= buffstat)
696 return threshold - buffstat;
698 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
701 * omap_mcbsp_get_dma_op_mode just return the current configured
702 * operating mode for the mcbsp channel
704 int omap_mcbsp_get_dma_op_mode(unsigned int id)
706 struct omap_mcbsp *mcbsp;
709 if (!omap_mcbsp_check_valid_id(id)) {
710 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
713 mcbsp = id_to_mcbsp_ptr(id);
715 dma_op_mode = mcbsp->dma_op_mode;
719 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
721 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
723 struct omap_device *od;
725 od = find_omap_device_by_dev(mcbsp->dev);
727 * Enable wakup behavior, smart idle and all wakeups
728 * REVISIT: some wakeups may be unnecessary
730 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
731 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
735 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
737 struct omap_device *od;
739 od = find_omap_device_by_dev(mcbsp->dev);
742 * Disable wakup behavior, smart idle and all wakeups
744 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
746 * HW bug workaround - If no_idle mode is taken, we need to
747 * go to smart_idle before going to always_idle, or the
748 * device will not hit retention anymore.
751 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
755 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
756 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
757 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
758 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
762 * We can choose between IRQ based or polled IO.
763 * This needs to be called before omap_mcbsp_request().
765 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
767 struct omap_mcbsp *mcbsp;
769 if (!omap_mcbsp_check_valid_id(id)) {
770 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
773 mcbsp = id_to_mcbsp_ptr(id);
775 spin_lock(&mcbsp->lock);
778 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
780 spin_unlock(&mcbsp->lock);
784 mcbsp->io_type = io_type;
786 spin_unlock(&mcbsp->lock);
790 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
792 int omap_mcbsp_request(unsigned int id)
794 struct omap_mcbsp *mcbsp;
798 if (!omap_mcbsp_check_valid_id(id)) {
799 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
802 mcbsp = id_to_mcbsp_ptr(id);
804 reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
809 spin_lock(&mcbsp->lock);
811 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
818 mcbsp->reg_cache = reg_cache;
819 spin_unlock(&mcbsp->lock);
821 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
822 mcbsp->pdata->ops->request(id);
824 pm_runtime_get_sync(mcbsp->dev);
826 /* Do procedure specific to omap34xx arch, if applicable */
827 omap34xx_mcbsp_request(mcbsp);
830 * Make sure that transmitter, receiver and sample-rate generator are
831 * not running before activating IRQs.
833 MCBSP_WRITE(mcbsp, SPCR1, 0);
834 MCBSP_WRITE(mcbsp, SPCR2, 0);
836 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
837 /* We need to get IRQs here */
838 init_completion(&mcbsp->tx_irq_completion);
839 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
840 0, "McBSP", (void *)mcbsp);
842 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
843 "for McBSP%d\n", mcbsp->tx_irq,
845 goto err_clk_disable;
849 init_completion(&mcbsp->rx_irq_completion);
850 err = request_irq(mcbsp->rx_irq,
851 omap_mcbsp_rx_irq_handler,
852 0, "McBSP", (void *)mcbsp);
854 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
855 "for McBSP%d\n", mcbsp->rx_irq,
864 free_irq(mcbsp->tx_irq, (void *)mcbsp);
866 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
867 mcbsp->pdata->ops->free(id);
869 /* Do procedure specific to omap34xx arch, if applicable */
870 omap34xx_mcbsp_free(mcbsp);
872 pm_runtime_put_sync(mcbsp->dev);
874 spin_lock(&mcbsp->lock);
876 mcbsp->reg_cache = NULL;
878 spin_unlock(&mcbsp->lock);
883 EXPORT_SYMBOL(omap_mcbsp_request);
885 void omap_mcbsp_free(unsigned int id)
887 struct omap_mcbsp *mcbsp;
890 if (!omap_mcbsp_check_valid_id(id)) {
891 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
894 mcbsp = id_to_mcbsp_ptr(id);
896 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
897 mcbsp->pdata->ops->free(id);
899 /* Do procedure specific to omap34xx arch, if applicable */
900 omap34xx_mcbsp_free(mcbsp);
902 pm_runtime_put_sync(mcbsp->dev);
904 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
907 free_irq(mcbsp->rx_irq, (void *)mcbsp);
908 free_irq(mcbsp->tx_irq, (void *)mcbsp);
911 reg_cache = mcbsp->reg_cache;
913 spin_lock(&mcbsp->lock);
915 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
918 mcbsp->reg_cache = NULL;
919 spin_unlock(&mcbsp->lock);
924 EXPORT_SYMBOL(omap_mcbsp_free);
927 * Here we start the McBSP, by enabling transmitter, receiver or both.
928 * If no transmitter or receiver is active prior calling, then sample-rate
929 * generator and frame sync are started.
931 void omap_mcbsp_start(unsigned int id, int tx, int rx)
933 struct omap_mcbsp *mcbsp;
937 if (!omap_mcbsp_check_valid_id(id)) {
938 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
941 mcbsp = id_to_mcbsp_ptr(id);
943 if (cpu_is_omap34xx())
944 omap_st_start(mcbsp);
946 mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
947 mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
949 /* Only enable SRG, if McBSP is master */
950 w = MCBSP_READ_CACHE(mcbsp, PCR0);
951 if (w & (FSXM | FSRM | CLKXM | CLKRM))
952 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
953 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
956 /* Start the sample generator */
957 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
958 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
961 /* Enable transmitter and receiver */
963 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
964 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
967 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
968 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
971 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
972 * REVISIT: 100us may give enough time for two CLKSRG, however
973 * due to some unknown PM related, clock gating etc. reason it
979 /* Start frame sync */
980 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
981 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
984 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
985 /* Release the transmitter and receiver */
986 w = MCBSP_READ_CACHE(mcbsp, XCCR);
987 w &= ~(tx ? XDISABLE : 0);
988 MCBSP_WRITE(mcbsp, XCCR, w);
989 w = MCBSP_READ_CACHE(mcbsp, RCCR);
990 w &= ~(rx ? RDISABLE : 0);
991 MCBSP_WRITE(mcbsp, RCCR, w);
994 /* Dump McBSP Regs */
995 omap_mcbsp_dump_reg(id);
997 EXPORT_SYMBOL(omap_mcbsp_start);
999 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
1001 struct omap_mcbsp *mcbsp;
1005 if (!omap_mcbsp_check_valid_id(id)) {
1006 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1010 mcbsp = id_to_mcbsp_ptr(id);
1012 /* Reset transmitter */
1014 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
1015 w = MCBSP_READ_CACHE(mcbsp, XCCR);
1016 w |= (tx ? XDISABLE : 0);
1017 MCBSP_WRITE(mcbsp, XCCR, w);
1019 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
1020 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
1022 /* Reset receiver */
1024 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
1025 w = MCBSP_READ_CACHE(mcbsp, RCCR);
1026 w |= (rx ? RDISABLE : 0);
1027 MCBSP_WRITE(mcbsp, RCCR, w);
1029 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
1030 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
1032 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
1033 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
1036 /* Reset the sample rate generator */
1037 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
1038 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
1041 if (cpu_is_omap34xx())
1042 omap_st_stop(mcbsp);
1044 EXPORT_SYMBOL(omap_mcbsp_stop);
1046 /* polled mcbsp i/o operations */
1047 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
1049 struct omap_mcbsp *mcbsp;
1051 if (!omap_mcbsp_check_valid_id(id)) {
1052 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1056 mcbsp = id_to_mcbsp_ptr(id);
1058 MCBSP_WRITE(mcbsp, DXR1, buf);
1059 /* if frame sync error - clear the error */
1060 if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
1062 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
1066 /* wait for transmit confirmation */
1068 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
1069 if (attemps++ > 1000) {
1070 MCBSP_WRITE(mcbsp, SPCR2,
1071 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1074 MCBSP_WRITE(mcbsp, SPCR2,
1075 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1078 dev_err(mcbsp->dev, "Could not write to"
1079 " McBSP%d Register\n", mcbsp->id);
1087 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1089 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
1091 struct omap_mcbsp *mcbsp;
1093 if (!omap_mcbsp_check_valid_id(id)) {
1094 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1097 mcbsp = id_to_mcbsp_ptr(id);
1099 /* if frame sync error - clear the error */
1100 if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
1102 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
1106 /* wait for receive confirmation */
1108 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
1109 if (attemps++ > 1000) {
1110 MCBSP_WRITE(mcbsp, SPCR1,
1111 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1114 MCBSP_WRITE(mcbsp, SPCR1,
1115 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1118 dev_err(mcbsp->dev, "Could not read from"
1119 " McBSP%d Register\n", mcbsp->id);
1124 *buf = MCBSP_READ(mcbsp, DRR1);
1128 EXPORT_SYMBOL(omap_mcbsp_pollread);
1131 * IRQ based word transmission.
1133 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1135 struct omap_mcbsp *mcbsp;
1136 omap_mcbsp_word_length word_length;
1138 if (!omap_mcbsp_check_valid_id(id)) {
1139 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1143 mcbsp = id_to_mcbsp_ptr(id);
1144 word_length = mcbsp->tx_word_length;
1146 wait_for_completion(&mcbsp->tx_irq_completion);
1148 if (word_length > OMAP_MCBSP_WORD_16)
1149 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1150 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1152 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1154 u32 omap_mcbsp_recv_word(unsigned int id)
1156 struct omap_mcbsp *mcbsp;
1157 u16 word_lsb, word_msb = 0;
1158 omap_mcbsp_word_length word_length;
1160 if (!omap_mcbsp_check_valid_id(id)) {
1161 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1164 mcbsp = id_to_mcbsp_ptr(id);
1166 word_length = mcbsp->rx_word_length;
1168 wait_for_completion(&mcbsp->rx_irq_completion);
1170 if (word_length > OMAP_MCBSP_WORD_16)
1171 word_msb = MCBSP_READ(mcbsp, DRR2);
1172 word_lsb = MCBSP_READ(mcbsp, DRR1);
1174 return (word_lsb | (word_msb << 16));
1176 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1178 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1180 struct omap_mcbsp *mcbsp;
1181 omap_mcbsp_word_length tx_word_length;
1182 omap_mcbsp_word_length rx_word_length;
1183 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1185 if (!omap_mcbsp_check_valid_id(id)) {
1186 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1189 mcbsp = id_to_mcbsp_ptr(id);
1190 tx_word_length = mcbsp->tx_word_length;
1191 rx_word_length = mcbsp->rx_word_length;
1193 if (tx_word_length != rx_word_length)
1196 /* First we wait for the transmitter to be ready */
1197 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1198 while (!(spcr2 & XRDY)) {
1199 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1200 if (attempts++ > 1000) {
1201 /* We must reset the transmitter */
1202 MCBSP_WRITE(mcbsp, SPCR2,
1203 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1205 MCBSP_WRITE(mcbsp, SPCR2,
1206 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1208 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1209 "ready\n", mcbsp->id);
1214 /* Now we can push the data */
1215 if (tx_word_length > OMAP_MCBSP_WORD_16)
1216 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1217 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1219 /* We wait for the receiver to be ready */
1220 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1221 while (!(spcr1 & RRDY)) {
1222 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1223 if (attempts++ > 1000) {
1224 /* We must reset the receiver */
1225 MCBSP_WRITE(mcbsp, SPCR1,
1226 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1228 MCBSP_WRITE(mcbsp, SPCR1,
1229 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1231 dev_err(mcbsp->dev, "McBSP%d receiver not "
1232 "ready\n", mcbsp->id);
1237 /* Receiver is ready, let's read the dummy data */
1238 if (rx_word_length > OMAP_MCBSP_WORD_16)
1239 word_msb = MCBSP_READ(mcbsp, DRR2);
1240 word_lsb = MCBSP_READ(mcbsp, DRR1);
1244 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1246 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1248 struct omap_mcbsp *mcbsp;
1250 omap_mcbsp_word_length tx_word_length;
1251 omap_mcbsp_word_length rx_word_length;
1252 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1254 if (!omap_mcbsp_check_valid_id(id)) {
1255 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1259 mcbsp = id_to_mcbsp_ptr(id);
1261 tx_word_length = mcbsp->tx_word_length;
1262 rx_word_length = mcbsp->rx_word_length;
1264 if (tx_word_length != rx_word_length)
1267 /* First we wait for the transmitter to be ready */
1268 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1269 while (!(spcr2 & XRDY)) {
1270 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1271 if (attempts++ > 1000) {
1272 /* We must reset the transmitter */
1273 MCBSP_WRITE(mcbsp, SPCR2,
1274 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1276 MCBSP_WRITE(mcbsp, SPCR2,
1277 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1279 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1280 "ready\n", mcbsp->id);
1285 /* We first need to enable the bus clock */
1286 if (tx_word_length > OMAP_MCBSP_WORD_16)
1287 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1288 MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1290 /* We wait for the receiver to be ready */
1291 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1292 while (!(spcr1 & RRDY)) {
1293 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1294 if (attempts++ > 1000) {
1295 /* We must reset the receiver */
1296 MCBSP_WRITE(mcbsp, SPCR1,
1297 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1299 MCBSP_WRITE(mcbsp, SPCR1,
1300 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1302 dev_err(mcbsp->dev, "McBSP%d receiver not "
1303 "ready\n", mcbsp->id);
1308 /* Receiver is ready, there is something for us */
1309 if (rx_word_length > OMAP_MCBSP_WORD_16)
1310 word_msb = MCBSP_READ(mcbsp, DRR2);
1311 word_lsb = MCBSP_READ(mcbsp, DRR1);
1313 word[0] = (word_lsb | (word_msb << 16));
1317 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1320 * Simple DMA based buffer rx/tx routines.
1321 * Nothing fancy, just a single buffer tx/rx through DMA.
1322 * The DMA resources are released once the transfer is done.
1323 * For anything fancier, you should use your own customized DMA
1324 * routines and callbacks.
1326 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1327 unsigned int length)
1329 struct omap_mcbsp *mcbsp;
1335 if (!omap_mcbsp_check_valid_id(id)) {
1336 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1339 mcbsp = id_to_mcbsp_ptr(id);
1341 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1342 omap_mcbsp_tx_dma_callback,
1345 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1346 "McBSP%d TX. Trying IRQ based TX\n",
1350 mcbsp->dma_tx_lch = dma_tx_ch;
1352 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1355 init_completion(&mcbsp->tx_dma_completion);
1357 if (cpu_class_is_omap1()) {
1358 src_port = OMAP_DMA_PORT_TIPB;
1359 dest_port = OMAP_DMA_PORT_EMIFF;
1361 if (cpu_class_is_omap2())
1362 sync_dev = mcbsp->dma_tx_sync;
1364 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1365 OMAP_DMA_DATA_TYPE_S16,
1367 OMAP_DMA_SYNC_ELEMENT,
1370 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1372 OMAP_DMA_AMODE_CONSTANT,
1373 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1376 omap_set_dma_src_params(mcbsp->dma_tx_lch,
1378 OMAP_DMA_AMODE_POST_INC,
1382 omap_start_dma(mcbsp->dma_tx_lch);
1383 wait_for_completion(&mcbsp->tx_dma_completion);
1387 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1389 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1390 unsigned int length)
1392 struct omap_mcbsp *mcbsp;
1398 if (!omap_mcbsp_check_valid_id(id)) {
1399 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1402 mcbsp = id_to_mcbsp_ptr(id);
1404 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1405 omap_mcbsp_rx_dma_callback,
1408 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1409 "McBSP%d RX. Trying IRQ based RX\n",
1413 mcbsp->dma_rx_lch = dma_rx_ch;
1415 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1418 init_completion(&mcbsp->rx_dma_completion);
1420 if (cpu_class_is_omap1()) {
1421 src_port = OMAP_DMA_PORT_TIPB;
1422 dest_port = OMAP_DMA_PORT_EMIFF;
1424 if (cpu_class_is_omap2())
1425 sync_dev = mcbsp->dma_rx_sync;
1427 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1428 OMAP_DMA_DATA_TYPE_S16,
1430 OMAP_DMA_SYNC_ELEMENT,
1433 omap_set_dma_src_params(mcbsp->dma_rx_lch,
1435 OMAP_DMA_AMODE_CONSTANT,
1436 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1439 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1441 OMAP_DMA_AMODE_POST_INC,
1445 omap_start_dma(mcbsp->dma_rx_lch);
1446 wait_for_completion(&mcbsp->rx_dma_completion);
1450 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1454 * Since SPI setup is much simpler than the generic McBSP one,
1455 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1456 * Once this is done, you can call omap_mcbsp_start().
1458 void omap_mcbsp_set_spi_mode(unsigned int id,
1459 const struct omap_mcbsp_spi_cfg *spi_cfg)
1461 struct omap_mcbsp *mcbsp;
1462 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1464 if (!omap_mcbsp_check_valid_id(id)) {
1465 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1468 mcbsp = id_to_mcbsp_ptr(id);
1470 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1472 /* SPI has only one frame */
1473 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1474 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1476 /* Clock stop mode */
1477 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1478 mcbsp_cfg.spcr1 |= (1 << 12);
1480 mcbsp_cfg.spcr1 |= (3 << 11);
1482 /* Set clock parities */
1483 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1484 mcbsp_cfg.pcr0 |= CLKRP;
1486 mcbsp_cfg.pcr0 &= ~CLKRP;
1488 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1489 mcbsp_cfg.pcr0 &= ~CLKXP;
1491 mcbsp_cfg.pcr0 |= CLKXP;
1493 /* Set SCLKME to 0 and CLKSM to 1 */
1494 mcbsp_cfg.pcr0 &= ~SCLKME;
1495 mcbsp_cfg.srgr2 |= CLKSM;
1498 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1499 mcbsp_cfg.pcr0 &= ~FSXP;
1501 mcbsp_cfg.pcr0 |= FSXP;
1503 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1504 mcbsp_cfg.pcr0 |= CLKXM;
1505 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1506 mcbsp_cfg.pcr0 |= FSXM;
1507 mcbsp_cfg.srgr2 &= ~FSGM;
1508 mcbsp_cfg.xcr2 |= XDATDLY(1);
1509 mcbsp_cfg.rcr2 |= RDATDLY(1);
1511 mcbsp_cfg.pcr0 &= ~CLKXM;
1512 mcbsp_cfg.srgr1 |= CLKGDV(1);
1513 mcbsp_cfg.pcr0 &= ~FSXM;
1514 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1515 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1518 mcbsp_cfg.xcr2 &= ~XPHASE;
1519 mcbsp_cfg.rcr2 &= ~RPHASE;
1521 omap_mcbsp_config(id, &mcbsp_cfg);
1523 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1525 #ifdef CONFIG_ARCH_OMAP3
1526 #define max_thres(m) (mcbsp->pdata->buffer_size)
1527 #define valid_threshold(m, val) ((val) <= max_thres(m))
1528 #define THRESHOLD_PROP_BUILDER(prop) \
1529 static ssize_t prop##_show(struct device *dev, \
1530 struct device_attribute *attr, char *buf) \
1532 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1534 return sprintf(buf, "%u\n", mcbsp->prop); \
1537 static ssize_t prop##_store(struct device *dev, \
1538 struct device_attribute *attr, \
1539 const char *buf, size_t size) \
1541 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1542 unsigned long val; \
1545 status = strict_strtoul(buf, 0, &val); \
1549 if (!valid_threshold(mcbsp, val)) \
1552 mcbsp->prop = val; \
1556 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1558 THRESHOLD_PROP_BUILDER(max_tx_thres);
1559 THRESHOLD_PROP_BUILDER(max_rx_thres);
1561 static const char *dma_op_modes[] = {
1562 "element", "threshold", "frame",
1565 static ssize_t dma_op_mode_show(struct device *dev,
1566 struct device_attribute *attr, char *buf)
1568 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1569 int dma_op_mode, i = 0;
1571 const char * const *s;
1573 dma_op_mode = mcbsp->dma_op_mode;
1575 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1576 if (dma_op_mode == i)
1577 len += sprintf(buf + len, "[%s] ", *s);
1579 len += sprintf(buf + len, "%s ", *s);
1581 len += sprintf(buf + len, "\n");
1586 static ssize_t dma_op_mode_store(struct device *dev,
1587 struct device_attribute *attr,
1588 const char *buf, size_t size)
1590 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1591 const char * const *s;
1594 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1595 if (sysfs_streq(buf, *s))
1598 if (i == ARRAY_SIZE(dma_op_modes))
1601 spin_lock_irq(&mcbsp->lock);
1606 mcbsp->dma_op_mode = i;
1609 spin_unlock_irq(&mcbsp->lock);
1614 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1616 static ssize_t st_taps_show(struct device *dev,
1617 struct device_attribute *attr, char *buf)
1619 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1620 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1624 spin_lock_irq(&mcbsp->lock);
1625 for (i = 0; i < st_data->nr_taps; i++)
1626 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1629 status += sprintf(&buf[status], "\n");
1630 spin_unlock_irq(&mcbsp->lock);
1635 static ssize_t st_taps_store(struct device *dev,
1636 struct device_attribute *attr,
1637 const char *buf, size_t size)
1639 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1640 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1641 int val, tmp, status, i = 0;
1643 spin_lock_irq(&mcbsp->lock);
1644 memset(st_data->taps, 0, sizeof(st_data->taps));
1645 st_data->nr_taps = 0;
1648 status = sscanf(buf, "%d%n", &val, &tmp);
1649 if (status < 0 || status == 0) {
1653 if (val < -32768 || val > 32767) {
1657 st_data->taps[i++] = val;
1664 st_data->nr_taps = i;
1667 spin_unlock_irq(&mcbsp->lock);
1672 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1674 static const struct attribute *additional_attrs[] = {
1675 &dev_attr_max_tx_thres.attr,
1676 &dev_attr_max_rx_thres.attr,
1677 &dev_attr_dma_op_mode.attr,
1681 static const struct attribute_group additional_attr_group = {
1682 .attrs = (struct attribute **)additional_attrs,
1685 static inline int __devinit omap_additional_add(struct device *dev)
1687 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1690 static inline void __devexit omap_additional_remove(struct device *dev)
1692 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1695 static const struct attribute *sidetone_attrs[] = {
1696 &dev_attr_st_taps.attr,
1700 static const struct attribute_group sidetone_attr_group = {
1701 .attrs = (struct attribute **)sidetone_attrs,
1704 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1706 struct platform_device *pdev;
1707 struct resource *res;
1708 struct omap_mcbsp_st_data *st_data;
1711 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1717 pdev = container_of(mcbsp->dev, struct platform_device, dev);
1719 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1720 st_data->io_base_st = ioremap(res->start, resource_size(res));
1721 if (!st_data->io_base_st) {
1726 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1730 mcbsp->st_data = st_data;
1734 iounmap(st_data->io_base_st);
1742 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1744 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1747 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1748 iounmap(st_data->io_base_st);
1753 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1755 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1756 if (cpu_is_omap34xx()) {
1758 * Initially configure the maximum thresholds to a safe value.
1759 * The McBSP FIFO usage with these values should not go under
1761 * If the whole FIFO without safety buffer is used, than there
1762 * is a possibility that the DMA will be not able to push the
1763 * new data on time, causing channel shifts in runtime.
1765 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1766 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1768 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1769 * for mcbsp2 instances.
1771 if (omap_additional_add(mcbsp->dev))
1772 dev_warn(mcbsp->dev,
1773 "Unable to create additional controls\n");
1775 if (mcbsp->id == 2 || mcbsp->id == 3)
1776 if (omap_st_add(mcbsp))
1777 dev_warn(mcbsp->dev,
1778 "Unable to create sidetone controls\n");
1781 mcbsp->max_tx_thres = -EINVAL;
1782 mcbsp->max_rx_thres = -EINVAL;
1786 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1788 if (cpu_is_omap34xx()) {
1789 omap_additional_remove(mcbsp->dev);
1791 if (mcbsp->id == 2 || mcbsp->id == 3)
1792 omap_st_remove(mcbsp);
1796 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1797 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1798 #endif /* CONFIG_ARCH_OMAP3 */
1801 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1802 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1804 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1806 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1807 struct omap_mcbsp *mcbsp;
1808 int id = pdev->id - 1;
1809 struct resource *res;
1813 dev_err(&pdev->dev, "McBSP device initialized without"
1819 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1821 if (id >= omap_mcbsp_count) {
1822 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1827 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1833 spin_lock_init(&mcbsp->lock);
1836 mcbsp->dma_tx_lch = -1;
1837 mcbsp->dma_rx_lch = -1;
1839 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1841 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1843 dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1844 "resource\n", __func__, pdev->id);
1849 mcbsp->phys_base = res->start;
1850 omap_mcbsp_cache_size = resource_size(res);
1851 mcbsp->io_base = ioremap(res->start, resource_size(res));
1852 if (!mcbsp->io_base) {
1857 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1859 mcbsp->phys_dma_base = mcbsp->phys_base;
1861 mcbsp->phys_dma_base = res->start;
1863 /* Default I/O is IRQ based */
1864 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1866 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1867 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1869 /* From OMAP4 there will be a single irq line */
1870 if (mcbsp->tx_irq == -ENXIO)
1871 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1873 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1875 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1876 __func__, pdev->id);
1880 mcbsp->dma_rx_sync = res->start;
1882 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1884 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1885 __func__, pdev->id);
1889 mcbsp->dma_tx_sync = res->start;
1891 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1892 if (IS_ERR(mcbsp->fclk)) {
1893 ret = PTR_ERR(mcbsp->fclk);
1894 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1898 mcbsp->pdata = pdata;
1899 mcbsp->dev = &pdev->dev;
1900 mcbsp_ptr[id] = mcbsp;
1901 mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
1902 platform_set_drvdata(pdev, mcbsp);
1903 pm_runtime_enable(mcbsp->dev);
1905 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1906 omap34xx_device_init(mcbsp);
1911 iounmap(mcbsp->io_base);
1918 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1920 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1922 platform_set_drvdata(pdev, NULL);
1925 if (mcbsp->pdata && mcbsp->pdata->ops &&
1926 mcbsp->pdata->ops->free)
1927 mcbsp->pdata->ops->free(mcbsp->id);
1929 omap34xx_device_exit(mcbsp);
1931 clk_put(mcbsp->fclk);
1933 iounmap(mcbsp->io_base);
1940 static struct platform_driver omap_mcbsp_driver = {
1941 .probe = omap_mcbsp_probe,
1942 .remove = __devexit_p(omap_mcbsp_remove),
1944 .name = "omap-mcbsp",
1948 int __init omap_mcbsp_init(void)
1950 /* Register the McBSP driver */
1951 return platform_driver_register(&omap_mcbsp_driver);