2 * linux/arch/arm/plat-omap/mcbsp.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Multichannel mode not supported.
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
24 #include <linux/slab.h>
26 #include <plat/mcbsp.h>
27 #include <plat/omap_device.h>
28 #include <linux/pm_runtime.h>
30 /* XXX These "sideways" includes are a sign that something is wrong */
31 #include "../mach-omap2/cm2xxx_3xxx.h"
32 #include "../mach-omap2/cm-regbits-34xx.h"
34 struct omap_mcbsp **mcbsp_ptr;
35 int omap_mcbsp_count, omap_mcbsp_cache_size;
37 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
39 if (cpu_class_is_omap1()) {
40 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
41 __raw_writew((u16)val, mcbsp->io_base + reg);
42 } else if (cpu_is_omap2420()) {
43 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
44 __raw_writew((u16)val, mcbsp->io_base + reg);
46 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
47 __raw_writel(val, mcbsp->io_base + reg);
51 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
53 if (cpu_class_is_omap1()) {
54 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
55 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
56 } else if (cpu_is_omap2420()) {
57 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
58 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
60 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
61 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
65 #ifdef CONFIG_ARCH_OMAP3
66 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
68 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
71 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
73 return __raw_readl(mcbsp->st_data->io_base_st + reg);
77 #define MCBSP_READ(mcbsp, reg) \
78 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
79 #define MCBSP_WRITE(mcbsp, reg, val) \
80 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
81 #define MCBSP_READ_CACHE(mcbsp, reg) \
82 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
84 #define MCBSP_ST_READ(mcbsp, reg) \
85 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
86 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
87 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
89 static void omap_mcbsp_dump_reg(u8 id)
91 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
93 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
94 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
95 MCBSP_READ(mcbsp, DRR2));
96 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
97 MCBSP_READ(mcbsp, DRR1));
98 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
99 MCBSP_READ(mcbsp, DXR2));
100 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
101 MCBSP_READ(mcbsp, DXR1));
102 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
103 MCBSP_READ(mcbsp, SPCR2));
104 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
105 MCBSP_READ(mcbsp, SPCR1));
106 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
107 MCBSP_READ(mcbsp, RCR2));
108 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
109 MCBSP_READ(mcbsp, RCR1));
110 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
111 MCBSP_READ(mcbsp, XCR2));
112 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
113 MCBSP_READ(mcbsp, XCR1));
114 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
115 MCBSP_READ(mcbsp, SRGR2));
116 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
117 MCBSP_READ(mcbsp, SRGR1));
118 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
119 MCBSP_READ(mcbsp, PCR0));
120 dev_dbg(mcbsp->dev, "***********************\n");
123 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
125 struct omap_mcbsp *mcbsp_tx = dev_id;
128 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
129 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
131 if (irqst_spcr2 & XSYNC_ERR) {
132 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
134 /* Writing zero to XSYNC_ERR clears the IRQ */
135 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
141 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
143 struct omap_mcbsp *mcbsp_rx = dev_id;
146 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
147 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
149 if (irqst_spcr1 & RSYNC_ERR) {
150 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
152 /* Writing zero to RSYNC_ERR clears the IRQ */
153 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
160 * omap_mcbsp_config simply write a config to the
162 * You either call this function or set the McBSP registers
163 * by yourself before calling omap_mcbsp_start().
165 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
167 struct omap_mcbsp *mcbsp;
169 if (!omap_mcbsp_check_valid_id(id)) {
170 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
173 mcbsp = id_to_mcbsp_ptr(id);
175 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
176 mcbsp->id, mcbsp->phys_base);
178 /* We write the given config */
179 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
180 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
181 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
182 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
183 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
184 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
185 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
186 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
187 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
188 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
189 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
190 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
191 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
192 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
195 EXPORT_SYMBOL(omap_mcbsp_config);
198 * omap_mcbsp_dma_params - returns the dma channel number
200 * @stream - indicates the direction of data flow (rx or tx)
202 * Returns the dma channel number for the rx channel or tx channel
203 * based on the value of @stream for the requested mcbsp given by @id
205 int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
207 struct omap_mcbsp *mcbsp;
209 if (!omap_mcbsp_check_valid_id(id)) {
210 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
213 mcbsp = id_to_mcbsp_ptr(id);
216 return mcbsp->dma_rx_sync;
218 return mcbsp->dma_tx_sync;
220 EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
223 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
225 * @stream - indicates the direction of data flow (rx or tx)
227 * Returns the address of mcbsp data transmit register or data receive register
228 * to be used by DMA for transferring/receiving data based on the value of
229 * @stream for the requested mcbsp given by @id
231 int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
233 struct omap_mcbsp *mcbsp;
236 if (!omap_mcbsp_check_valid_id(id)) {
237 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
240 mcbsp = id_to_mcbsp_ptr(id);
242 data_reg = mcbsp->phys_dma_base;
244 if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
246 data_reg += OMAP_MCBSP_REG_DRR1;
248 data_reg += OMAP_MCBSP_REG_DXR1;
251 data_reg += OMAP_MCBSP_REG_DRR;
253 data_reg += OMAP_MCBSP_REG_DXR;
258 EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
260 #ifdef CONFIG_ARCH_OMAP3
261 static struct omap_device *find_omap_device_by_dev(struct device *dev)
263 struct platform_device *pdev = container_of(dev,
264 struct platform_device, dev);
265 return container_of(pdev, struct omap_device, pdev);
268 static void omap_st_on(struct omap_mcbsp *mcbsp)
271 struct omap_device *od;
273 od = find_omap_device_by_dev(mcbsp->dev);
276 * Sidetone uses McBSP ICLK - which must not idle when sidetones
277 * are enabled or sidetones start sounding ugly.
279 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
280 w &= ~(1 << (mcbsp->id - 2));
281 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
283 /* Enable McBSP Sidetone */
284 w = MCBSP_READ(mcbsp, SSELCR);
285 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
287 /* Enable Sidetone from Sidetone Core */
288 w = MCBSP_ST_READ(mcbsp, SSELCR);
289 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
292 static void omap_st_off(struct omap_mcbsp *mcbsp)
295 struct omap_device *od;
297 od = find_omap_device_by_dev(mcbsp->dev);
299 w = MCBSP_ST_READ(mcbsp, SSELCR);
300 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
302 w = MCBSP_READ(mcbsp, SSELCR);
303 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
305 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
306 w |= 1 << (mcbsp->id - 2);
307 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
310 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
313 struct omap_device *od;
315 od = find_omap_device_by_dev(mcbsp->dev);
317 val = MCBSP_ST_READ(mcbsp, SSELCR);
319 if (val & ST_COEFFWREN)
320 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
322 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
324 for (i = 0; i < 128; i++)
325 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
329 val = MCBSP_ST_READ(mcbsp, SSELCR);
330 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
331 val = MCBSP_ST_READ(mcbsp, SSELCR);
333 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
336 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
339 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
342 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
343 struct omap_device *od;
345 od = find_omap_device_by_dev(mcbsp->dev);
347 w = MCBSP_ST_READ(mcbsp, SSELCR);
349 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
350 ST_CH1GAIN(st_data->ch1gain));
353 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
355 struct omap_mcbsp *mcbsp;
356 struct omap_mcbsp_st_data *st_data;
359 if (!omap_mcbsp_check_valid_id(id)) {
360 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
364 mcbsp = id_to_mcbsp_ptr(id);
365 st_data = mcbsp->st_data;
370 spin_lock_irq(&mcbsp->lock);
372 st_data->ch0gain = chgain;
373 else if (channel == 1)
374 st_data->ch1gain = chgain;
378 if (st_data->enabled)
379 omap_st_chgain(mcbsp);
380 spin_unlock_irq(&mcbsp->lock);
384 EXPORT_SYMBOL(omap_st_set_chgain);
386 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
388 struct omap_mcbsp *mcbsp;
389 struct omap_mcbsp_st_data *st_data;
392 if (!omap_mcbsp_check_valid_id(id)) {
393 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
397 mcbsp = id_to_mcbsp_ptr(id);
398 st_data = mcbsp->st_data;
403 spin_lock_irq(&mcbsp->lock);
405 *chgain = st_data->ch0gain;
406 else if (channel == 1)
407 *chgain = st_data->ch1gain;
410 spin_unlock_irq(&mcbsp->lock);
414 EXPORT_SYMBOL(omap_st_get_chgain);
416 static int omap_st_start(struct omap_mcbsp *mcbsp)
418 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
420 if (st_data && st_data->enabled && !st_data->running) {
421 omap_st_fir_write(mcbsp, st_data->taps);
422 omap_st_chgain(mcbsp);
426 st_data->running = 1;
433 int omap_st_enable(unsigned int id)
435 struct omap_mcbsp *mcbsp;
436 struct omap_mcbsp_st_data *st_data;
438 if (!omap_mcbsp_check_valid_id(id)) {
439 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
443 mcbsp = id_to_mcbsp_ptr(id);
444 st_data = mcbsp->st_data;
449 spin_lock_irq(&mcbsp->lock);
450 st_data->enabled = 1;
451 omap_st_start(mcbsp);
452 spin_unlock_irq(&mcbsp->lock);
456 EXPORT_SYMBOL(omap_st_enable);
458 static int omap_st_stop(struct omap_mcbsp *mcbsp)
460 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
462 if (st_data && st_data->running) {
465 st_data->running = 0;
472 int omap_st_disable(unsigned int id)
474 struct omap_mcbsp *mcbsp;
475 struct omap_mcbsp_st_data *st_data;
478 if (!omap_mcbsp_check_valid_id(id)) {
479 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
483 mcbsp = id_to_mcbsp_ptr(id);
484 st_data = mcbsp->st_data;
489 spin_lock_irq(&mcbsp->lock);
491 st_data->enabled = 0;
492 spin_unlock_irq(&mcbsp->lock);
496 EXPORT_SYMBOL(omap_st_disable);
498 int omap_st_is_enabled(unsigned int id)
500 struct omap_mcbsp *mcbsp;
501 struct omap_mcbsp_st_data *st_data;
503 if (!omap_mcbsp_check_valid_id(id)) {
504 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
508 mcbsp = id_to_mcbsp_ptr(id);
509 st_data = mcbsp->st_data;
515 return st_data->enabled;
517 EXPORT_SYMBOL(omap_st_is_enabled);
520 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
521 * The threshold parameter is 1 based, and it is converted (threshold - 1)
522 * for the THRSH2 register.
524 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
526 struct omap_mcbsp *mcbsp;
528 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
531 if (!omap_mcbsp_check_valid_id(id)) {
532 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
535 mcbsp = id_to_mcbsp_ptr(id);
537 if (threshold && threshold <= mcbsp->max_tx_thres)
538 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
540 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
543 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
544 * The threshold parameter is 1 based, and it is converted (threshold - 1)
545 * for the THRSH1 register.
547 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
549 struct omap_mcbsp *mcbsp;
551 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
554 if (!omap_mcbsp_check_valid_id(id)) {
555 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
558 mcbsp = id_to_mcbsp_ptr(id);
560 if (threshold && threshold <= mcbsp->max_rx_thres)
561 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
563 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
566 * omap_mcbsp_get_max_tx_thres just return the current configured
567 * maximum threshold for transmission
569 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
571 struct omap_mcbsp *mcbsp;
573 if (!omap_mcbsp_check_valid_id(id)) {
574 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
577 mcbsp = id_to_mcbsp_ptr(id);
579 return mcbsp->max_tx_thres;
581 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
584 * omap_mcbsp_get_max_rx_thres just return the current configured
585 * maximum threshold for reception
587 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
589 struct omap_mcbsp *mcbsp;
591 if (!omap_mcbsp_check_valid_id(id)) {
592 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
595 mcbsp = id_to_mcbsp_ptr(id);
597 return mcbsp->max_rx_thres;
599 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
601 u16 omap_mcbsp_get_fifo_size(unsigned int id)
603 struct omap_mcbsp *mcbsp;
605 if (!omap_mcbsp_check_valid_id(id)) {
606 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
609 mcbsp = id_to_mcbsp_ptr(id);
611 return mcbsp->pdata->buffer_size;
613 EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
616 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
618 u16 omap_mcbsp_get_tx_delay(unsigned int id)
620 struct omap_mcbsp *mcbsp;
623 if (!omap_mcbsp_check_valid_id(id)) {
624 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
627 mcbsp = id_to_mcbsp_ptr(id);
629 /* Returns the number of free locations in the buffer */
630 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
632 /* Number of slots are different in McBSP ports */
633 return mcbsp->pdata->buffer_size - buffstat;
635 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
638 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
639 * to reach the threshold value (when the DMA will be triggered to read it)
641 u16 omap_mcbsp_get_rx_delay(unsigned int id)
643 struct omap_mcbsp *mcbsp;
644 u16 buffstat, threshold;
646 if (!omap_mcbsp_check_valid_id(id)) {
647 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
650 mcbsp = id_to_mcbsp_ptr(id);
652 /* Returns the number of used locations in the buffer */
653 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
655 threshold = MCBSP_READ(mcbsp, THRSH1);
657 /* Return the number of location till we reach the threshold limit */
658 if (threshold <= buffstat)
661 return threshold - buffstat;
663 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
666 * omap_mcbsp_get_dma_op_mode just return the current configured
667 * operating mode for the mcbsp channel
669 int omap_mcbsp_get_dma_op_mode(unsigned int id)
671 struct omap_mcbsp *mcbsp;
674 if (!omap_mcbsp_check_valid_id(id)) {
675 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
678 mcbsp = id_to_mcbsp_ptr(id);
680 dma_op_mode = mcbsp->dma_op_mode;
684 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
686 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
688 struct omap_device *od;
690 od = find_omap_device_by_dev(mcbsp->dev);
692 * Enable wakup behavior, smart idle and all wakeups
693 * REVISIT: some wakeups may be unnecessary
695 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
696 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
700 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
702 struct omap_device *od;
704 od = find_omap_device_by_dev(mcbsp->dev);
707 * Disable wakup behavior, smart idle and all wakeups
709 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
711 * HW bug workaround - If no_idle mode is taken, we need to
712 * go to smart_idle before going to always_idle, or the
713 * device will not hit retention anymore.
716 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
720 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
721 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
722 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
723 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
726 int omap_mcbsp_request(unsigned int id)
728 struct omap_mcbsp *mcbsp;
732 if (!omap_mcbsp_check_valid_id(id)) {
733 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
736 mcbsp = id_to_mcbsp_ptr(id);
738 reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
743 spin_lock(&mcbsp->lock);
745 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
752 mcbsp->reg_cache = reg_cache;
753 spin_unlock(&mcbsp->lock);
755 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
756 mcbsp->pdata->ops->request(id);
758 pm_runtime_get_sync(mcbsp->dev);
760 /* Do procedure specific to omap34xx arch, if applicable */
761 omap34xx_mcbsp_request(mcbsp);
764 * Make sure that transmitter, receiver and sample-rate generator are
765 * not running before activating IRQs.
767 MCBSP_WRITE(mcbsp, SPCR1, 0);
768 MCBSP_WRITE(mcbsp, SPCR2, 0);
770 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
771 0, "McBSP", (void *)mcbsp);
773 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
774 "for McBSP%d\n", mcbsp->tx_irq,
776 goto err_clk_disable;
780 err = request_irq(mcbsp->rx_irq,
781 omap_mcbsp_rx_irq_handler,
782 0, "McBSP", (void *)mcbsp);
784 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
785 "for McBSP%d\n", mcbsp->rx_irq,
793 free_irq(mcbsp->tx_irq, (void *)mcbsp);
795 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
796 mcbsp->pdata->ops->free(id);
798 /* Do procedure specific to omap34xx arch, if applicable */
799 omap34xx_mcbsp_free(mcbsp);
801 pm_runtime_put_sync(mcbsp->dev);
803 spin_lock(&mcbsp->lock);
805 mcbsp->reg_cache = NULL;
807 spin_unlock(&mcbsp->lock);
812 EXPORT_SYMBOL(omap_mcbsp_request);
814 void omap_mcbsp_free(unsigned int id)
816 struct omap_mcbsp *mcbsp;
819 if (!omap_mcbsp_check_valid_id(id)) {
820 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
823 mcbsp = id_to_mcbsp_ptr(id);
825 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
826 mcbsp->pdata->ops->free(id);
828 /* Do procedure specific to omap34xx arch, if applicable */
829 omap34xx_mcbsp_free(mcbsp);
831 pm_runtime_put_sync(mcbsp->dev);
834 free_irq(mcbsp->rx_irq, (void *)mcbsp);
835 free_irq(mcbsp->tx_irq, (void *)mcbsp);
837 reg_cache = mcbsp->reg_cache;
839 spin_lock(&mcbsp->lock);
841 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
844 mcbsp->reg_cache = NULL;
845 spin_unlock(&mcbsp->lock);
850 EXPORT_SYMBOL(omap_mcbsp_free);
853 * Here we start the McBSP, by enabling transmitter, receiver or both.
854 * If no transmitter or receiver is active prior calling, then sample-rate
855 * generator and frame sync are started.
857 void omap_mcbsp_start(unsigned int id, int tx, int rx)
859 struct omap_mcbsp *mcbsp;
863 if (!omap_mcbsp_check_valid_id(id)) {
864 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
867 mcbsp = id_to_mcbsp_ptr(id);
869 if (cpu_is_omap34xx())
870 omap_st_start(mcbsp);
872 /* Only enable SRG, if McBSP is master */
873 w = MCBSP_READ_CACHE(mcbsp, PCR0);
874 if (w & (FSXM | FSRM | CLKXM | CLKRM))
875 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
876 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
879 /* Start the sample generator */
880 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
881 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
884 /* Enable transmitter and receiver */
886 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
887 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
890 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
891 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
894 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
895 * REVISIT: 100us may give enough time for two CLKSRG, however
896 * due to some unknown PM related, clock gating etc. reason it
902 /* Start frame sync */
903 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
904 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
907 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
908 /* Release the transmitter and receiver */
909 w = MCBSP_READ_CACHE(mcbsp, XCCR);
910 w &= ~(tx ? XDISABLE : 0);
911 MCBSP_WRITE(mcbsp, XCCR, w);
912 w = MCBSP_READ_CACHE(mcbsp, RCCR);
913 w &= ~(rx ? RDISABLE : 0);
914 MCBSP_WRITE(mcbsp, RCCR, w);
917 /* Dump McBSP Regs */
918 omap_mcbsp_dump_reg(id);
920 EXPORT_SYMBOL(omap_mcbsp_start);
922 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
924 struct omap_mcbsp *mcbsp;
928 if (!omap_mcbsp_check_valid_id(id)) {
929 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
933 mcbsp = id_to_mcbsp_ptr(id);
935 /* Reset transmitter */
937 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
938 w = MCBSP_READ_CACHE(mcbsp, XCCR);
939 w |= (tx ? XDISABLE : 0);
940 MCBSP_WRITE(mcbsp, XCCR, w);
942 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
943 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
947 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
948 w = MCBSP_READ_CACHE(mcbsp, RCCR);
949 w |= (rx ? RDISABLE : 0);
950 MCBSP_WRITE(mcbsp, RCCR, w);
952 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
953 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
955 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
956 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
959 /* Reset the sample rate generator */
960 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
961 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
964 if (cpu_is_omap34xx())
967 EXPORT_SYMBOL(omap_mcbsp_stop);
969 #ifdef CONFIG_ARCH_OMAP3
970 #define max_thres(m) (mcbsp->pdata->buffer_size)
971 #define valid_threshold(m, val) ((val) <= max_thres(m))
972 #define THRESHOLD_PROP_BUILDER(prop) \
973 static ssize_t prop##_show(struct device *dev, \
974 struct device_attribute *attr, char *buf) \
976 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
978 return sprintf(buf, "%u\n", mcbsp->prop); \
981 static ssize_t prop##_store(struct device *dev, \
982 struct device_attribute *attr, \
983 const char *buf, size_t size) \
985 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
989 status = strict_strtoul(buf, 0, &val); \
993 if (!valid_threshold(mcbsp, val)) \
1000 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1002 THRESHOLD_PROP_BUILDER(max_tx_thres);
1003 THRESHOLD_PROP_BUILDER(max_rx_thres);
1005 static const char *dma_op_modes[] = {
1006 "element", "threshold", "frame",
1009 static ssize_t dma_op_mode_show(struct device *dev,
1010 struct device_attribute *attr, char *buf)
1012 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1013 int dma_op_mode, i = 0;
1015 const char * const *s;
1017 dma_op_mode = mcbsp->dma_op_mode;
1019 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1020 if (dma_op_mode == i)
1021 len += sprintf(buf + len, "[%s] ", *s);
1023 len += sprintf(buf + len, "%s ", *s);
1025 len += sprintf(buf + len, "\n");
1030 static ssize_t dma_op_mode_store(struct device *dev,
1031 struct device_attribute *attr,
1032 const char *buf, size_t size)
1034 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1035 const char * const *s;
1038 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1039 if (sysfs_streq(buf, *s))
1042 if (i == ARRAY_SIZE(dma_op_modes))
1045 spin_lock_irq(&mcbsp->lock);
1050 mcbsp->dma_op_mode = i;
1053 spin_unlock_irq(&mcbsp->lock);
1058 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1060 static ssize_t st_taps_show(struct device *dev,
1061 struct device_attribute *attr, char *buf)
1063 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1064 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1068 spin_lock_irq(&mcbsp->lock);
1069 for (i = 0; i < st_data->nr_taps; i++)
1070 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1073 status += sprintf(&buf[status], "\n");
1074 spin_unlock_irq(&mcbsp->lock);
1079 static ssize_t st_taps_store(struct device *dev,
1080 struct device_attribute *attr,
1081 const char *buf, size_t size)
1083 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1084 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1085 int val, tmp, status, i = 0;
1087 spin_lock_irq(&mcbsp->lock);
1088 memset(st_data->taps, 0, sizeof(st_data->taps));
1089 st_data->nr_taps = 0;
1092 status = sscanf(buf, "%d%n", &val, &tmp);
1093 if (status < 0 || status == 0) {
1097 if (val < -32768 || val > 32767) {
1101 st_data->taps[i++] = val;
1108 st_data->nr_taps = i;
1111 spin_unlock_irq(&mcbsp->lock);
1116 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1118 static const struct attribute *additional_attrs[] = {
1119 &dev_attr_max_tx_thres.attr,
1120 &dev_attr_max_rx_thres.attr,
1121 &dev_attr_dma_op_mode.attr,
1125 static const struct attribute_group additional_attr_group = {
1126 .attrs = (struct attribute **)additional_attrs,
1129 static inline int __devinit omap_additional_add(struct device *dev)
1131 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1134 static inline void __devexit omap_additional_remove(struct device *dev)
1136 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1139 static const struct attribute *sidetone_attrs[] = {
1140 &dev_attr_st_taps.attr,
1144 static const struct attribute_group sidetone_attr_group = {
1145 .attrs = (struct attribute **)sidetone_attrs,
1148 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1150 struct platform_device *pdev;
1151 struct resource *res;
1152 struct omap_mcbsp_st_data *st_data;
1155 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1161 pdev = container_of(mcbsp->dev, struct platform_device, dev);
1163 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1164 st_data->io_base_st = ioremap(res->start, resource_size(res));
1165 if (!st_data->io_base_st) {
1170 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1174 mcbsp->st_data = st_data;
1178 iounmap(st_data->io_base_st);
1186 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1188 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1191 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1192 iounmap(st_data->io_base_st);
1197 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1199 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1200 if (cpu_is_omap34xx()) {
1202 * Initially configure the maximum thresholds to a safe value.
1203 * The McBSP FIFO usage with these values should not go under
1205 * If the whole FIFO without safety buffer is used, than there
1206 * is a possibility that the DMA will be not able to push the
1207 * new data on time, causing channel shifts in runtime.
1209 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1210 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1212 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1213 * for mcbsp2 instances.
1215 if (omap_additional_add(mcbsp->dev))
1216 dev_warn(mcbsp->dev,
1217 "Unable to create additional controls\n");
1219 if (mcbsp->id == 2 || mcbsp->id == 3)
1220 if (omap_st_add(mcbsp))
1221 dev_warn(mcbsp->dev,
1222 "Unable to create sidetone controls\n");
1225 mcbsp->max_tx_thres = -EINVAL;
1226 mcbsp->max_rx_thres = -EINVAL;
1230 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1232 if (cpu_is_omap34xx()) {
1233 omap_additional_remove(mcbsp->dev);
1235 if (mcbsp->id == 2 || mcbsp->id == 3)
1236 omap_st_remove(mcbsp);
1240 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1241 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1242 #endif /* CONFIG_ARCH_OMAP3 */
1245 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1246 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1248 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1250 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1251 struct omap_mcbsp *mcbsp;
1252 int id = pdev->id - 1;
1253 struct resource *res;
1257 dev_err(&pdev->dev, "McBSP device initialized without"
1263 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1265 if (id >= omap_mcbsp_count) {
1266 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1271 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1277 spin_lock_init(&mcbsp->lock);
1281 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1283 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1285 dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1286 "resource\n", __func__, pdev->id);
1291 mcbsp->phys_base = res->start;
1292 omap_mcbsp_cache_size = resource_size(res);
1293 mcbsp->io_base = ioremap(res->start, resource_size(res));
1294 if (!mcbsp->io_base) {
1299 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1301 mcbsp->phys_dma_base = mcbsp->phys_base;
1303 mcbsp->phys_dma_base = res->start;
1305 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1306 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1308 /* From OMAP4 there will be a single irq line */
1309 if (mcbsp->tx_irq == -ENXIO)
1310 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1312 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1314 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1315 __func__, pdev->id);
1319 mcbsp->dma_rx_sync = res->start;
1321 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1323 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1324 __func__, pdev->id);
1328 mcbsp->dma_tx_sync = res->start;
1330 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1331 if (IS_ERR(mcbsp->fclk)) {
1332 ret = PTR_ERR(mcbsp->fclk);
1333 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1337 mcbsp->pdata = pdata;
1338 mcbsp->dev = &pdev->dev;
1339 mcbsp_ptr[id] = mcbsp;
1340 mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
1341 platform_set_drvdata(pdev, mcbsp);
1342 pm_runtime_enable(mcbsp->dev);
1344 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1345 omap34xx_device_init(mcbsp);
1350 iounmap(mcbsp->io_base);
1357 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1359 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1361 platform_set_drvdata(pdev, NULL);
1364 if (mcbsp->pdata && mcbsp->pdata->ops &&
1365 mcbsp->pdata->ops->free)
1366 mcbsp->pdata->ops->free(mcbsp->id);
1368 omap34xx_device_exit(mcbsp);
1370 clk_put(mcbsp->fclk);
1372 iounmap(mcbsp->io_base);
1379 static struct platform_driver omap_mcbsp_driver = {
1380 .probe = omap_mcbsp_probe,
1381 .remove = __devexit_p(omap_mcbsp_remove),
1383 .name = "omap-mcbsp",
1387 int __init omap_mcbsp_init(void)
1389 /* Register the McBSP driver */
1390 return platform_driver_register(&omap_mcbsp_driver);