arch/arm/plat-omap/sram.c

   1 /*
   2  * linux/arch/arm/plat-omap/sram.c
   3  *
   4  * OMAP SRAM detection and management
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #undef DEBUG
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/tlb.h>
  24 #include <asm/cacheflush.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include <plat/sram.h>
  29 #include <plat/board.h>
  30 #include <plat/cpu.h>
  31 #include <plat/vram.h>
  32
  33 #include <plat/control.h>
  34
  35 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  36 # include "../mach-omap2/prm.h"
  37 # include "../mach-omap2/cm.h"
  38 # include "../mach-omap2/sdrc.h"
  39 #endif
  40
  41 #define OMAP1_SRAM_PA           0x20000000
  42 #define OMAP1_SRAM_VA           VMALLOC_END
  43 #define OMAP2_SRAM_PA           0x40200000
  44 #define OMAP2_SRAM_PUB_PA       0x4020f800
  45 #define OMAP2_SRAM_VA           0xfe400000
  46 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
  47 #define OMAP3_SRAM_PA           0x40200000
  48 #define OMAP3_SRAM_VA           0xfe400000
  49 #define OMAP3_SRAM_PUB_PA       0x40208000
  50 #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
  51 #define OMAP4_SRAM_PA           0x40300000
  52 #define OMAP4_SRAM_VA           0xfe400000
  53 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
  54 #define OMAP4_SRAM_PUB_VA       (OMAP4_SRAM_VA + 0x4000)
  55
  56 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  57 #define SRAM_BOOTLOADER_SZ      0x00
  58 #else
  59 #define SRAM_BOOTLOADER_SZ      0x80
  60 #endif
  61
  62 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
  63 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
  64 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
  65
  66 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
  67 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
  68 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
  69 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
  70 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
  71 #define OMAP34XX_VA_CONTROL_STAT        OMAP2_L4_IO_ADDRESS(0x480022F0)
  72
  73 #define GP_DEVICE               0x300
  74
  75 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  76
  77 static unsigned long omap_sram_start;
  78 static unsigned long omap_sram_base;
  79 static unsigned long omap_sram_size;
  80 static unsigned long omap_sram_ceil;
  81
  82 extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
  83                                          unsigned long sram_vstart,
  84                                          unsigned long sram_size,
  85                                          unsigned long pstart_avail,
  86                                          unsigned long size_avail);
  87
  88 /*
  89  * Depending on the target RAMFS firewall setup, the public usable amount of
  90  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  91  * device allows ARM11 but not other initiators for full size. This
  92  * functionality seems ok until some nice security API happens.
  93  */
  94 static int is_sram_locked(void)
  95 {
  96         if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
  97                 /* RAMFW: R/W access to all initiators for all qualifier sets */
  98                 if (cpu_is_omap242x()) {
  99                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
 100                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
 101                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
 102                 }
 103                 if (cpu_is_omap34xx()) {
 104                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
 105                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
 106                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
 107                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
 108                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
 109                 }
 110                 return 0;
 111         } else
 112                 return 1; /* assume locked with no PPA or security driver */
 113 }
 114
 115 /*
 116  * The amount of SRAM depends on the core type.
 117  * Note that we cannot try to test for SRAM here because writes
 118  * to secure SRAM will hang the system. Also the SRAM is not
 119  * yet mapped at this point.
 120  */
 121 void __init omap_detect_sram(void)
 122 {
 123         unsigned long reserved;
 124
 125         if (cpu_class_is_omap2()) {
 126                 if (is_sram_locked()) {
 127                         if (cpu_is_omap34xx()) {
 128                                 omap_sram_base = OMAP3_SRAM_PUB_VA;
 129                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
 130                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
 131                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
 132                                         omap_sram_size = 0x7000; /* 28K */
 133                                 } else {
 134                                         omap_sram_size = 0x8000; /* 32K */
 135                                 }
 136                         } else if (cpu_is_omap44xx()) {
 137                                 omap_sram_base = OMAP4_SRAM_PUB_VA;
 138                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
 139                                 omap_sram_size = 0xa000; /* 40K */
 140                         } else {
 141                                 omap_sram_base = OMAP2_SRAM_PUB_VA;
 142                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
 143                                 omap_sram_size = 0x800; /* 2K */
 144                         }
 145                 } else {
 146                         if (cpu_is_omap34xx()) {
 147                                 omap_sram_base = OMAP3_SRAM_VA;
 148                                 omap_sram_start = OMAP3_SRAM_PA;
 149                                 omap_sram_size = 0x10000; /* 64K */
 150                         } else if (cpu_is_omap44xx()) {
 151                                 omap_sram_base = OMAP4_SRAM_VA;
 152                                 omap_sram_start = OMAP4_SRAM_PA;
 153                                 omap_sram_size = 0xe000; /* 56K */
 154                         } else {
 155                                 omap_sram_base = OMAP2_SRAM_VA;
 156                                 omap_sram_start = OMAP2_SRAM_PA;
 157                                 if (cpu_is_omap242x())
 158                                         omap_sram_size = 0xa0000; /* 640K */
 159                                 else if (cpu_is_omap243x())
 160                                         omap_sram_size = 0x10000; /* 64K */
 161                         }
 162                 }
 163         } else {
 164                 omap_sram_base = OMAP1_SRAM_VA;
 165                 omap_sram_start = OMAP1_SRAM_PA;
 166
 167                 if (cpu_is_omap7xx())
 168                         omap_sram_size = 0x32000;       /* 200K */
 169                 else if (cpu_is_omap15xx())
 170                         omap_sram_size = 0x30000;       /* 192K */
 171                 else if (cpu_is_omap1610() || cpu_is_omap1621() ||
 172                      cpu_is_omap1710())
 173                         omap_sram_size = 0x4000;        /* 16K */
 174                 else if (cpu_is_omap1611())
 175                         omap_sram_size = 0x3e800;       /* 250K */
 176                 else {
 177                         printk(KERN_ERR "Could not detect SRAM size\n");
 178                         omap_sram_size = 0x4000;
 179                 }
 180         }
 181         reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
 182                                        omap_sram_size,
 183                                        omap_sram_start + SRAM_BOOTLOADER_SZ,
 184                                        omap_sram_size - SRAM_BOOTLOADER_SZ);
 185         omap_sram_size -= reserved;
 186
 187         reserved = omap_vram_reserve_sram(omap_sram_start, omap_sram_base,
 188                         omap_sram_size,
 189                         omap_sram_start + SRAM_BOOTLOADER_SZ,
 190                         omap_sram_size - SRAM_BOOTLOADER_SZ);
 191         omap_sram_size -= reserved;
 192
 193         omap_sram_ceil = omap_sram_base + omap_sram_size;
 194 }
 195
 196 static struct map_desc omap_sram_io_desc[] __initdata = {
 197         {       /* .length gets filled in at runtime */
 198                 .virtual        = OMAP1_SRAM_VA,
 199                 .pfn            = __phys_to_pfn(OMAP1_SRAM_PA),
 200                 .type           = MT_MEMORY
 201         }
 202 };
 203
 204 /*
 205  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 206  */
 207 void __init omap_map_sram(void)
 208 {
 209         unsigned long base;
 210
 211         if (omap_sram_size == 0)
 212                 return;
 213
 214         if (cpu_is_omap24xx()) {
 215                 omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
 216
 217                 base = OMAP2_SRAM_PA;
 218                 base = ROUND_DOWN(base, PAGE_SIZE);
 219                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 220         }
 221
 222         if (cpu_is_omap34xx()) {
 223                 omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
 224                 base = OMAP3_SRAM_PA;
 225                 base = ROUND_DOWN(base, PAGE_SIZE);
 226                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 227
 228                 /*
 229                  * SRAM must be marked as non-cached on OMAP3 since the
 230                  * CORE DPLL M2 divider change code (in SRAM) runs with the
 231                  * SDRAM controller disabled, and if it is marked cached,
 232                  * the ARM may attempt to write cache lines back to SDRAM
 233                  * which will cause the system to hang.
 234                  */
 235                 omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
 236         }
 237
 238         if (cpu_is_omap44xx()) {
 239                 omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
 240                 base = OMAP4_SRAM_PA;
 241                 base = ROUND_DOWN(base, PAGE_SIZE);
 242                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 243         }
 244         omap_sram_io_desc[0].length = 1024 * 1024;      /* Use section desc */
 245         iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
 246
 247         printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
 248         __pfn_to_phys(omap_sram_io_desc[0].pfn),
 249         omap_sram_io_desc[0].virtual,
 250                omap_sram_io_desc[0].length);
 251
 252         /*
 253          * Normally devicemaps_init() would flush caches and tlb after
 254          * mdesc->map_io(), but since we're called from map_io(), we
 255          * must do it here.
 256          */
 257         local_flush_tlb_all();
 258         flush_cache_all();
 259
 260         /*
 261          * Looks like we need to preserve some bootloader code at the
 262          * beginning of SRAM for jumping to flash for reboot to work...
 263          */
 264         memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
 265                omap_sram_size - SRAM_BOOTLOADER_SZ);
 266 }
 267
 268 void * omap_sram_push(void * start, unsigned long size)
 269 {
 270         if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
 271                 printk(KERN_ERR "Not enough space in SRAM\n");
 272                 return NULL;
 273         }
 274
 275         omap_sram_ceil -= size;
 276         omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
 277         memcpy((void *)omap_sram_ceil, start, size);
 278         flush_icache_range((unsigned long)omap_sram_ceil,
 279                 (unsigned long)(omap_sram_ceil + size));
 280
 281         return (void *)omap_sram_ceil;
 282 }
 283
 284 #ifdef CONFIG_ARCH_OMAP1
 285
 286 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 287
 288 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 289 {
 290         BUG_ON(!_omap_sram_reprogram_clock);
 291         _omap_sram_reprogram_clock(dpllctl, ckctl);
 292 }
 293
 294 int __init omap1_sram_init(void)
 295 {
 296         _omap_sram_reprogram_clock =
 297                         omap_sram_push(omap1_sram_reprogram_clock,
 298                                         omap1_sram_reprogram_clock_sz);
 299
 300         return 0;
 301 }
 302
 303 #else
 304 #define omap1_sram_init()       do {} while (0)
 305 #endif
 306
 307 #if defined(CONFIG_ARCH_OMAP2)
 308
 309 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 310                               u32 base_cs, u32 force_unlock);
 311
 312 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 313                    u32 base_cs, u32 force_unlock)
 314 {
 315         BUG_ON(!_omap2_sram_ddr_init);
 316         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 317                              base_cs, force_unlock);
 318 }
 319
 320 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 321                                           u32 mem_type);
 322
 323 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 324 {
 325         BUG_ON(!_omap2_sram_reprogram_sdrc);
 326         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 327 }
 328
 329 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 330
 331 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 332 {
 333         BUG_ON(!_omap2_set_prcm);
 334         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 335 }
 336 #endif
 337
 338 #ifdef CONFIG_ARCH_OMAP2420
 339 int __init omap242x_sram_init(void)
 340 {
 341         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
 342                                         omap242x_sram_ddr_init_sz);
 343
 344         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
 345                                             omap242x_sram_reprogram_sdrc_sz);
 346
 347         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
 348                                          omap242x_sram_set_prcm_sz);
 349
 350         return 0;
 351 }
 352 #else
 353 static inline int omap242x_sram_init(void)
 354 {
 355         return 0;
 356 }
 357 #endif
 358
 359 #ifdef CONFIG_ARCH_OMAP2430
 360 int __init omap243x_sram_init(void)
 361 {
 362         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
 363                                         omap243x_sram_ddr_init_sz);
 364
 365         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
 366                                             omap243x_sram_reprogram_sdrc_sz);
 367
 368         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
 369                                          omap243x_sram_set_prcm_sz);
 370
 371         return 0;
 372 }
 373 #else
 374 static inline int omap243x_sram_init(void)
 375 {
 376         return 0;
 377 }
 378 #endif
 379
 380 #ifdef CONFIG_ARCH_OMAP3
 381
 382 static u32 (*_omap3_sram_configure_core_dpll)(
 383                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
 384                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 385                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 386                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 387                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 388
 389 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
 390                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 391                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 392                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 393                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 394 {
 395         BUG_ON(!_omap3_sram_configure_core_dpll);
 396         return _omap3_sram_configure_core_dpll(
 397                         m2, unlock_dll, f, inc,
 398                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
 399                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
 400                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
 401                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 402 }
 403
 404 #ifdef CONFIG_PM
 405 void omap3_sram_restore_context(void)
 406 {
 407         omap_sram_ceil = omap_sram_base + omap_sram_size;
 408
 409         _omap3_sram_configure_core_dpll =
 410                 omap_sram_push(omap3_sram_configure_core_dpll,
 411                                omap3_sram_configure_core_dpll_sz);
 412         omap_push_sram_idle();
 413 }
 414 #endif /* CONFIG_PM */
 415
 416 int __init omap34xx_sram_init(void)
 417 {
 418         _omap3_sram_configure_core_dpll =
 419                 omap_sram_push(omap3_sram_configure_core_dpll,
 420                                omap3_sram_configure_core_dpll_sz);
 421         omap_push_sram_idle();
 422         return 0;
 423 }
 424 #else
 425 static inline int omap34xx_sram_init(void)
 426 {
 427         return 0;
 428 }
 429 #endif
 430
 431 #ifdef CONFIG_ARCH_OMAP4
 432 int __init omap44xx_sram_init(void)
 433 {
 434         printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
 435
 436         return -ENODEV;
 437 }
 438 #else
 439 static inline int omap44xx_sram_init(void)
 440 {
 441         return 0;
 442 }
 443 #endif
 444
 445 int __init omap_sram_init(void)
 446 {
 447         omap_detect_sram();
 448         omap_map_sram();
 449
 450         if (!(cpu_class_is_omap2()))
 451                 omap1_sram_init();
 452         else if (cpu_is_omap242x())
 453                 omap242x_sram_init();
 454         else if (cpu_is_omap2430())
 455                 omap243x_sram_init();
 456         else if (cpu_is_omap34xx())
 457                 omap34xx_sram_init();
 458         else if (cpu_is_omap44xx())
 459                 omap44xx_sram_init();
 460
 461         return 0;
 462 }