2 * linux/arch/arm/plat-omap/sram.c
4 * OMAP SRAM detection and management
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
22 #include <linux/omapfb.h>
25 #include <asm/cacheflush.h>
27 #include <asm/mach/map.h>
29 #include <plat/sram.h>
30 #include <plat/board.h>
32 #include <plat/vram.h>
36 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
37 # include "../mach-omap2/prm.h"
38 # include "../mach-omap2/cm.h"
39 # include "../mach-omap2/sdrc.h"
42 #define OMAP1_SRAM_PA 0x20000000
43 #define OMAP1_SRAM_VA VMALLOC_END
44 #define OMAP2_SRAM_PA 0x40200000
45 #define OMAP2_SRAM_PUB_PA 0x4020f800
46 #define OMAP2_SRAM_VA 0xfe400000
47 #define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800)
48 #define OMAP3_SRAM_PA 0x40200000
49 #define OMAP3_SRAM_VA 0xfe400000
50 #define OMAP3_SRAM_PUB_PA 0x40208000
51 #define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000)
52 #define OMAP4_SRAM_PA 0x40300000
53 #define OMAP4_SRAM_VA 0xfe400000
54 #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
55 #define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000)
57 #if defined(CONFIG_ARCH_OMAP2PLUS)
58 #define SRAM_BOOTLOADER_SZ 0x00
60 #define SRAM_BOOTLOADER_SZ 0x80
63 #define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
64 #define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
65 #define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
67 #define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
68 #define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
69 #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
70 #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
71 #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
73 #define GP_DEVICE 0x300
75 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
77 static unsigned long omap_sram_start;
78 static unsigned long omap_sram_base;
79 static unsigned long omap_sram_size;
80 static unsigned long omap_sram_ceil;
83 * Depending on the target RAMFS firewall setup, the public usable amount of
84 * SRAM varies. The default accessible size for all device types is 2k. A GP
85 * device allows ARM11 but not other initiators for full size. This
86 * functionality seems ok until some nice security API happens.
88 static int is_sram_locked(void)
90 if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
91 /* RAMFW: R/W access to all initiators for all qualifier sets */
92 if (cpu_is_omap242x()) {
93 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
94 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
95 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
97 if (cpu_is_omap34xx()) {
98 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
99 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
100 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
101 __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
102 __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
106 return 1; /* assume locked with no PPA or security driver */
110 * The amount of SRAM depends on the core type.
111 * Note that we cannot try to test for SRAM here because writes
112 * to secure SRAM will hang the system. Also the SRAM is not
113 * yet mapped at this point.
115 static void __init omap_detect_sram(void)
117 unsigned long reserved;
119 if (cpu_class_is_omap2()) {
120 if (is_sram_locked()) {
121 if (cpu_is_omap34xx()) {
122 omap_sram_base = OMAP3_SRAM_PUB_VA;
123 omap_sram_start = OMAP3_SRAM_PUB_PA;
124 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
125 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
126 omap_sram_size = 0x7000; /* 28K */
128 omap_sram_size = 0x8000; /* 32K */
130 } else if (cpu_is_omap44xx()) {
131 omap_sram_base = OMAP4_SRAM_PUB_VA;
132 omap_sram_start = OMAP4_SRAM_PUB_PA;
133 omap_sram_size = 0xa000; /* 40K */
135 omap_sram_base = OMAP2_SRAM_PUB_VA;
136 omap_sram_start = OMAP2_SRAM_PUB_PA;
137 omap_sram_size = 0x800; /* 2K */
140 if (cpu_is_omap34xx()) {
141 omap_sram_base = OMAP3_SRAM_VA;
142 omap_sram_start = OMAP3_SRAM_PA;
143 omap_sram_size = 0x10000; /* 64K */
144 } else if (cpu_is_omap44xx()) {
145 omap_sram_base = OMAP4_SRAM_VA;
146 omap_sram_start = OMAP4_SRAM_PA;
147 omap_sram_size = 0xe000; /* 56K */
149 omap_sram_base = OMAP2_SRAM_VA;
150 omap_sram_start = OMAP2_SRAM_PA;
151 if (cpu_is_omap242x())
152 omap_sram_size = 0xa0000; /* 640K */
153 else if (cpu_is_omap243x())
154 omap_sram_size = 0x10000; /* 64K */
158 omap_sram_base = OMAP1_SRAM_VA;
159 omap_sram_start = OMAP1_SRAM_PA;
161 if (cpu_is_omap7xx())
162 omap_sram_size = 0x32000; /* 200K */
163 else if (cpu_is_omap15xx())
164 omap_sram_size = 0x30000; /* 192K */
165 else if (cpu_is_omap1610() || cpu_is_omap1621() ||
167 omap_sram_size = 0x4000; /* 16K */
168 else if (cpu_is_omap1611())
169 omap_sram_size = 0x3e800; /* 250K */
171 printk(KERN_ERR "Could not detect SRAM size\n");
172 omap_sram_size = 0x4000;
175 reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
177 omap_sram_start + SRAM_BOOTLOADER_SZ,
178 omap_sram_size - SRAM_BOOTLOADER_SZ);
179 omap_sram_size -= reserved;
181 reserved = omap_vram_reserve_sram(omap_sram_start, omap_sram_base,
183 omap_sram_start + SRAM_BOOTLOADER_SZ,
184 omap_sram_size - SRAM_BOOTLOADER_SZ);
185 omap_sram_size -= reserved;
187 omap_sram_ceil = omap_sram_base + omap_sram_size;
190 static struct map_desc omap_sram_io_desc[] __initdata = {
191 { /* .length gets filled in at runtime */
192 .virtual = OMAP1_SRAM_VA,
193 .pfn = __phys_to_pfn(OMAP1_SRAM_PA),
199 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
201 static void __init omap_map_sram(void)
205 if (omap_sram_size == 0)
208 if (cpu_is_omap24xx()) {
209 omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
211 base = OMAP2_SRAM_PA;
212 base = ROUND_DOWN(base, PAGE_SIZE);
213 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
216 if (cpu_is_omap34xx()) {
217 omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
218 base = OMAP3_SRAM_PA;
219 base = ROUND_DOWN(base, PAGE_SIZE);
220 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
223 * SRAM must be marked as non-cached on OMAP3 since the
224 * CORE DPLL M2 divider change code (in SRAM) runs with the
225 * SDRAM controller disabled, and if it is marked cached,
226 * the ARM may attempt to write cache lines back to SDRAM
227 * which will cause the system to hang.
229 omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
232 if (cpu_is_omap44xx()) {
233 omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
234 base = OMAP4_SRAM_PA;
235 base = ROUND_DOWN(base, PAGE_SIZE);
236 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
238 omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
239 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
241 printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
242 __pfn_to_phys(omap_sram_io_desc[0].pfn),
243 omap_sram_io_desc[0].virtual,
244 omap_sram_io_desc[0].length);
247 * Normally devicemaps_init() would flush caches and tlb after
248 * mdesc->map_io(), but since we're called from map_io(), we
251 local_flush_tlb_all();
255 * Looks like we need to preserve some bootloader code at the
256 * beginning of SRAM for jumping to flash for reboot to work...
258 memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
259 omap_sram_size - SRAM_BOOTLOADER_SZ);
262 void * omap_sram_push(void * start, unsigned long size)
264 if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
265 printk(KERN_ERR "Not enough space in SRAM\n");
269 omap_sram_ceil -= size;
270 omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
271 memcpy((void *)omap_sram_ceil, start, size);
272 flush_icache_range((unsigned long)omap_sram_ceil,
273 (unsigned long)(omap_sram_ceil + size));
275 return (void *)omap_sram_ceil;
278 #ifdef CONFIG_ARCH_OMAP1
280 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
282 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
284 BUG_ON(!_omap_sram_reprogram_clock);
285 _omap_sram_reprogram_clock(dpllctl, ckctl);
288 int __init omap1_sram_init(void)
290 _omap_sram_reprogram_clock =
291 omap_sram_push(omap1_sram_reprogram_clock,
292 omap1_sram_reprogram_clock_sz);
298 #define omap1_sram_init() do {} while (0)
301 #if defined(CONFIG_ARCH_OMAP2)
303 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
304 u32 base_cs, u32 force_unlock);
306 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
307 u32 base_cs, u32 force_unlock)
309 BUG_ON(!_omap2_sram_ddr_init);
310 _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
311 base_cs, force_unlock);
314 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
317 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
319 BUG_ON(!_omap2_sram_reprogram_sdrc);
320 _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
323 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
325 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
327 BUG_ON(!_omap2_set_prcm);
328 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
332 #ifdef CONFIG_ARCH_OMAP2420
333 static int __init omap242x_sram_init(void)
335 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
336 omap242x_sram_ddr_init_sz);
338 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
339 omap242x_sram_reprogram_sdrc_sz);
341 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
342 omap242x_sram_set_prcm_sz);
347 static inline int omap242x_sram_init(void)
353 #ifdef CONFIG_ARCH_OMAP2430
354 static int __init omap243x_sram_init(void)
356 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
357 omap243x_sram_ddr_init_sz);
359 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
360 omap243x_sram_reprogram_sdrc_sz);
362 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
363 omap243x_sram_set_prcm_sz);
368 static inline int omap243x_sram_init(void)
374 #ifdef CONFIG_ARCH_OMAP3
376 static u32 (*_omap3_sram_configure_core_dpll)(
377 u32 m2, u32 unlock_dll, u32 f, u32 inc,
378 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
379 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
380 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
381 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
383 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
384 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
385 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
386 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
387 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
389 BUG_ON(!_omap3_sram_configure_core_dpll);
390 return _omap3_sram_configure_core_dpll(
391 m2, unlock_dll, f, inc,
392 sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
393 sdrc_actim_ctrl_b_0, sdrc_mr_0,
394 sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
395 sdrc_actim_ctrl_b_1, sdrc_mr_1);
399 void omap3_sram_restore_context(void)
401 omap_sram_ceil = omap_sram_base + omap_sram_size;
403 _omap3_sram_configure_core_dpll =
404 omap_sram_push(omap3_sram_configure_core_dpll,
405 omap3_sram_configure_core_dpll_sz);
406 omap_push_sram_idle();
408 #endif /* CONFIG_PM */
410 static int __init omap34xx_sram_init(void)
412 _omap3_sram_configure_core_dpll =
413 omap_sram_push(omap3_sram_configure_core_dpll,
414 omap3_sram_configure_core_dpll_sz);
415 omap_push_sram_idle();
419 static inline int omap34xx_sram_init(void)
425 #ifdef CONFIG_ARCH_OMAP4
426 static int __init omap44xx_sram_init(void)
428 printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
433 static inline int omap44xx_sram_init(void)
439 int __init omap_sram_init(void)
444 if (!(cpu_class_is_omap2()))
446 else if (cpu_is_omap242x())
447 omap242x_sram_init();
448 else if (cpu_is_omap2430())
449 omap243x_sram_init();
450 else if (cpu_is_omap34xx())
451 omap34xx_sram_init();
452 else if (cpu_is_omap44xx())
453 omap44xx_sram_init();