2 * arch/arm/plat-orion/gpio.c
4 * Marvell Orion SoC GPIO handling.
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/irq.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/bitops.h>
18 #include <linux/gpio.h>
21 * GPIO unit register offsets.
23 #define GPIO_OUT_OFF 0x0000
24 #define GPIO_IO_CONF_OFF 0x0004
25 #define GPIO_BLINK_EN_OFF 0x0008
26 #define GPIO_IN_POL_OFF 0x000c
27 #define GPIO_DATA_IN_OFF 0x0010
28 #define GPIO_EDGE_CAUSE_OFF 0x0014
29 #define GPIO_EDGE_MASK_OFF 0x0018
30 #define GPIO_LEVEL_MASK_OFF 0x001c
32 struct orion_gpio_chip {
33 struct gpio_chip chip;
36 unsigned long valid_input;
37 unsigned long valid_output;
39 int secondary_irq_base;
42 static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
44 return ochip->base + GPIO_OUT_OFF;
47 static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
49 return ochip->base + GPIO_IO_CONF_OFF;
52 static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
54 return ochip->base + GPIO_BLINK_EN_OFF;
57 static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
59 return ochip->base + GPIO_IN_POL_OFF;
62 static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
64 return ochip->base + GPIO_DATA_IN_OFF;
67 static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
69 return ochip->base + GPIO_EDGE_CAUSE_OFF;
72 static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
74 return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
77 static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
79 return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
83 static struct orion_gpio_chip orion_gpio_chips[2];
84 static int orion_gpio_chip_count;
87 __set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
91 u = readl(GPIO_IO_CONF(ochip));
96 writel(u, GPIO_IO_CONF(ochip));
99 static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
103 u = readl(GPIO_OUT(ochip));
108 writel(u, GPIO_OUT(ochip));
112 __set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
116 u = readl(GPIO_BLINK_EN(ochip));
121 writel(u, GPIO_BLINK_EN(ochip));
125 orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
127 if (pin >= ochip->chip.ngpio)
130 if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
133 if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
139 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
144 * GENERIC_GPIO primitives.
146 static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
148 struct orion_gpio_chip *ochip =
149 container_of(chip, struct orion_gpio_chip, chip);
151 if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
152 orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
158 static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
160 struct orion_gpio_chip *ochip =
161 container_of(chip, struct orion_gpio_chip, chip);
164 if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
167 spin_lock_irqsave(&ochip->lock, flags);
168 __set_direction(ochip, pin, 1);
169 spin_unlock_irqrestore(&ochip->lock, flags);
174 static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
176 struct orion_gpio_chip *ochip =
177 container_of(chip, struct orion_gpio_chip, chip);
180 if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
181 val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
183 val = readl(GPIO_OUT(ochip));
186 return (val >> pin) & 1;
190 orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
192 struct orion_gpio_chip *ochip =
193 container_of(chip, struct orion_gpio_chip, chip);
196 if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
199 spin_lock_irqsave(&ochip->lock, flags);
200 __set_blinking(ochip, pin, 0);
201 __set_level(ochip, pin, value);
202 __set_direction(ochip, pin, 0);
203 spin_unlock_irqrestore(&ochip->lock, flags);
208 static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
210 struct orion_gpio_chip *ochip =
211 container_of(chip, struct orion_gpio_chip, chip);
214 spin_lock_irqsave(&ochip->lock, flags);
215 __set_level(ochip, pin, value);
216 spin_unlock_irqrestore(&ochip->lock, flags);
219 static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
221 struct orion_gpio_chip *ochip =
222 container_of(chip, struct orion_gpio_chip, chip);
224 return ochip->secondary_irq_base + pin;
229 * Orion-specific GPIO API extensions.
231 static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
235 for (i = 0; i < orion_gpio_chip_count; i++) {
236 struct orion_gpio_chip *ochip = orion_gpio_chips + i;
237 struct gpio_chip *chip = &ochip->chip;
239 if (pin >= chip->base && pin < chip->base + chip->ngpio)
246 void __init orion_gpio_set_unused(unsigned pin)
248 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
253 pin -= ochip->chip.base;
255 /* Configure as output, drive low. */
256 __set_level(ochip, pin, 0);
257 __set_direction(ochip, pin, 0);
260 void __init orion_gpio_set_valid(unsigned pin, int mode)
262 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
267 pin -= ochip->chip.base;
270 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
272 if (mode & GPIO_INPUT_OK)
273 __set_bit(pin, &ochip->valid_input);
275 __clear_bit(pin, &ochip->valid_input);
277 if (mode & GPIO_OUTPUT_OK)
278 __set_bit(pin, &ochip->valid_output);
280 __clear_bit(pin, &ochip->valid_output);
283 void orion_gpio_set_blink(unsigned pin, int blink)
285 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
291 spin_lock_irqsave(&ochip->lock, flags);
292 __set_level(ochip, pin, 0);
293 __set_blinking(ochip, pin, blink);
294 spin_unlock_irqrestore(&ochip->lock, flags);
296 EXPORT_SYMBOL(orion_gpio_set_blink);
299 /*****************************************************************************
302 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
303 * value of the line or the opposite value.
305 * Level IRQ handlers: DATA_IN is used directly as cause register.
306 * Interrupt are masked by LEVEL_MASK registers.
307 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
308 * Interrupt are masked by EDGE_MASK registers.
309 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
310 * the polarity to catch the next line transaction.
311 * This is a race condition that might not perfectly
312 * work on some use cases.
314 * Every eight GPIO lines are grouped (OR'ed) before going up to main
318 * data-in /--------| |-----| |----\
319 * -----| |----- ---- to main cause reg
320 * X \----------------| |----/
321 * polarity LEVEL mask
323 ****************************************************************************/
325 static int gpio_irq_set_type(struct irq_data *d, u32 type)
327 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
328 struct irq_chip_type *ct = irq_data_get_chip_type(d);
329 struct orion_gpio_chip *ochip = gc->private;
333 pin = d->irq - gc->irq_base;
335 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
337 printk(KERN_ERR "orion gpio_irq_set_type failed "
338 "(irq %d, pin %d).\n", d->irq, pin);
342 type &= IRQ_TYPE_SENSE_MASK;
343 if (type == IRQ_TYPE_NONE)
346 /* Check if we need to change chip and handler */
347 if (!(ct->type & type))
348 if (irq_setup_alt_chip(d, type))
352 * Configure interrupt polarity.
354 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
355 u = readl(GPIO_IN_POL(ochip));
357 writel(u, GPIO_IN_POL(ochip));
358 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
359 u = readl(GPIO_IN_POL(ochip));
361 writel(u, GPIO_IN_POL(ochip));
362 } else if (type == IRQ_TYPE_EDGE_BOTH) {
365 v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
368 * set initial polarity based on current input level
370 u = readl(GPIO_IN_POL(ochip));
372 u |= 1 << pin; /* falling */
374 u &= ~(1 << pin); /* rising */
375 writel(u, GPIO_IN_POL(ochip));
381 void __init orion_gpio_init(int gpio_base, int ngpio,
382 u32 base, int mask_offset, int secondary_irq_base)
384 struct orion_gpio_chip *ochip;
385 struct irq_chip_generic *gc;
386 struct irq_chip_type *ct;
388 if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
391 ochip = orion_gpio_chips + orion_gpio_chip_count;
392 ochip->chip.label = "orion_gpio";
393 ochip->chip.request = orion_gpio_request;
394 ochip->chip.direction_input = orion_gpio_direction_input;
395 ochip->chip.get = orion_gpio_get;
396 ochip->chip.direction_output = orion_gpio_direction_output;
397 ochip->chip.set = orion_gpio_set;
398 ochip->chip.to_irq = orion_gpio_to_irq;
399 ochip->chip.base = gpio_base;
400 ochip->chip.ngpio = ngpio;
401 ochip->chip.can_sleep = 0;
402 spin_lock_init(&ochip->lock);
403 ochip->base = (void __iomem *)base;
404 ochip->valid_input = 0;
405 ochip->valid_output = 0;
406 ochip->mask_offset = mask_offset;
407 ochip->secondary_irq_base = secondary_irq_base;
409 gpiochip_add(&ochip->chip);
411 orion_gpio_chip_count++;
414 * Mask and clear GPIO interrupts.
416 writel(0, GPIO_EDGE_CAUSE(ochip));
417 writel(0, GPIO_EDGE_MASK(ochip));
418 writel(0, GPIO_LEVEL_MASK(ochip));
420 gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base,
421 ochip->base, handle_level_irq);
425 ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
426 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
427 ct->chip.irq_mask = irq_gc_mask_clr_bit;
428 ct->chip.irq_unmask = irq_gc_mask_set_bit;
429 ct->chip.irq_set_type = gpio_irq_set_type;
432 ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
433 ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
434 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
435 ct->chip.irq_ack = irq_gc_ack_clr_bit;
436 ct->chip.irq_mask = irq_gc_mask_clr_bit;
437 ct->chip.irq_unmask = irq_gc_mask_set_bit;
438 ct->chip.irq_set_type = gpio_irq_set_type;
439 ct->handler = handle_edge_irq;
441 irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
442 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
445 void orion_gpio_irq_handler(int pinoff)
447 struct orion_gpio_chip *ochip;
451 ochip = orion_gpio_chip_find(pinoff);
455 cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
456 cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
458 for (i = 0; i < ochip->chip.ngpio; i++) {
461 irq = ochip->secondary_irq_base + i;
463 if (!(cause & (1 << i)))
466 type = irqd_get_trigger_type(irq_get_irq_data(irq));
467 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
468 /* Swap polarity (race with GPIO line) */
471 polarity = readl(GPIO_IN_POL(ochip));
473 writel(polarity, GPIO_IN_POL(ochip));
475 generic_handle_irq(irq);