1 /* linux/arch/arm/plat-s3c24xx/clock.c
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C24XX Core clock control support
8 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
10 ** Copyright (C) 2004 ARM Limited.
11 ** Written by Deep Blue Solutions Limited.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/errno.h>
34 #include <linux/err.h>
35 #include <linux/platform_device.h>
36 #include <linux/sysdev.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/clk.h>
40 #include <linux/spinlock.h>
41 #include <linux/delay.h>
44 #include <mach/hardware.h>
47 #include <mach/regs-clock.h>
48 #include <mach/regs-gpio.h>
50 #include <plat/cpu-freq.h>
52 #include <plat/clock.h>
56 /* clock information */
58 static LIST_HEAD(clocks);
60 /* We originally used an mutex here, but some contexts (see resume)
61 * are calling functions such as clk_set_parent() with IRQs disabled
62 * causing an BUG to be triggered.
64 DEFINE_SPINLOCK(clocks_lock);
66 /* enable and disable calls for use with the clk struct */
68 static int clk_null_enable(struct clk *clk, int enable)
75 struct clk *clk_get(struct device *dev, const char *id)
78 struct clk *clk = ERR_PTR(-ENOENT);
81 if (dev == NULL || dev->bus != &platform_bus_type)
84 idno = to_platform_device(dev)->id;
86 spin_lock(&clocks_lock);
88 list_for_each_entry(p, &clocks, list) {
90 strcmp(id, p->name) == 0 &&
91 try_module_get(p->owner)) {
97 /* check for the case where a device was supplied, but the
98 * clock that was being searched for is not device specific */
101 list_for_each_entry(p, &clocks, list) {
102 if (p->id == -1 && strcmp(id, p->name) == 0 &&
103 try_module_get(p->owner)) {
110 spin_unlock(&clocks_lock);
114 void clk_put(struct clk *clk)
116 module_put(clk->owner);
119 int clk_enable(struct clk *clk)
121 if (IS_ERR(clk) || clk == NULL)
124 clk_enable(clk->parent);
126 spin_lock(&clocks_lock);
128 if ((clk->usage++) == 0)
129 (clk->enable)(clk, 1);
131 spin_unlock(&clocks_lock);
135 void clk_disable(struct clk *clk)
137 if (IS_ERR(clk) || clk == NULL)
140 spin_lock(&clocks_lock);
142 if ((--clk->usage) == 0)
143 (clk->enable)(clk, 0);
145 spin_unlock(&clocks_lock);
146 clk_disable(clk->parent);
150 unsigned long clk_get_rate(struct clk *clk)
158 if (clk->get_rate != NULL)
159 return (clk->get_rate)(clk);
161 if (clk->parent != NULL)
162 return clk_get_rate(clk->parent);
167 long clk_round_rate(struct clk *clk, unsigned long rate)
169 if (!IS_ERR(clk) && clk->round_rate)
170 return (clk->round_rate)(clk, rate);
175 int clk_set_rate(struct clk *clk, unsigned long rate)
182 /* We do not default just do a clk->rate = rate as
183 * the clock may have been made this way by choice.
186 WARN_ON(clk->set_rate == NULL);
188 if (clk->set_rate == NULL)
191 spin_lock(&clocks_lock);
192 ret = (clk->set_rate)(clk, rate);
193 spin_unlock(&clocks_lock);
198 struct clk *clk_get_parent(struct clk *clk)
203 int clk_set_parent(struct clk *clk, struct clk *parent)
210 spin_lock(&clocks_lock);
213 ret = (clk->set_parent)(clk, parent);
215 spin_unlock(&clocks_lock);
220 EXPORT_SYMBOL(clk_get);
221 EXPORT_SYMBOL(clk_put);
222 EXPORT_SYMBOL(clk_enable);
223 EXPORT_SYMBOL(clk_disable);
224 EXPORT_SYMBOL(clk_get_rate);
225 EXPORT_SYMBOL(clk_round_rate);
226 EXPORT_SYMBOL(clk_set_rate);
227 EXPORT_SYMBOL(clk_get_parent);
228 EXPORT_SYMBOL(clk_set_parent);
232 static int clk_default_setrate(struct clk *clk, unsigned long rate)
238 struct clk clk_xtal = {
246 struct clk clk_mpll = {
249 .set_rate = clk_default_setrate,
252 struct clk clk_upll = {
265 .set_rate = clk_default_setrate,
274 .set_rate = clk_default_setrate,
283 .set_rate = clk_default_setrate,
286 struct clk clk_usb_bus = {
295 struct clk s3c24xx_uclk = {
300 /* initialise the clock system */
302 int s3c24xx_register_clock(struct clk *clk)
304 clk->owner = THIS_MODULE;
306 if (clk->enable == NULL)
307 clk->enable = clk_null_enable;
309 /* add to the list of available clocks */
311 spin_lock(&clocks_lock);
312 list_add(&clk->list, &clocks);
313 spin_unlock(&clocks_lock);
318 int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
322 for (; nr_clks > 0; nr_clks--, clks++) {
323 if (s3c24xx_register_clock(*clks) < 0)
330 /* initalise all the clocks */
332 void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
336 clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
339 clk_mpll.rate = fclk;
345 int __init s3c24xx_register_baseclocks(unsigned long xtal)
347 printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
349 clk_xtal.rate = xtal;
351 /* register our clocks */
353 if (s3c24xx_register_clock(&clk_xtal) < 0)
354 printk(KERN_ERR "failed to register master xtal\n");
356 if (s3c24xx_register_clock(&clk_mpll) < 0)
357 printk(KERN_ERR "failed to register mpll clock\n");
359 if (s3c24xx_register_clock(&clk_upll) < 0)
360 printk(KERN_ERR "failed to register upll clock\n");
362 if (s3c24xx_register_clock(&clk_f) < 0)
363 printk(KERN_ERR "failed to register cpu fclk\n");
365 if (s3c24xx_register_clock(&clk_h) < 0)
366 printk(KERN_ERR "failed to register cpu hclk\n");
368 if (s3c24xx_register_clock(&clk_p) < 0)
369 printk(KERN_ERR "failed to register cpu pclk\n");