1 /* linux/arch/arm/plat-s3c24xx/clock.c
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C24XX Core clock control support
8 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
10 ** Copyright (C) 2004 ARM Limited.
11 ** Written by Deep Blue Solutions Limited.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/errno.h>
34 #include <linux/err.h>
35 #include <linux/platform_device.h>
36 #include <linux/sysdev.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/clk.h>
40 #include <linux/spinlock.h>
41 #include <linux/delay.h>
44 #include <mach/hardware.h>
47 #include <mach/regs-clock.h>
48 #include <mach/regs-gpio.h>
50 #include <plat/clock.h>
54 /* clock information */
56 static LIST_HEAD(clocks);
58 /* We originally used an mutex here, but some contexts (see resume)
59 * are calling functions such as clk_set_parent() with IRQs disabled
60 * causing an BUG to be triggered.
62 DEFINE_SPINLOCK(clocks_lock);
64 /* enable and disable calls for use with the clk struct */
66 static int clk_null_enable(struct clk *clk, int enable)
73 struct clk *clk_get(struct device *dev, const char *id)
76 struct clk *clk = ERR_PTR(-ENOENT);
79 if (dev == NULL || dev->bus != &platform_bus_type)
82 idno = to_platform_device(dev)->id;
84 spin_lock(&clocks_lock);
86 list_for_each_entry(p, &clocks, list) {
88 strcmp(id, p->name) == 0 &&
89 try_module_get(p->owner)) {
95 /* check for the case where a device was supplied, but the
96 * clock that was being searched for is not device specific */
99 list_for_each_entry(p, &clocks, list) {
100 if (p->id == -1 && strcmp(id, p->name) == 0 &&
101 try_module_get(p->owner)) {
108 spin_unlock(&clocks_lock);
112 void clk_put(struct clk *clk)
114 module_put(clk->owner);
117 int clk_enable(struct clk *clk)
119 if (IS_ERR(clk) || clk == NULL)
122 clk_enable(clk->parent);
124 spin_lock(&clocks_lock);
126 if ((clk->usage++) == 0)
127 (clk->enable)(clk, 1);
129 spin_unlock(&clocks_lock);
133 void clk_disable(struct clk *clk)
135 if (IS_ERR(clk) || clk == NULL)
138 spin_lock(&clocks_lock);
140 if ((--clk->usage) == 0)
141 (clk->enable)(clk, 0);
143 spin_unlock(&clocks_lock);
144 clk_disable(clk->parent);
148 unsigned long clk_get_rate(struct clk *clk)
156 if (clk->get_rate != NULL)
157 return (clk->get_rate)(clk);
159 if (clk->parent != NULL)
160 return clk_get_rate(clk->parent);
165 long clk_round_rate(struct clk *clk, unsigned long rate)
167 if (!IS_ERR(clk) && clk->round_rate)
168 return (clk->round_rate)(clk, rate);
173 int clk_set_rate(struct clk *clk, unsigned long rate)
180 /* We do not default just do a clk->rate = rate as
181 * the clock may have been made this way by choice.
184 WARN_ON(clk->set_rate == NULL);
186 if (clk->set_rate == NULL)
189 spin_lock(&clocks_lock);
190 ret = (clk->set_rate)(clk, rate);
191 spin_unlock(&clocks_lock);
196 struct clk *clk_get_parent(struct clk *clk)
201 int clk_set_parent(struct clk *clk, struct clk *parent)
208 spin_lock(&clocks_lock);
211 ret = (clk->set_parent)(clk, parent);
213 spin_unlock(&clocks_lock);
218 EXPORT_SYMBOL(clk_get);
219 EXPORT_SYMBOL(clk_put);
220 EXPORT_SYMBOL(clk_enable);
221 EXPORT_SYMBOL(clk_disable);
222 EXPORT_SYMBOL(clk_get_rate);
223 EXPORT_SYMBOL(clk_round_rate);
224 EXPORT_SYMBOL(clk_set_rate);
225 EXPORT_SYMBOL(clk_get_parent);
226 EXPORT_SYMBOL(clk_set_parent);
230 static int clk_default_setrate(struct clk *clk, unsigned long rate)
236 struct clk clk_xtal = {
244 struct clk clk_mpll = {
247 .set_rate = clk_default_setrate,
250 struct clk clk_upll = {
263 .set_rate = clk_default_setrate,
272 .set_rate = clk_default_setrate,
281 .set_rate = clk_default_setrate,
284 struct clk clk_usb_bus = {
293 struct clk s3c24xx_uclk = {
298 /* initialise the clock system */
300 int s3c24xx_register_clock(struct clk *clk)
302 clk->owner = THIS_MODULE;
304 if (clk->enable == NULL)
305 clk->enable = clk_null_enable;
307 /* add to the list of available clocks */
309 spin_lock(&clocks_lock);
310 list_add(&clk->list, &clocks);
311 spin_unlock(&clocks_lock);
316 int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
320 for (; nr_clks > 0; nr_clks--, clks++) {
321 if (s3c24xx_register_clock(*clks) < 0)
328 /* initalise all the clocks */
330 int __init s3c24xx_setup_clocks(unsigned long xtal,
335 printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
337 /* initialise the main system clocks */
339 clk_xtal.rate = xtal;
340 clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
342 clk_mpll.rate = fclk;
347 /* assume uart clocks are correctly setup */
349 /* register our clocks */
351 if (s3c24xx_register_clock(&clk_xtal) < 0)
352 printk(KERN_ERR "failed to register master xtal\n");
354 if (s3c24xx_register_clock(&clk_mpll) < 0)
355 printk(KERN_ERR "failed to register mpll clock\n");
357 if (s3c24xx_register_clock(&clk_upll) < 0)
358 printk(KERN_ERR "failed to register upll clock\n");
360 if (s3c24xx_register_clock(&clk_f) < 0)
361 printk(KERN_ERR "failed to register cpu fclk\n");
363 if (s3c24xx_register_clock(&clk_h) < 0)
364 printk(KERN_ERR "failed to register cpu hclk\n");
366 if (s3c24xx_register_clock(&clk_p) < 0)
367 printk(KERN_ERR "failed to register cpu pclk\n");