1 /* linux/arch/arm/plat-s3c24xx/cpu.c
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/interrupt.h>
28 #include <linux/ioport.h>
29 #include <linux/serial_core.h>
30 #include <linux/platform_device.h>
31 #include <linux/delay.h>
33 #include <linux/delay.h>
35 #include <mach/hardware.h>
37 #include <asm/cacheflush.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/map.h>
42 #include <mach/system-reset.h>
44 #include <mach/regs-gpio.h>
45 #include <plat/regs-serial.h>
48 #include <plat/devs.h>
49 #include <plat/clock.h>
50 #include <plat/s3c2400.h>
51 #include <plat/s3c2410.h>
52 #include <plat/s3c2412.h>
54 #include <plat/s3c2440.h>
55 #include <plat/s3c2442.h>
56 #include <plat/s3c2443.h>
58 /* table of supported CPUs */
60 static const char name_s3c2400[] = "S3C2400";
61 static const char name_s3c2410[] = "S3C2410";
62 static const char name_s3c2412[] = "S3C2412";
63 static const char name_s3c2440[] = "S3C2440";
64 static const char name_s3c2442[] = "S3C2442";
65 static const char name_s3c2443[] = "S3C2443";
66 static const char name_s3c2410a[] = "S3C2410A";
67 static const char name_s3c2440a[] = "S3C2440A";
69 static struct cpu_table cpu_ids[] __initdata = {
73 .map_io = s3c2410_map_io,
74 .init_clocks = s3c2410_init_clocks,
75 .init_uarts = s3c2410_init_uarts,
82 .map_io = s3c2410_map_io,
83 .init_clocks = s3c2410_init_clocks,
84 .init_uarts = s3c2410_init_uarts,
91 .map_io = s3c244x_map_io,
92 .init_clocks = s3c244x_init_clocks,
93 .init_uarts = s3c244x_init_uarts,
100 .map_io = s3c244x_map_io,
101 .init_clocks = s3c244x_init_clocks,
102 .init_uarts = s3c244x_init_uarts,
103 .init = s3c2440_init,
104 .name = name_s3c2440a
107 .idcode = 0x32440aaa,
108 .idmask = 0xffffffff,
109 .map_io = s3c244x_map_io,
110 .init_clocks = s3c244x_init_clocks,
111 .init_uarts = s3c244x_init_uarts,
112 .init = s3c2442_init,
116 .idcode = 0x32412001,
117 .idmask = 0xffffffff,
118 .map_io = s3c2412_map_io,
119 .init_clocks = s3c2412_init_clocks,
120 .init_uarts = s3c2412_init_uarts,
121 .init = s3c2412_init,
122 .name = name_s3c2412,
124 { /* a newer version of the s3c2412 */
125 .idcode = 0x32412003,
126 .idmask = 0xffffffff,
127 .map_io = s3c2412_map_io,
128 .init_clocks = s3c2412_init_clocks,
129 .init_uarts = s3c2412_init_uarts,
130 .init = s3c2412_init,
131 .name = name_s3c2412,
134 .idcode = 0x32443001,
135 .idmask = 0xffffffff,
136 .map_io = s3c2443_map_io,
137 .init_clocks = s3c2443_init_clocks,
138 .init_uarts = s3c2443_init_uarts,
139 .init = s3c2443_init,
140 .name = name_s3c2443,
143 .idcode = 0x0, /* S3C2400 doesn't have an idcode */
144 .idmask = 0xffffffff,
145 .map_io = s3c2400_map_io,
146 .init_clocks = s3c2400_init_clocks,
147 .init_uarts = s3c2400_init_uarts,
148 .init = s3c2400_init,
153 /* minimal IO mapping */
155 static struct map_desc s3c_iodesc[] __initdata = {
162 /* read cpu identificaiton code */
164 static unsigned long s3c24xx_read_idcode_v5(void)
166 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
167 return __raw_readl(S3C2412_GSTATUS1);
169 return 1UL; /* don't look like an 2400 */
173 static unsigned long s3c24xx_read_idcode_v4(void)
175 #ifndef CONFIG_CPU_S3C2400
176 return __raw_readl(S3C2410_GSTATUS1);
182 /* Hook for arm_pm_restart to ensure we execute the reset code
183 * with the caches enabled. It seems at least the S3C2440 has a problem
184 * resetting if there is bus activity interrupted by the reset.
186 static void s3c24xx_pm_restart(char mode)
191 local_irq_save(flags);
192 __cpuc_flush_kern_all();
193 __cpuc_flush_user_all();
196 local_irq_restore(flags);
199 /* fallback, or unhandled */
200 arm_machine_restart(mode);
203 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
205 unsigned long idcode = 0x0;
207 /* initialise the io descriptors we need for initialisation */
208 iotable_init(mach_desc, size);
209 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
211 if (cpu_architecture() >= CPU_ARCH_ARMv5) {
212 idcode = s3c24xx_read_idcode_v5();
214 idcode = s3c24xx_read_idcode_v4();
217 arm_pm_restart = s3c24xx_pm_restart;
219 s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));