1 /* linux/arch/arm/plat-s3c24xx/gpiolib.c
3 * Copyright (c) 2008-2010 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
7 * S3C24XX GPIOlib support
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/sysdev.h>
19 #include <linux/ioport.h>
21 #include <linux/gpio.h>
23 #include <plat/gpio-core.h>
24 #include <plat/gpio-cfg.h>
25 #include <plat/gpio-cfg-helpers.h>
26 #include <mach/hardware.h>
30 #include <mach/regs-gpio.h>
32 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
37 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
38 unsigned offset, int value)
40 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
41 void __iomem *base = ourchip->base;
46 local_irq_save(flags);
48 con = __raw_readl(base + 0x00);
49 dat = __raw_readl(base + 0x04);
51 dat &= ~(1 << offset);
55 __raw_writel(dat, base + 0x04);
57 con &= ~(1 << offset);
59 __raw_writel(con, base + 0x00);
60 __raw_writel(dat, base + 0x04);
62 local_irq_restore(flags);
66 static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset)
69 return IRQ_EINT0 + offset;
72 return IRQ_EINT4 + offset - 4;
77 static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
78 .set_config = s3c_gpio_setcfg_s3c24xx_a,
79 .get_config = s3c_gpio_getcfg_s3c24xx_a,
82 struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
83 .set_config = s3c_gpio_setcfg_s3c24xx,
84 .get_config = s3c_gpio_getcfg_s3c24xx,
87 struct s3c_gpio_chip s3c24xx_gpios[] = {
89 .base = S3C2410_GPACON,
90 .pm = __gpio_pm(&s3c_gpio_pm_1bit),
91 .config = &s3c24xx_gpiocfg_banka,
93 .base = S3C2410_GPA(0),
97 .direction_input = s3c24xx_gpiolib_banka_input,
98 .direction_output = s3c24xx_gpiolib_banka_output,
102 .base = S3C2410_GPBCON,
103 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
105 .base = S3C2410_GPB(0),
106 .owner = THIS_MODULE,
112 .base = S3C2410_GPCCON,
113 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
115 .base = S3C2410_GPC(0),
116 .owner = THIS_MODULE,
122 .base = S3C2410_GPDCON,
123 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
125 .base = S3C2410_GPD(0),
126 .owner = THIS_MODULE,
132 .base = S3C2410_GPECON,
133 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
135 .base = S3C2410_GPE(0),
137 .owner = THIS_MODULE,
142 .base = S3C2410_GPFCON,
143 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
145 .base = S3C2410_GPF(0),
146 .owner = THIS_MODULE,
149 .to_irq = s3c24xx_gpiolib_bankf_toirq,
153 .base = S3C2410_GPGCON,
154 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
155 .irq_base = IRQ_EINT8,
157 .base = S3C2410_GPG(0),
158 .owner = THIS_MODULE,
161 .to_irq = samsung_gpiolib_to_irq,
164 .base = S3C2410_GPHCON,
165 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
167 .base = S3C2410_GPH(0),
168 .owner = THIS_MODULE,
173 /* GPIOS for the S3C2443 and later devices. */
175 .base = S3C2440_GPJCON,
176 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
178 .base = S3C2410_GPJ(0),
179 .owner = THIS_MODULE,
184 .base = S3C2443_GPKCON,
185 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
187 .base = S3C2410_GPK(0),
188 .owner = THIS_MODULE,
193 .base = S3C2443_GPLCON,
194 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
196 .base = S3C2410_GPL(0),
197 .owner = THIS_MODULE,
202 .base = S3C2443_GPMCON,
203 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
205 .base = S3C2410_GPM(0),
206 .owner = THIS_MODULE,
214 static __init int s3c24xx_gpiolib_init(void)
216 struct s3c_gpio_chip *chip = s3c24xx_gpios;
219 for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) {
221 chip->config = &s3c24xx_gpiocfg_default;
223 s3c_gpiolib_add(chip);
229 core_initcall(s3c24xx_gpiolib_init);