1 /* linux/arch/arm/plat-s3c24xx/gpiolib.c
3 * Copyright (c) 2008-2010 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
7 * S3C24XX GPIOlib support
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/sysdev.h>
19 #include <linux/ioport.h>
21 #include <linux/gpio.h>
23 #include <plat/gpio-core.h>
24 #include <plat/gpio-cfg.h>
25 #include <plat/gpio-cfg-helpers.h>
26 #include <mach/hardware.h>
30 #include <mach/regs-gpio.h>
32 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
37 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
38 unsigned offset, int value)
40 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
41 void __iomem *base = ourchip->base;
46 local_irq_save(flags);
48 con = __raw_readl(base + 0x00);
49 dat = __raw_readl(base + 0x04);
51 dat &= ~(1 << offset);
55 __raw_writel(dat, base + 0x04);
57 con &= ~(1 << offset);
59 __raw_writel(con, base + 0x00);
60 __raw_writel(dat, base + 0x04);
62 local_irq_restore(flags);
66 static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset)
69 return IRQ_EINT0 + offset;
72 return IRQ_EINT4 + offset - 4;
77 static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
79 return IRQ_EINT8 + offset;
82 static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
83 .set_config = s3c_gpio_setcfg_s3c24xx_a,
84 .get_config = s3c_gpio_getcfg_s3c24xx_a,
87 struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
88 .set_config = s3c_gpio_setcfg_s3c24xx,
89 .get_config = s3c_gpio_getcfg_s3c24xx,
90 .set_pull = s3c_gpio_setpull_1up,
91 .get_pull = s3c_gpio_getpull_1up,
94 struct s3c_gpio_chip s3c24xx_gpios[] = {
96 .base = S3C2410_GPACON,
97 .pm = __gpio_pm(&s3c_gpio_pm_1bit),
98 .config = &s3c24xx_gpiocfg_banka,
100 .base = S3C2410_GPA(0),
101 .owner = THIS_MODULE,
104 .direction_input = s3c24xx_gpiolib_banka_input,
105 .direction_output = s3c24xx_gpiolib_banka_output,
109 .base = S3C2410_GPBCON,
110 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
112 .base = S3C2410_GPB(0),
113 .owner = THIS_MODULE,
119 .base = S3C2410_GPCCON,
120 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
122 .base = S3C2410_GPC(0),
123 .owner = THIS_MODULE,
129 .base = S3C2410_GPDCON,
130 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
132 .base = S3C2410_GPD(0),
133 .owner = THIS_MODULE,
139 .base = S3C2410_GPECON,
140 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
142 .base = S3C2410_GPE(0),
144 .owner = THIS_MODULE,
149 .base = S3C2410_GPFCON,
150 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
152 .base = S3C2410_GPF(0),
153 .owner = THIS_MODULE,
156 .to_irq = s3c24xx_gpiolib_bankf_toirq,
160 .base = S3C2410_GPGCON,
161 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
163 .base = S3C2410_GPG(0),
164 .owner = THIS_MODULE,
167 .to_irq = s3c24xx_gpiolib_bankg_toirq,
170 .base = S3C2410_GPHCON,
171 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
173 .base = S3C2410_GPH(0),
174 .owner = THIS_MODULE,
179 /* GPIOS for the S3C2443 and later devices. */
181 .base = S3C2440_GPJCON,
182 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
184 .base = S3C2410_GPJ(0),
185 .owner = THIS_MODULE,
190 .base = S3C2443_GPKCON,
191 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
193 .base = S3C2410_GPK(0),
194 .owner = THIS_MODULE,
199 .base = S3C2443_GPLCON,
200 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
202 .base = S3C2410_GPL(0),
203 .owner = THIS_MODULE,
208 .base = S3C2443_GPMCON,
209 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
211 .base = S3C2410_GPM(0),
212 .owner = THIS_MODULE,
220 static __init int s3c24xx_gpiolib_init(void)
222 struct s3c_gpio_chip *chip = s3c24xx_gpios;
225 for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) {
227 chip->config = &s3c24xx_gpiocfg_default;
229 s3c_gpiolib_add(chip);
235 core_initcall(s3c24xx_gpiolib_init);