1 /* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C6400 based common clock support
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/errno.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/sysdev.h>
25 #include <mach/hardware.h>
28 #include <plat/cpu-freq.h>
30 #include <plat/regs-clock.h>
31 #include <plat/clock.h>
35 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
36 * ext_xtal_mux for want of an actual name from the manual.
39 static struct clk clk_ext_xtal_mux = {
44 #define clk_fin_apll clk_ext_xtal_mux
45 #define clk_fin_mpll clk_ext_xtal_mux
46 #define clk_fin_epll clk_ext_xtal_mux
48 #define clk_fout_mpll clk_mpll
51 unsigned int nr_sources;
60 struct clk_sources *sources;
62 unsigned int divider_shift;
63 void __iomem *reg_divider;
66 static struct clk clk_fout_apll = {
71 static struct clk *clk_src_apll_list[] = {
76 static struct clk_sources clk_src_apll = {
77 .sources = clk_src_apll_list,
78 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
81 static struct clksrc_clk clk_mout_apll = {
86 .shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT,
87 .mask = S3C6400_CLKSRC_APLL_MOUT,
88 .sources = &clk_src_apll,
91 static struct clk clk_fout_epll = {
96 static struct clk *clk_src_epll_list[] = {
101 static struct clk_sources clk_src_epll = {
102 .sources = clk_src_epll_list,
103 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
106 static struct clksrc_clk clk_mout_epll = {
111 .shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT,
112 .mask = S3C6400_CLKSRC_EPLL_MOUT,
113 .sources = &clk_src_epll,
116 static struct clk *clk_src_mpll_list[] = {
118 [1] = &clk_fout_mpll,
121 static struct clk_sources clk_src_mpll = {
122 .sources = clk_src_mpll_list,
123 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
126 static struct clksrc_clk clk_mout_mpll = {
131 .shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT,
132 .mask = S3C6400_CLKSRC_MPLL_MOUT,
133 .sources = &clk_src_mpll,
136 static unsigned int armclk_mask;
138 static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
140 unsigned long rate = clk_get_rate(clk->parent);
143 /* divisor mask starts at bit0, so no need to shift */
144 clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
146 return rate / (clkdiv + 1);
149 static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
152 unsigned long parent = clk_get_rate(clk->parent);
158 div = (parent / rate) - 1;
159 if (div > armclk_mask)
162 return parent / (div + 1);
165 static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
167 unsigned long parent = clk_get_rate(clk->parent);
171 if (rate < parent / (armclk_mask + 1))
174 rate = clk_round_rate(clk, rate);
175 div = clk_get_rate(clk->parent) / rate;
177 val = __raw_readl(S3C_CLK_DIV0);
180 __raw_writel(val, S3C_CLK_DIV0);
186 static struct clk clk_arm = {
189 .parent = &clk_mout_apll.clk,
190 .get_rate = s3c64xx_clk_arm_get_rate,
191 .set_rate = s3c64xx_clk_arm_set_rate,
192 .round_rate = s3c64xx_clk_arm_round_rate,
195 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
197 unsigned long rate = clk_get_rate(clk->parent);
199 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
201 if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
207 static struct clk clk_dout_mpll = {
210 .parent = &clk_mout_mpll.clk,
211 .get_rate = s3c64xx_clk_doutmpll_get_rate,
214 static struct clk *clkset_spi_mmc_list[] = {
221 static struct clk_sources clkset_spi_mmc = {
222 .sources = clkset_spi_mmc_list,
223 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
226 static struct clk *clkset_irda_list[] = {
233 static struct clk_sources clkset_irda = {
234 .sources = clkset_irda_list,
235 .nr_sources = ARRAY_SIZE(clkset_irda_list),
238 static struct clk *clkset_uart_list[] = {
245 static struct clk_sources clkset_uart = {
246 .sources = clkset_uart_list,
247 .nr_sources = ARRAY_SIZE(clkset_uart_list),
250 static struct clk *clkset_uhost_list[] = {
257 static struct clk_sources clkset_uhost = {
258 .sources = clkset_uhost_list,
259 .nr_sources = ARRAY_SIZE(clkset_uhost_list),
263 /* The peripheral clocks are all controlled via clocksource followed
264 * by an optional divider and gate stage. We currently roll this into
265 * one clock which hides the intermediate clock from the mux.
267 * Note, the JPEG clock can only be an even divider...
269 * The scaler and LCD clocks depend on the S3C64XX version, and also
270 * have a common parent divisor so are not included here.
273 static inline struct clksrc_clk *to_clksrc(struct clk *clk)
275 return container_of(clk, struct clksrc_clk, clk);
278 static unsigned long s3c64xx_getrate_clksrc(struct clk *clk)
280 struct clksrc_clk *sclk = to_clksrc(clk);
281 unsigned long rate = clk_get_rate(clk->parent);
282 u32 clkdiv = __raw_readl(sclk->reg_divider);
284 clkdiv >>= sclk->divider_shift;
292 static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
294 struct clksrc_clk *sclk = to_clksrc(clk);
295 void __iomem *reg = sclk->reg_divider;
299 rate = clk_round_rate(clk, rate);
300 div = clk_get_rate(clk->parent) / rate;
304 val = __raw_readl(reg);
305 val &= ~(0xf << sclk->divider_shift);
306 val |= (div - 1) << sclk->divider_shift;
307 __raw_writel(val, reg);
312 static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent)
314 struct clksrc_clk *sclk = to_clksrc(clk);
315 struct clk_sources *srcs = sclk->sources;
316 u32 clksrc = __raw_readl(S3C_CLK_SRC);
320 for (ptr = 0; ptr < srcs->nr_sources; ptr++)
321 if (srcs->sources[ptr] == parent) {
327 clksrc &= ~sclk->mask;
328 clksrc |= src_nr << sclk->shift;
330 __raw_writel(clksrc, S3C_CLK_SRC);
332 clk->parent = parent;
339 static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
342 unsigned long parent_rate = clk_get_rate(clk->parent);
345 if (rate > parent_rate)
348 div = parent_rate / rate;
355 rate = parent_rate / div;
361 static struct clksrc_clk clk_mmc0 = {
365 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
366 .enable = s3c64xx_sclk_ctrl,
367 .set_parent = s3c64xx_setparent_clksrc,
368 .get_rate = s3c64xx_getrate_clksrc,
369 .set_rate = s3c64xx_setrate_clksrc,
370 .round_rate = s3c64xx_roundrate_clksrc,
372 .shift = S3C6400_CLKSRC_MMC0_SHIFT,
373 .mask = S3C6400_CLKSRC_MMC0_MASK,
374 .sources = &clkset_spi_mmc,
375 .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT,
376 .reg_divider = S3C_CLK_DIV1,
379 static struct clksrc_clk clk_mmc1 = {
383 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
384 .enable = s3c64xx_sclk_ctrl,
385 .get_rate = s3c64xx_getrate_clksrc,
386 .set_rate = s3c64xx_setrate_clksrc,
387 .set_parent = s3c64xx_setparent_clksrc,
388 .round_rate = s3c64xx_roundrate_clksrc,
390 .shift = S3C6400_CLKSRC_MMC1_SHIFT,
391 .mask = S3C6400_CLKSRC_MMC1_MASK,
392 .sources = &clkset_spi_mmc,
393 .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT,
394 .reg_divider = S3C_CLK_DIV1,
397 static struct clksrc_clk clk_mmc2 = {
401 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
402 .enable = s3c64xx_sclk_ctrl,
403 .get_rate = s3c64xx_getrate_clksrc,
404 .set_rate = s3c64xx_setrate_clksrc,
405 .set_parent = s3c64xx_setparent_clksrc,
406 .round_rate = s3c64xx_roundrate_clksrc,
408 .shift = S3C6400_CLKSRC_MMC2_SHIFT,
409 .mask = S3C6400_CLKSRC_MMC2_MASK,
410 .sources = &clkset_spi_mmc,
411 .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT,
412 .reg_divider = S3C_CLK_DIV1,
415 static struct clksrc_clk clk_usbhost = {
417 .name = "usb-bus-host",
419 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
420 .enable = s3c64xx_sclk_ctrl,
421 .set_parent = s3c64xx_setparent_clksrc,
422 .get_rate = s3c64xx_getrate_clksrc,
423 .set_rate = s3c64xx_setrate_clksrc,
424 .round_rate = s3c64xx_roundrate_clksrc,
426 .shift = S3C6400_CLKSRC_UHOST_SHIFT,
427 .mask = S3C6400_CLKSRC_UHOST_MASK,
428 .sources = &clkset_uhost,
429 .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT,
430 .reg_divider = S3C_CLK_DIV1,
433 static struct clksrc_clk clk_uart_uclk1 = {
437 .ctrlbit = S3C_CLKCON_SCLK_UART,
438 .enable = s3c64xx_sclk_ctrl,
439 .set_parent = s3c64xx_setparent_clksrc,
440 .get_rate = s3c64xx_getrate_clksrc,
441 .set_rate = s3c64xx_setrate_clksrc,
442 .round_rate = s3c64xx_roundrate_clksrc,
444 .shift = S3C6400_CLKSRC_UART_SHIFT,
445 .mask = S3C6400_CLKSRC_UART_MASK,
446 .sources = &clkset_uart,
447 .divider_shift = S3C6400_CLKDIV2_UART_SHIFT,
448 .reg_divider = S3C_CLK_DIV2,
451 /* Where does UCLK0 come from? */
453 static struct clksrc_clk clk_spi0 = {
457 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
458 .enable = s3c64xx_sclk_ctrl,
459 .set_parent = s3c64xx_setparent_clksrc,
460 .get_rate = s3c64xx_getrate_clksrc,
461 .set_rate = s3c64xx_setrate_clksrc,
462 .round_rate = s3c64xx_roundrate_clksrc,
464 .shift = S3C6400_CLKSRC_SPI0_SHIFT,
465 .mask = S3C6400_CLKSRC_SPI0_MASK,
466 .sources = &clkset_spi_mmc,
467 .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT,
468 .reg_divider = S3C_CLK_DIV2,
471 static struct clksrc_clk clk_spi1 = {
475 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
476 .enable = s3c64xx_sclk_ctrl,
477 .set_parent = s3c64xx_setparent_clksrc,
478 .get_rate = s3c64xx_getrate_clksrc,
479 .set_rate = s3c64xx_setrate_clksrc,
480 .round_rate = s3c64xx_roundrate_clksrc,
482 .shift = S3C6400_CLKSRC_SPI1_SHIFT,
483 .mask = S3C6400_CLKSRC_SPI1_MASK,
484 .sources = &clkset_spi_mmc,
485 .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT,
486 .reg_divider = S3C_CLK_DIV2,
489 static struct clk clk_iis_cd0 = {
490 .name = "iis_cdclk0",
494 static struct clk clk_iis_cd1 = {
495 .name = "iis_cdclk1",
499 static struct clk clk_pcm_cd = {
504 static struct clk *clkset_audio0_list[] = {
505 [0] = &clk_mout_epll.clk,
506 [1] = &clk_dout_mpll,
512 static struct clk_sources clkset_audio0 = {
513 .sources = clkset_audio0_list,
514 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
517 static struct clksrc_clk clk_audio0 = {
521 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
522 .enable = s3c64xx_sclk_ctrl,
523 .set_parent = s3c64xx_setparent_clksrc,
524 .get_rate = s3c64xx_getrate_clksrc,
525 .set_rate = s3c64xx_setrate_clksrc,
526 .round_rate = s3c64xx_roundrate_clksrc,
528 .shift = S3C6400_CLKSRC_AUDIO0_SHIFT,
529 .mask = S3C6400_CLKSRC_AUDIO0_MASK,
530 .sources = &clkset_audio0,
531 .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT,
532 .reg_divider = S3C_CLK_DIV2,
535 static struct clk *clkset_audio1_list[] = {
536 [0] = &clk_mout_epll.clk,
537 [1] = &clk_dout_mpll,
543 static struct clk_sources clkset_audio1 = {
544 .sources = clkset_audio1_list,
545 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
548 static struct clksrc_clk clk_audio1 = {
552 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
553 .enable = s3c64xx_sclk_ctrl,
554 .set_parent = s3c64xx_setparent_clksrc,
555 .get_rate = s3c64xx_getrate_clksrc,
556 .set_rate = s3c64xx_setrate_clksrc,
557 .round_rate = s3c64xx_roundrate_clksrc,
559 .shift = S3C6400_CLKSRC_AUDIO1_SHIFT,
560 .mask = S3C6400_CLKSRC_AUDIO1_MASK,
561 .sources = &clkset_audio1,
562 .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT,
563 .reg_divider = S3C_CLK_DIV2,
566 static struct clksrc_clk clk_irda = {
570 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
571 .enable = s3c64xx_sclk_ctrl,
572 .set_parent = s3c64xx_setparent_clksrc,
573 .get_rate = s3c64xx_getrate_clksrc,
574 .set_rate = s3c64xx_setrate_clksrc,
575 .round_rate = s3c64xx_roundrate_clksrc,
577 .shift = S3C6400_CLKSRC_IRDA_SHIFT,
578 .mask = S3C6400_CLKSRC_IRDA_MASK,
579 .sources = &clkset_irda,
580 .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT,
581 .reg_divider = S3C_CLK_DIV2,
584 static struct clk *clkset_camif_list[] = {
588 static struct clk_sources clkset_camif = {
589 .sources = clkset_camif_list,
590 .nr_sources = ARRAY_SIZE(clkset_camif_list),
593 static struct clksrc_clk clk_camif = {
597 .ctrlbit = S3C_CLKCON_SCLK_CAM,
598 .enable = s3c64xx_sclk_ctrl,
599 .set_parent = s3c64xx_setparent_clksrc,
600 .get_rate = s3c64xx_getrate_clksrc,
601 .set_rate = s3c64xx_setrate_clksrc,
602 .round_rate = s3c64xx_roundrate_clksrc,
606 .sources = &clkset_camif,
607 .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT,
608 .reg_divider = S3C_CLK_DIV0,
611 /* Clock initialisation code */
613 static struct clksrc_clk *init_parents[] = {
630 static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
632 struct clk_sources *srcs = clk->sources;
633 u32 clksrc = __raw_readl(S3C_CLK_SRC);
636 clksrc >>= clk->shift;
638 if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
639 printk(KERN_ERR "%s: bad source %d\n",
640 clk->clk.name, clksrc);
644 clk->clk.parent = srcs->sources[clksrc];
646 printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
647 clk->clk.name, clk->clk.parent->name, clksrc,
648 clk_get_rate(&clk->clk));
651 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
653 void __init_or_cpufreq s3c6400_setup_clocks(void)
655 struct clk *xtal_clk;
667 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
669 clkdiv0 = __raw_readl(S3C_CLK_DIV0);
670 printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
672 xtal_clk = clk_get(NULL, "xtal");
673 BUG_ON(IS_ERR(xtal_clk));
675 xtal = clk_get_rate(xtal_clk);
678 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
680 /* For now assume the mux always selects the crystal */
681 clk_ext_xtal_mux.parent = xtal_clk;
683 epll = s3c6400_get_epll(xtal);
684 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
685 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
689 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
692 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
693 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
694 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
696 printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
699 clk_fout_mpll.rate = mpll;
700 clk_fout_epll.rate = epll;
701 clk_fout_apll.rate = apll;
708 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
709 s3c6400_set_clksrc(init_parents[ptr]);
712 static struct clk *clks[] __initdata = {
736 * s3c6400_register_clocks - register clocks for s3c6400 and above
737 * @armclk_divlimit: Divisor mask for ARMCLK
739 * Register the clocks for the S3C6400 and above SoC range, such
740 * as ARMCLK and the clocks which have divider chains attached.
742 * This call does not setup the clocks, which is left to the
743 * s3c6400_setup_clocks() call which may be needed by the cpufreq
744 * or resume code to re-set the clocks if the bootloader has changed
747 void __init s3c6400_register_clocks(unsigned armclk_divlimit)
753 armclk_mask = armclk_divlimit;
755 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
757 ret = s3c24xx_register_clock(clkp);
759 printk(KERN_ERR "Failed to register clock %s (%d)\n",
764 clk_mpll.parent = &clk_mout_mpll.clk;
765 clk_epll.parent = &clk_mout_epll.clk;