1 /* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C6400 based common clock support
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/errno.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/sysdev.h>
25 #include <mach/hardware.h>
28 #include <plat/cpu-freq.h>
30 #include <plat/regs-clock.h>
31 #include <plat/clock.h>
35 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
36 * ext_xtal_mux for want of an actual name from the manual.
39 static struct clk clk_ext_xtal_mux = {
44 #define clk_fin_apll clk_ext_xtal_mux
45 #define clk_fin_mpll clk_ext_xtal_mux
46 #define clk_fin_epll clk_ext_xtal_mux
48 #define clk_fout_mpll clk_mpll
49 #define clk_fout_epll clk_epll
52 unsigned int nr_sources;
61 struct clk_sources *sources;
63 unsigned int divider_shift;
64 void __iomem *reg_divider;
67 static struct clk clk_fout_apll = {
72 static struct clk *clk_src_apll_list[] = {
77 static struct clk_sources clk_src_apll = {
78 .sources = clk_src_apll_list,
79 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
82 static struct clksrc_clk clk_mout_apll = {
87 .shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT,
88 .mask = S3C6400_CLKSRC_APLL_MOUT,
89 .sources = &clk_src_apll,
92 static struct clk *clk_src_epll_list[] = {
97 static struct clk_sources clk_src_epll = {
98 .sources = clk_src_epll_list,
99 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
102 static struct clksrc_clk clk_mout_epll = {
107 .shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT,
108 .mask = S3C6400_CLKSRC_EPLL_MOUT,
109 .sources = &clk_src_epll,
112 static struct clk *clk_src_mpll_list[] = {
114 [1] = &clk_fout_mpll,
117 static struct clk_sources clk_src_mpll = {
118 .sources = clk_src_mpll_list,
119 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
122 static struct clksrc_clk clk_mout_mpll = {
127 .shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT,
128 .mask = S3C6400_CLKSRC_MPLL_MOUT,
129 .sources = &clk_src_mpll,
132 static unsigned int armclk_mask;
134 static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
136 unsigned long rate = clk_get_rate(clk->parent);
139 /* divisor mask starts at bit0, so no need to shift */
140 clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
142 return rate / (clkdiv + 1);
145 static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
148 unsigned long parent = clk_get_rate(clk->parent);
154 div = (parent / rate) - 1;
155 if (div > armclk_mask)
158 return parent / (div + 1);
161 static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
163 unsigned long parent = clk_get_rate(clk->parent);
167 if (rate < parent / (armclk_mask + 1))
170 rate = clk_round_rate(clk, rate);
171 div = clk_get_rate(clk->parent) / rate;
173 val = __raw_readl(S3C_CLK_DIV0);
176 __raw_writel(val, S3C_CLK_DIV0);
182 static struct clk clk_arm = {
185 .parent = &clk_mout_apll.clk,
186 .get_rate = s3c64xx_clk_arm_get_rate,
187 .set_rate = s3c64xx_clk_arm_set_rate,
188 .round_rate = s3c64xx_clk_arm_round_rate,
191 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
193 unsigned long rate = clk_get_rate(clk->parent);
195 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
197 if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
203 static struct clk clk_dout_mpll = {
206 .parent = &clk_mout_mpll.clk,
207 .get_rate = s3c64xx_clk_doutmpll_get_rate,
210 static struct clk *clkset_spi_mmc_list[] = {
217 static struct clk_sources clkset_spi_mmc = {
218 .sources = clkset_spi_mmc_list,
219 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
222 static struct clk *clkset_irda_list[] = {
229 static struct clk_sources clkset_irda = {
230 .sources = clkset_irda_list,
231 .nr_sources = ARRAY_SIZE(clkset_irda_list),
234 static struct clk *clkset_uart_list[] = {
241 static struct clk_sources clkset_uart = {
242 .sources = clkset_uart_list,
243 .nr_sources = ARRAY_SIZE(clkset_uart_list),
246 static struct clk *clkset_uhost_list[] = {
253 static struct clk_sources clkset_uhost = {
254 .sources = clkset_uhost_list,
255 .nr_sources = ARRAY_SIZE(clkset_uhost_list),
259 /* The peripheral clocks are all controlled via clocksource followed
260 * by an optional divider and gate stage. We currently roll this into
261 * one clock which hides the intermediate clock from the mux.
263 * Note, the JPEG clock can only be an even divider...
265 * The scaler and LCD clocks depend on the S3C64XX version, and also
266 * have a common parent divisor so are not included here.
269 static inline struct clksrc_clk *to_clksrc(struct clk *clk)
271 return container_of(clk, struct clksrc_clk, clk);
274 static unsigned long s3c64xx_getrate_clksrc(struct clk *clk)
276 struct clksrc_clk *sclk = to_clksrc(clk);
277 unsigned long rate = clk_get_rate(clk->parent);
278 u32 clkdiv = __raw_readl(sclk->reg_divider);
280 clkdiv >>= sclk->divider_shift;
288 static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
290 struct clksrc_clk *sclk = to_clksrc(clk);
291 void __iomem *reg = sclk->reg_divider;
295 rate = clk_round_rate(clk, rate);
296 div = clk_get_rate(clk->parent) / rate;
300 val = __raw_readl(reg);
301 val &= ~(0xf << sclk->divider_shift);
302 val |= (div - 1) << sclk->divider_shift;
303 __raw_writel(val, reg);
308 static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent)
310 struct clksrc_clk *sclk = to_clksrc(clk);
311 struct clk_sources *srcs = sclk->sources;
312 u32 clksrc = __raw_readl(S3C_CLK_SRC);
316 for (ptr = 0; ptr < srcs->nr_sources; ptr++)
317 if (srcs->sources[ptr] == parent) {
323 clksrc &= ~sclk->mask;
324 clksrc |= src_nr << sclk->shift;
326 __raw_writel(clksrc, S3C_CLK_SRC);
328 clk->parent = parent;
335 static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
338 unsigned long parent_rate = clk_get_rate(clk->parent);
341 if (rate > parent_rate)
344 div = parent_rate / rate;
351 rate = parent_rate / div;
357 static struct clksrc_clk clk_mmc0 = {
361 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
362 .enable = s3c64xx_sclk_ctrl,
363 .set_parent = s3c64xx_setparent_clksrc,
364 .get_rate = s3c64xx_getrate_clksrc,
365 .set_rate = s3c64xx_setrate_clksrc,
366 .round_rate = s3c64xx_roundrate_clksrc,
368 .shift = S3C6400_CLKSRC_MMC0_SHIFT,
369 .mask = S3C6400_CLKSRC_MMC0_MASK,
370 .sources = &clkset_spi_mmc,
371 .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT,
372 .reg_divider = S3C_CLK_DIV1,
375 static struct clksrc_clk clk_mmc1 = {
379 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
380 .enable = s3c64xx_sclk_ctrl,
381 .get_rate = s3c64xx_getrate_clksrc,
382 .set_rate = s3c64xx_setrate_clksrc,
383 .set_parent = s3c64xx_setparent_clksrc,
384 .round_rate = s3c64xx_roundrate_clksrc,
386 .shift = S3C6400_CLKSRC_MMC1_SHIFT,
387 .mask = S3C6400_CLKSRC_MMC1_MASK,
388 .sources = &clkset_spi_mmc,
389 .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT,
390 .reg_divider = S3C_CLK_DIV1,
393 static struct clksrc_clk clk_mmc2 = {
397 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
398 .enable = s3c64xx_sclk_ctrl,
399 .get_rate = s3c64xx_getrate_clksrc,
400 .set_rate = s3c64xx_setrate_clksrc,
401 .set_parent = s3c64xx_setparent_clksrc,
402 .round_rate = s3c64xx_roundrate_clksrc,
404 .shift = S3C6400_CLKSRC_MMC2_SHIFT,
405 .mask = S3C6400_CLKSRC_MMC2_MASK,
406 .sources = &clkset_spi_mmc,
407 .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT,
408 .reg_divider = S3C_CLK_DIV1,
411 static struct clksrc_clk clk_usbhost = {
413 .name = "usb-bus-host",
415 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
416 .enable = s3c64xx_sclk_ctrl,
417 .set_parent = s3c64xx_setparent_clksrc,
418 .get_rate = s3c64xx_getrate_clksrc,
419 .set_rate = s3c64xx_setrate_clksrc,
420 .round_rate = s3c64xx_roundrate_clksrc,
422 .shift = S3C6400_CLKSRC_UHOST_SHIFT,
423 .mask = S3C6400_CLKSRC_UHOST_MASK,
424 .sources = &clkset_uhost,
425 .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT,
426 .reg_divider = S3C_CLK_DIV1,
429 static struct clksrc_clk clk_uart_uclk1 = {
433 .ctrlbit = S3C_CLKCON_SCLK_UART,
434 .enable = s3c64xx_sclk_ctrl,
435 .set_parent = s3c64xx_setparent_clksrc,
436 .get_rate = s3c64xx_getrate_clksrc,
437 .set_rate = s3c64xx_setrate_clksrc,
438 .round_rate = s3c64xx_roundrate_clksrc,
440 .shift = S3C6400_CLKSRC_UART_SHIFT,
441 .mask = S3C6400_CLKSRC_UART_MASK,
442 .sources = &clkset_uart,
443 .divider_shift = S3C6400_CLKDIV2_UART_SHIFT,
444 .reg_divider = S3C_CLK_DIV2,
447 /* Where does UCLK0 come from? */
449 static struct clksrc_clk clk_spi0 = {
453 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
454 .enable = s3c64xx_sclk_ctrl,
455 .set_parent = s3c64xx_setparent_clksrc,
456 .get_rate = s3c64xx_getrate_clksrc,
457 .set_rate = s3c64xx_setrate_clksrc,
458 .round_rate = s3c64xx_roundrate_clksrc,
460 .shift = S3C6400_CLKSRC_SPI0_SHIFT,
461 .mask = S3C6400_CLKSRC_SPI0_MASK,
462 .sources = &clkset_spi_mmc,
463 .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT,
464 .reg_divider = S3C_CLK_DIV2,
467 static struct clksrc_clk clk_spi1 = {
471 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
472 .enable = s3c64xx_sclk_ctrl,
473 .set_parent = s3c64xx_setparent_clksrc,
474 .get_rate = s3c64xx_getrate_clksrc,
475 .set_rate = s3c64xx_setrate_clksrc,
476 .round_rate = s3c64xx_roundrate_clksrc,
478 .shift = S3C6400_CLKSRC_SPI1_SHIFT,
479 .mask = S3C6400_CLKSRC_SPI1_MASK,
480 .sources = &clkset_spi_mmc,
481 .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT,
482 .reg_divider = S3C_CLK_DIV2,
485 static struct clk clk_iis_cd0 = {
486 .name = "iis_cdclk0",
490 static struct clk clk_iis_cd1 = {
491 .name = "iis_cdclk1",
495 static struct clk clk_pcm_cd = {
500 static struct clk *clkset_audio0_list[] = {
501 [0] = &clk_mout_epll.clk,
502 [1] = &clk_dout_mpll,
508 static struct clk_sources clkset_audio0 = {
509 .sources = clkset_audio0_list,
510 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
513 static struct clksrc_clk clk_audio0 = {
517 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
518 .enable = s3c64xx_sclk_ctrl,
519 .set_parent = s3c64xx_setparent_clksrc,
520 .get_rate = s3c64xx_getrate_clksrc,
521 .set_rate = s3c64xx_setrate_clksrc,
522 .round_rate = s3c64xx_roundrate_clksrc,
524 .shift = S3C6400_CLKSRC_AUDIO0_SHIFT,
525 .mask = S3C6400_CLKSRC_AUDIO0_MASK,
526 .sources = &clkset_audio0,
527 .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT,
528 .reg_divider = S3C_CLK_DIV2,
531 static struct clk *clkset_audio1_list[] = {
532 [0] = &clk_mout_epll.clk,
533 [1] = &clk_dout_mpll,
539 static struct clk_sources clkset_audio1 = {
540 .sources = clkset_audio1_list,
541 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
544 static struct clksrc_clk clk_audio1 = {
548 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
549 .enable = s3c64xx_sclk_ctrl,
550 .set_parent = s3c64xx_setparent_clksrc,
551 .get_rate = s3c64xx_getrate_clksrc,
552 .set_rate = s3c64xx_setrate_clksrc,
553 .round_rate = s3c64xx_roundrate_clksrc,
555 .shift = S3C6400_CLKSRC_AUDIO1_SHIFT,
556 .mask = S3C6400_CLKSRC_AUDIO1_MASK,
557 .sources = &clkset_audio1,
558 .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT,
559 .reg_divider = S3C_CLK_DIV2,
562 static struct clksrc_clk clk_irda = {
566 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
567 .enable = s3c64xx_sclk_ctrl,
568 .set_parent = s3c64xx_setparent_clksrc,
569 .get_rate = s3c64xx_getrate_clksrc,
570 .set_rate = s3c64xx_setrate_clksrc,
571 .round_rate = s3c64xx_roundrate_clksrc,
573 .shift = S3C6400_CLKSRC_IRDA_SHIFT,
574 .mask = S3C6400_CLKSRC_IRDA_MASK,
575 .sources = &clkset_irda,
576 .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT,
577 .reg_divider = S3C_CLK_DIV2,
580 static struct clk *clkset_camif_list[] = {
584 static struct clk_sources clkset_camif = {
585 .sources = clkset_camif_list,
586 .nr_sources = ARRAY_SIZE(clkset_camif_list),
589 static struct clksrc_clk clk_camif = {
593 .ctrlbit = S3C_CLKCON_SCLK_CAM,
594 .enable = s3c64xx_sclk_ctrl,
595 .set_parent = s3c64xx_setparent_clksrc,
596 .get_rate = s3c64xx_getrate_clksrc,
597 .set_rate = s3c64xx_setrate_clksrc,
598 .round_rate = s3c64xx_roundrate_clksrc,
602 .sources = &clkset_camif,
603 .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT,
604 .reg_divider = S3C_CLK_DIV0,
607 /* Clock initialisation code */
609 static struct clksrc_clk *init_parents[] = {
626 static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
628 struct clk_sources *srcs = clk->sources;
629 u32 clksrc = __raw_readl(S3C_CLK_SRC);
632 clksrc >>= clk->shift;
634 if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
635 printk(KERN_ERR "%s: bad source %d\n",
636 clk->clk.name, clksrc);
640 clk->clk.parent = srcs->sources[clksrc];
642 printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
643 clk->clk.name, clk->clk.parent->name, clksrc,
644 clk_get_rate(&clk->clk));
647 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
649 void __init_or_cpufreq s3c6400_setup_clocks(void)
651 struct clk *xtal_clk;
663 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
665 clkdiv0 = __raw_readl(S3C_CLK_DIV0);
666 printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
668 xtal_clk = clk_get(NULL, "xtal");
669 BUG_ON(IS_ERR(xtal_clk));
671 xtal = clk_get_rate(xtal_clk);
674 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
676 /* For now assume the mux always selects the crystal */
677 clk_ext_xtal_mux.parent = xtal_clk;
679 epll = s3c6400_get_epll(xtal);
680 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
681 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
685 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
688 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
689 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
690 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
692 printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
695 clk_fout_mpll.rate = mpll;
696 clk_fout_epll.rate = epll;
697 clk_fout_apll.rate = apll;
704 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
705 s3c6400_set_clksrc(init_parents[ptr]);
708 static struct clk *clks[] __initdata = {
731 * s3c6400_register_clocks - register clocks for s3c6400 and above
732 * @armclk_divlimit: Divisor mask for ARMCLK
734 * Register the clocks for the S3C6400 and above SoC range, such
735 * as ARMCLK and the clocks which have divider chains attached.
737 * This call does not setup the clocks, which is left to the
738 * s3c6400_setup_clocks() call which may be needed by the cpufreq
739 * or resume code to re-set the clocks if the bootloader has changed
742 void __init s3c6400_register_clocks(unsigned armclk_divlimit)
748 armclk_mask = armclk_divlimit;
750 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
752 ret = s3c24xx_register_clock(clkp);
754 printk(KERN_ERR "Failed to register clock %s (%d)\n",