1 /* linux/arch/arm/plat-s5p/clock.c
3 * Copyright 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5P - Common clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
22 #include <asm/div64.h>
24 #include <mach/regs-clock.h>
26 #include <plat/clock.h>
27 #include <plat/clock-clksrc.h>
28 #include <plat/s5p-clock.h>
30 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
33 struct clk clk_ext_xtal_mux = {
38 struct clk clk_xusbxti = {
43 struct clk s5p_clk_27m = {
49 /* 48MHz USB Phy clock output */
50 struct clk clk_48m = {
57 * No need .ctrlbit, this is always on
59 struct clk clk_fout_apll = {
65 * No need .ctrlbit, this is always on
67 struct clk clk_fout_mpll = {
72 /* EPLL clock output */
73 struct clk clk_fout_epll = {
79 /* DPLL clock output */
80 struct clk clk_fout_dpll = {
86 /* VPLL clock output */
87 struct clk clk_fout_vpll = {
93 /* Possible clock sources for APLL Mux */
94 static struct clk *clk_src_apll_list[] = {
99 struct clksrc_sources clk_src_apll = {
100 .sources = clk_src_apll_list,
101 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
104 /* Possible clock sources for MPLL Mux */
105 static struct clk *clk_src_mpll_list[] = {
107 [1] = &clk_fout_mpll,
110 struct clksrc_sources clk_src_mpll = {
111 .sources = clk_src_mpll_list,
112 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
115 /* Possible clock sources for EPLL Mux */
116 static struct clk *clk_src_epll_list[] = {
118 [1] = &clk_fout_epll,
121 struct clksrc_sources clk_src_epll = {
122 .sources = clk_src_epll_list,
123 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
126 /* Possible clock sources for DPLL Mux */
127 static struct clk *clk_src_dpll_list[] = {
129 [1] = &clk_fout_dpll,
132 struct clksrc_sources clk_src_dpll = {
133 .sources = clk_src_dpll_list,
134 .nr_sources = ARRAY_SIZE(clk_src_dpll_list),
137 struct clk clk_vpll = {
142 int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
144 unsigned int ctrlbit = clk->ctrlbit;
147 con = __raw_readl(reg);
148 con = enable ? (con | ctrlbit) : (con & ~ctrlbit);
149 __raw_writel(con, reg);
153 int s5p_epll_enable(struct clk *clk, int enable)
155 unsigned int ctrlbit = clk->ctrlbit;
156 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
159 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
161 __raw_writel(epll_con, S5P_EPLL_CON);
166 unsigned long s5p_epll_get_rate(struct clk *clk)
171 static struct clk *s5p_clks[] __initdata = {
184 void __init s5p_register_clocks(unsigned long xtal_freq)
188 clk_ext_xtal_mux.rate = xtal_freq;
190 ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks));
192 printk(KERN_ERR "Failed to register s5p clocks\n");