1 /* linux/arch/arm/plat-s5p/irq-eint.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P - IRQ EINT support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
17 #include <linux/sysdev.h>
18 #include <linux/gpio.h>
20 #include <asm/hardware/vic.h>
22 #include <plat/regs-irqtype.h>
28 #include <plat/gpio-cfg.h>
29 #include <mach/regs-gpio.h>
31 static inline void s5p_irq_eint_mask(unsigned int irq)
35 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
36 mask |= eint_irq_to_bit(irq);
37 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
40 static void s5p_irq_eint_unmask(unsigned int irq)
44 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
45 mask &= ~(eint_irq_to_bit(irq));
46 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
49 static inline void s5p_irq_eint_ack(unsigned int irq)
51 __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
54 static void s5p_irq_eint_maskack(unsigned int irq)
56 /* compiler should in-line these */
57 s5p_irq_eint_mask(irq);
58 s5p_irq_eint_ack(irq);
61 static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
63 int offs = eint_offset(irq);
69 case IRQ_TYPE_EDGE_RISING:
70 newvalue = S5P_EXTINT_RISEEDGE;
73 case IRQ_TYPE_EDGE_FALLING:
74 newvalue = S5P_EXTINT_RISEEDGE;
77 case IRQ_TYPE_EDGE_BOTH:
78 newvalue = S5P_EXTINT_BOTHEDGE;
81 case IRQ_TYPE_LEVEL_LOW:
82 newvalue = S5P_EXTINT_LOWLEV;
85 case IRQ_TYPE_LEVEL_HIGH:
86 newvalue = S5P_EXTINT_HILEV;
90 printk(KERN_ERR "No such irq type %d", type);
94 shift = (offs & 0x7) * 4;
97 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
99 ctrl |= newvalue << shift;
100 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));
102 if ((0 <= offs) && (offs < 8))
103 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
105 else if ((8 <= offs) && (offs < 16))
106 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
108 else if ((16 <= offs) && (offs < 24))
109 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
111 else if ((24 <= offs) && (offs < 32))
112 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
115 printk(KERN_ERR "No such irq number %d", offs);
120 static struct irq_chip s5p_irq_eint = {
122 .mask = s5p_irq_eint_mask,
123 .unmask = s5p_irq_eint_unmask,
124 .mask_ack = s5p_irq_eint_maskack,
125 .ack = s5p_irq_eint_ack,
126 .set_type = s5p_irq_eint_set_type,
128 .set_wake = s3c_irqext_wake,
132 /* s5p_irq_demux_eint
134 * This function demuxes the IRQ from the group0 external interrupts,
135 * from EINTs 16 to 31. It is designed to be inlined into the specific
136 * handler s5p_irq_demux_eintX_Y.
138 * Each EINT pend/mask registers handle eight of them.
140 static inline void s5p_irq_demux_eint(unsigned int start)
143 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
146 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
152 generic_handle_irq(irq - 1 + start);
153 status &= ~(1 << irq);
157 static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
159 s5p_irq_demux_eint(IRQ_EINT(16));
160 s5p_irq_demux_eint(IRQ_EINT(24));
163 static inline void s5p_irq_vic_eint_mask(unsigned int irq)
165 s5p_irq_eint_mask(irq);
168 static void s5p_irq_vic_eint_unmask(unsigned int irq)
170 s5p_irq_eint_unmask(irq);
173 static inline void s5p_irq_vic_eint_ack(unsigned int irq)
175 __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
178 static void s5p_irq_vic_eint_maskack(unsigned int irq)
180 s5p_irq_vic_eint_mask(irq);
181 s5p_irq_vic_eint_ack(irq);
184 static struct irq_chip s5p_irq_vic_eint = {
185 .name = "s5p_vic_eint",
186 .mask = s5p_irq_vic_eint_mask,
187 .unmask = s5p_irq_vic_eint_unmask,
188 .mask_ack = s5p_irq_vic_eint_maskack,
189 .ack = s5p_irq_vic_eint_ack,
190 .set_type = s5p_irq_eint_set_type,
192 .set_wake = s3c_irqext_wake,
196 int __init s5p_init_irq_eint(void)
200 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
201 set_irq_chip(irq, &s5p_irq_vic_eint);
203 for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
204 set_irq_chip(irq, &s5p_irq_eint);
205 set_irq_handler(irq, handle_level_irq);
206 set_irq_flags(irq, IRQF_VALID);
209 set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
213 arch_initcall(s5p_init_irq_eint);