1 /* linux/arch/arm/plat-s5pc1xx/clock.c
3 * Copyright 2009 Samsung Electronics Co.
5 * S5PC1XX Base clock support
7 * Based on plat-s3c64xx/clock.c
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/ioport.h>
18 #include <linux/clk.h>
21 #include <mach/hardware.h>
24 #include <plat/regs-clock.h>
25 #include <plat/devs.h>
26 #include <plat/clock.h>
28 struct clk clk_27m = {
34 static int clk_48m_ctrl(struct clk *clk, int enable)
39 /* can't rely on clock lock, this register has other usages */
40 local_irq_save(flags);
42 val = __raw_readl(S5PC100_CLKSRC1);
44 val |= S5PC100_CLKSRC1_CLK48M_MASK;
46 val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
48 __raw_writel(val, S5PC100_CLKSRC1);
49 local_irq_restore(flags);
54 struct clk clk_48m = {
58 .enable = clk_48m_ctrl,
61 struct clk clk_54m = {
67 static int clk_default_setrate(struct clk *clk, unsigned long rate)
73 static int clk_dummy_enable(struct clk *clk, int enable)
78 struct clk clk_hd0 = {
84 .set_rate = clk_default_setrate,
85 .enable = clk_dummy_enable,
88 struct clk clk_pd0 = {
94 .set_rate = clk_default_setrate,
95 .enable = clk_dummy_enable,
98 static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
100 unsigned int ctrlbit = clk->ctrlbit;
103 con = __raw_readl(reg);
108 __raw_writel(con, reg);
113 static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable)
115 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
118 static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable)
120 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
123 static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable)
125 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
128 static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable)
130 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
133 static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable)
135 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
138 static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable)
140 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
143 static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable)
145 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
148 static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable)
150 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
153 static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable)
155 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
158 static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable)
160 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
163 int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
165 return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
168 int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
170 return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
173 static struct clk s5pc100_init_clocks_disable[] = {
178 .enable = s5pc100_clk_d11_ctrl,
179 .ctrlbit = S5PC100_CLKGATE_D11_DSI,
184 .enable = s5pc100_clk_d11_ctrl,
185 .ctrlbit = S5PC100_CLKGATE_D11_CSI,
190 .enable = s5pc100_clk_d14_ctrl,
191 .ctrlbit = S5PC100_CLKGATE_D14_CCAN0,
196 .enable = s5pc100_clk_d14_ctrl,
197 .ctrlbit = S5PC100_CLKGATE_D14_CCAN1,
202 .enable = s5pc100_clk_d15_ctrl,
203 .ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
208 .enable = s5pc100_clk_d20_ctrl,
209 .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2,
214 .enable = s5pc100_clk_d20_ctrl,
215 .ctrlbit = S5PC100_CLKGATE_D20_I2SD2,
219 static struct clk s5pc100_init_clocks[] = {
220 /* System1 (D0_0) devices */
225 .enable = s5pc100_clk_d00_ctrl,
226 .ctrlbit = S5PC100_CLKGATE_D00_INTC,
231 .enable = s5pc100_clk_d00_ctrl,
232 .ctrlbit = S5PC100_CLKGATE_D00_TZIC,
237 .enable = s5pc100_clk_d00_ctrl,
238 .ctrlbit = S5PC100_CLKGATE_D00_CFCON,
243 .enable = s5pc100_clk_d00_ctrl,
244 .ctrlbit = S5PC100_CLKGATE_D00_MDMA,
249 .enable = s5pc100_clk_d00_ctrl,
250 .ctrlbit = S5PC100_CLKGATE_D00_G2D,
255 .enable = s5pc100_clk_d00_ctrl,
256 .ctrlbit = S5PC100_CLKGATE_D00_SECSS,
261 .enable = s5pc100_clk_d00_ctrl,
262 .ctrlbit = S5PC100_CLKGATE_D00_CSSYS,
265 /* Memory (D0_1) devices */
270 .enable = s5pc100_clk_d01_ctrl,
271 .ctrlbit = S5PC100_CLKGATE_D01_DMC,
276 .enable = s5pc100_clk_d01_ctrl,
277 .ctrlbit = S5PC100_CLKGATE_D01_SROMC,
282 .enable = s5pc100_clk_d01_ctrl,
283 .ctrlbit = S5PC100_CLKGATE_D01_ONENAND,
288 .enable = s5pc100_clk_d01_ctrl,
289 .ctrlbit = S5PC100_CLKGATE_D01_NFCON,
294 .enable = s5pc100_clk_d01_ctrl,
295 .ctrlbit = S5PC100_CLKGATE_D01_INTMEM,
300 .enable = s5pc100_clk_d01_ctrl,
301 .ctrlbit = S5PC100_CLKGATE_D01_EBI,
304 /* System2 (D0_2) devices */
309 .enable = s5pc100_clk_d02_ctrl,
310 .ctrlbit = S5PC100_CLKGATE_D02_SECKEY,
315 .enable = s5pc100_clk_d02_ctrl,
316 .ctrlbit = S5PC100_CLKGATE_D02_SDM,
319 /* File (D1_0) devices */
324 .enable = s5pc100_clk_d10_ctrl,
325 .ctrlbit = S5PC100_CLKGATE_D10_PDMA0,
330 .enable = s5pc100_clk_d10_ctrl,
331 .ctrlbit = S5PC100_CLKGATE_D10_PDMA1,
336 .enable = s5pc100_clk_d10_ctrl,
337 .ctrlbit = S5PC100_CLKGATE_D10_USBHOST,
342 .enable = s5pc100_clk_d10_ctrl,
343 .ctrlbit = S5PC100_CLKGATE_D10_USBOTG,
348 .enable = s5pc100_clk_d10_ctrl,
349 .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF,
354 .enable = s5pc100_clk_d10_ctrl,
355 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0,
360 .enable = s5pc100_clk_d10_ctrl,
361 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1,
366 .enable = s5pc100_clk_d10_ctrl,
367 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2,
370 /* Multimedia1 (D1_1) devices */
375 .enable = s5pc100_clk_d11_ctrl,
376 .ctrlbit = S5PC100_CLKGATE_D11_LCD,
381 .enable = s5pc100_clk_d11_ctrl,
382 .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR,
387 .enable = s5pc100_clk_d11_ctrl,
388 .ctrlbit = S5PC100_CLKGATE_D11_FIMC0,
393 .enable = s5pc100_clk_d11_ctrl,
394 .ctrlbit = S5PC100_CLKGATE_D11_FIMC1,
399 .enable = s5pc100_clk_d11_ctrl,
400 .ctrlbit = S5PC100_CLKGATE_D11_FIMC2,
405 .enable = s5pc100_clk_d11_ctrl,
406 .ctrlbit = S5PC100_CLKGATE_D11_JPEG,
411 .enable = s5pc100_clk_d11_ctrl,
412 .ctrlbit = S5PC100_CLKGATE_D11_G3D,
415 /* Multimedia2 (D1_2) devices */
420 .enable = s5pc100_clk_d12_ctrl,
421 .ctrlbit = S5PC100_CLKGATE_D12_TV,
426 .enable = s5pc100_clk_d12_ctrl,
427 .ctrlbit = S5PC100_CLKGATE_D12_VP,
432 .enable = s5pc100_clk_d12_ctrl,
433 .ctrlbit = S5PC100_CLKGATE_D12_MIXER,
438 .enable = s5pc100_clk_d12_ctrl,
439 .ctrlbit = S5PC100_CLKGATE_D12_HDMI,
444 .enable = s5pc100_clk_d12_ctrl,
445 .ctrlbit = S5PC100_CLKGATE_D12_MFC,
448 /* System (D1_3) devices */
453 .enable = s5pc100_clk_d13_ctrl,
454 .ctrlbit = S5PC100_CLKGATE_D13_CHIPID,
459 .enable = s5pc100_clk_d13_ctrl,
460 .ctrlbit = S5PC100_CLKGATE_D13_GPIO,
465 .enable = s5pc100_clk_d13_ctrl,
466 .ctrlbit = S5PC100_CLKGATE_D13_APC,
471 .enable = s5pc100_clk_d13_ctrl,
472 .ctrlbit = S5PC100_CLKGATE_D13_IEC,
477 .enable = s5pc100_clk_d13_ctrl,
478 .ctrlbit = S5PC100_CLKGATE_D13_PWM,
483 .enable = s5pc100_clk_d13_ctrl,
484 .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER,
489 .enable = s5pc100_clk_d13_ctrl,
490 .ctrlbit = S5PC100_CLKGATE_D13_WDT,
495 .enable = s5pc100_clk_d13_ctrl,
496 .ctrlbit = S5PC100_CLKGATE_D13_RTC,
499 /* Connectivity (D1_4) devices */
504 .enable = s5pc100_clk_d14_ctrl,
505 .ctrlbit = S5PC100_CLKGATE_D14_UART0,
510 .enable = s5pc100_clk_d14_ctrl,
511 .ctrlbit = S5PC100_CLKGATE_D14_UART1,
516 .enable = s5pc100_clk_d14_ctrl,
517 .ctrlbit = S5PC100_CLKGATE_D14_UART2,
522 .enable = s5pc100_clk_d14_ctrl,
523 .ctrlbit = S5PC100_CLKGATE_D14_UART3,
528 .enable = s5pc100_clk_d14_ctrl,
529 .ctrlbit = S5PC100_CLKGATE_D14_IIC,
534 .enable = s5pc100_clk_d14_ctrl,
535 .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC,
540 .enable = s5pc100_clk_d14_ctrl,
541 .ctrlbit = S5PC100_CLKGATE_D14_SPI0,
546 .enable = s5pc100_clk_d14_ctrl,
547 .ctrlbit = S5PC100_CLKGATE_D14_SPI1,
552 .enable = s5pc100_clk_d14_ctrl,
553 .ctrlbit = S5PC100_CLKGATE_D14_SPI2,
558 .enable = s5pc100_clk_d14_ctrl,
559 .ctrlbit = S5PC100_CLKGATE_D14_IRDA,
564 .enable = s5pc100_clk_d14_ctrl,
565 .ctrlbit = S5PC100_CLKGATE_D14_HSITX,
570 .enable = s5pc100_clk_d14_ctrl,
571 .ctrlbit = S5PC100_CLKGATE_D14_HSIRX,
574 /* Audio (D1_5) devices */
579 .enable = s5pc100_clk_d15_ctrl,
580 .ctrlbit = S5PC100_CLKGATE_D15_IIS0,
585 .enable = s5pc100_clk_d15_ctrl,
586 .ctrlbit = S5PC100_CLKGATE_D15_IIS1,
591 .enable = s5pc100_clk_d15_ctrl,
592 .ctrlbit = S5PC100_CLKGATE_D15_IIS2,
597 .enable = s5pc100_clk_d15_ctrl,
598 .ctrlbit = S5PC100_CLKGATE_D15_AC97,
603 .enable = s5pc100_clk_d15_ctrl,
604 .ctrlbit = S5PC100_CLKGATE_D15_PCM0,
609 .enable = s5pc100_clk_d15_ctrl,
610 .ctrlbit = S5PC100_CLKGATE_D15_PCM1,
615 .enable = s5pc100_clk_d15_ctrl,
616 .ctrlbit = S5PC100_CLKGATE_D15_SPDIF,
621 .enable = s5pc100_clk_d15_ctrl,
622 .ctrlbit = S5PC100_CLKGATE_D15_TSADC,
627 .enable = s5pc100_clk_d15_ctrl,
628 .ctrlbit = S5PC100_CLKGATE_D15_CG,
631 /* Audio (D2_0) devices: all disabled */
633 /* Special Clocks 0 */
638 .enable = s5pc100_sclk0_ctrl,
639 .ctrlbit = S5PC100_CLKGATE_SCLK0_HPM,
641 .name = "sclk_onenand",
644 .enable = s5pc100_sclk0_ctrl,
645 .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND,
650 .enable = s5pc100_sclk0_ctrl,
651 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48,
656 .enable = s5pc100_sclk0_ctrl,
657 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48,
662 .enable = s5pc100_sclk0_ctrl,
663 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48,
668 .enable = s5pc100_sclk0_ctrl,
669 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48,
674 .enable = s5pc100_sclk0_ctrl,
675 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48,
680 .enable = s5pc100_sclk0_ctrl,
681 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48,
683 /* Special Clocks 1 */
686 static struct clk *clks[] __initdata = {
694 void __init s5pc1xx_register_clocks(void)
701 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
703 clkp = s5pc100_init_clocks;
704 size = ARRAY_SIZE(s5pc100_init_clocks);
706 for (ptr = 0; ptr < size; ptr++, clkp++) {
707 ret = s3c24xx_register_clock(clkp);
709 printk(KERN_ERR "Failed to register clock %s (%d)\n",
714 clkp = s5pc100_init_clocks_disable;
715 size = ARRAY_SIZE(s5pc100_init_clocks_disable);
717 for (ptr = 0; ptr < size; ptr++, clkp++) {
718 ret = s3c24xx_register_clock(clkp);
720 printk(KERN_ERR "Failed to register clock %s (%d)\n",
724 (clkp->enable)(clkp, 0);