2 * arch/arm/plat-s5pc1xx/gpiolib.c
4 * Copyright 2009 Samsung Electronics Co
5 * Kyungmin Park <kyungmin.park@samsung.com>
7 * S5PC1XX - GPIOlib support
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/irq.h>
17 #include <linux/gpio.h>
20 #include <mach/gpio-core.h>
22 #include <plat/gpio-cfg.h>
23 #include <plat/gpio-cfg-helpers.h>
24 #include <plat/regs-gpio.h>
26 /* S5PC100 GPIO bank summary:
28 * Bank GPIOs Style INT Type
39 * F3 4 4Bit GPIO_INT10
40 * G0 8 4Bit GPIO_INT11
41 * G1 3 4Bit GPIO_INT12
42 * G2 7 4Bit GPIO_INT13
43 * G3 7 4Bit GPIO_INT14
49 * J0 8 4Bit GPIO_INT16
50 * J1 5 4Bit GPIO_INT17
51 * J2 8 4Bit GPIO_INT18
52 * J3 8 4Bit GPIO_INT19
53 * J4 4 4Bit GPIO_INT20
64 #define OFF_GPCON (0x00)
65 #define OFF_GPDAT (0x04)
67 #define con_4bit_shift(__off) ((__off) * 4)
70 #define gpio_dbg(x...) do { } while (0)
72 #define gpio_dbg(x...) printk(KERN_DEBUG x)
75 /* The s5pc1xx_gpiolib routines are to control the gpio banks where
76 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
79 * base + 0x00: Control register, 4 bits per gpio
80 * gpio n: 4 bits starting at (4*n)
81 * 0000 = input, 0001 = output, others mean special-function
82 * base + 0x04: Data register, 1 bit per gpio
85 * Note, since the data register is one bit per gpio and is at base + 0x4
86 * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
90 static int s5pc1xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
92 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
93 void __iomem *base = ourchip->base;
96 con = __raw_readl(base + OFF_GPCON);
97 con &= ~(0xf << con_4bit_shift(offset));
98 __raw_writel(con, base + OFF_GPCON);
100 gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
105 static int s5pc1xx_gpiolib_output(struct gpio_chip *chip,
106 unsigned offset, int value)
108 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
109 void __iomem *base = ourchip->base;
113 con = __raw_readl(base + OFF_GPCON);
114 con &= ~(0xf << con_4bit_shift(offset));
115 con |= 0x1 << con_4bit_shift(offset);
117 dat = __raw_readl(base + OFF_GPDAT);
121 dat &= ~(1 << offset);
123 __raw_writel(dat, base + OFF_GPDAT);
124 __raw_writel(con, base + OFF_GPCON);
125 __raw_writel(dat, base + OFF_GPDAT);
127 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
132 static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
134 return S3C_IRQ_GPIO(chip->base + offset);
137 static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
141 base = chip->base - S5PC100_GPH0(0);
143 return IRQ_EINT(offset);
144 base = chip->base - S5PC100_GPH1(0);
146 return IRQ_EINT(8 + offset);
147 base = chip->base - S5PC100_GPH2(0);
149 return IRQ_EINT(16 + offset);
150 base = chip->base - S5PC100_GPH3(0);
152 return IRQ_EINT(24 + offset);
156 static struct s3c_gpio_cfg gpio_cfg = {
157 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
158 .set_pull = s3c_gpio_setpull_updown,
159 .get_pull = s3c_gpio_getpull_updown,
162 static struct s3c_gpio_cfg gpio_cfg_eint = {
164 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
165 .set_pull = s3c_gpio_setpull_updown,
166 .get_pull = s3c_gpio_getpull_updown,
169 static struct s3c_gpio_cfg gpio_cfg_noint = {
170 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
171 .set_pull = s3c_gpio_setpull_updown,
172 .get_pull = s3c_gpio_getpull_updown,
175 static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
177 .base = S5PC100_GPA0_BASE,
180 .base = S5PC100_GPA0(0),
181 .ngpio = S5PC100_GPIO_A0_NR,
185 .base = S5PC100_GPA1_BASE,
188 .base = S5PC100_GPA1(0),
189 .ngpio = S5PC100_GPIO_A1_NR,
193 .base = S5PC100_GPB_BASE,
196 .base = S5PC100_GPB(0),
197 .ngpio = S5PC100_GPIO_B_NR,
201 .base = S5PC100_GPC_BASE,
204 .base = S5PC100_GPC(0),
205 .ngpio = S5PC100_GPIO_C_NR,
209 .base = S5PC100_GPD_BASE,
212 .base = S5PC100_GPD(0),
213 .ngpio = S5PC100_GPIO_D_NR,
217 .base = S5PC100_GPE0_BASE,
220 .base = S5PC100_GPE0(0),
221 .ngpio = S5PC100_GPIO_E0_NR,
225 .base = S5PC100_GPE1_BASE,
228 .base = S5PC100_GPE1(0),
229 .ngpio = S5PC100_GPIO_E1_NR,
233 .base = S5PC100_GPF0_BASE,
236 .base = S5PC100_GPF0(0),
237 .ngpio = S5PC100_GPIO_F0_NR,
241 .base = S5PC100_GPF1_BASE,
244 .base = S5PC100_GPF1(0),
245 .ngpio = S5PC100_GPIO_F1_NR,
249 .base = S5PC100_GPF2_BASE,
252 .base = S5PC100_GPF2(0),
253 .ngpio = S5PC100_GPIO_F2_NR,
257 .base = S5PC100_GPF3_BASE,
260 .base = S5PC100_GPF3(0),
261 .ngpio = S5PC100_GPIO_F3_NR,
265 .base = S5PC100_GPG0_BASE,
268 .base = S5PC100_GPG0(0),
269 .ngpio = S5PC100_GPIO_G0_NR,
273 .base = S5PC100_GPG1_BASE,
276 .base = S5PC100_GPG1(0),
277 .ngpio = S5PC100_GPIO_G1_NR,
281 .base = S5PC100_GPG2_BASE,
284 .base = S5PC100_GPG2(0),
285 .ngpio = S5PC100_GPIO_G2_NR,
289 .base = S5PC100_GPG3_BASE,
292 .base = S5PC100_GPG3(0),
293 .ngpio = S5PC100_GPIO_G3_NR,
297 .base = S5PC100_GPH0_BASE,
298 .config = &gpio_cfg_eint,
300 .base = S5PC100_GPH0(0),
301 .ngpio = S5PC100_GPIO_H0_NR,
305 .base = S5PC100_GPH1_BASE,
306 .config = &gpio_cfg_eint,
308 .base = S5PC100_GPH1(0),
309 .ngpio = S5PC100_GPIO_H1_NR,
313 .base = S5PC100_GPH2_BASE,
314 .config = &gpio_cfg_eint,
316 .base = S5PC100_GPH2(0),
317 .ngpio = S5PC100_GPIO_H2_NR,
321 .base = S5PC100_GPH3_BASE,
322 .config = &gpio_cfg_eint,
324 .base = S5PC100_GPH3(0),
325 .ngpio = S5PC100_GPIO_H3_NR,
329 .base = S5PC100_GPI_BASE,
332 .base = S5PC100_GPI(0),
333 .ngpio = S5PC100_GPIO_I_NR,
337 .base = S5PC100_GPJ0_BASE,
340 .base = S5PC100_GPJ0(0),
341 .ngpio = S5PC100_GPIO_J0_NR,
345 .base = S5PC100_GPJ1_BASE,
348 .base = S5PC100_GPJ1(0),
349 .ngpio = S5PC100_GPIO_J1_NR,
353 .base = S5PC100_GPJ2_BASE,
356 .base = S5PC100_GPJ2(0),
357 .ngpio = S5PC100_GPIO_J2_NR,
361 .base = S5PC100_GPJ3_BASE,
364 .base = S5PC100_GPJ3(0),
365 .ngpio = S5PC100_GPIO_J3_NR,
369 .base = S5PC100_GPJ4_BASE,
372 .base = S5PC100_GPJ4(0),
373 .ngpio = S5PC100_GPIO_J4_NR,
377 .base = S5PC100_GPK0_BASE,
378 .config = &gpio_cfg_noint,
380 .base = S5PC100_GPK0(0),
381 .ngpio = S5PC100_GPIO_K0_NR,
385 .base = S5PC100_GPK1_BASE,
386 .config = &gpio_cfg_noint,
388 .base = S5PC100_GPK1(0),
389 .ngpio = S5PC100_GPIO_K1_NR,
393 .base = S5PC100_GPK2_BASE,
394 .config = &gpio_cfg_noint,
396 .base = S5PC100_GPK2(0),
397 .ngpio = S5PC100_GPIO_K2_NR,
401 .base = S5PC100_GPK3_BASE,
402 .config = &gpio_cfg_noint,
404 .base = S5PC100_GPK3(0),
405 .ngpio = S5PC100_GPIO_K3_NR,
409 .base = S5PC100_GPL0_BASE,
410 .config = &gpio_cfg_noint,
412 .base = S5PC100_GPL0(0),
413 .ngpio = S5PC100_GPIO_L0_NR,
417 .base = S5PC100_GPL1_BASE,
418 .config = &gpio_cfg_noint,
420 .base = S5PC100_GPL1(0),
421 .ngpio = S5PC100_GPIO_L1_NR,
425 .base = S5PC100_GPL2_BASE,
426 .config = &gpio_cfg_noint,
428 .base = S5PC100_GPL2(0),
429 .ngpio = S5PC100_GPIO_L2_NR,
433 .base = S5PC100_GPL3_BASE,
434 .config = &gpio_cfg_noint,
436 .base = S5PC100_GPL3(0),
437 .ngpio = S5PC100_GPIO_L3_NR,
441 .base = S5PC100_GPL4_BASE,
442 .config = &gpio_cfg_noint,
444 .base = S5PC100_GPL4(0),
445 .ngpio = S5PC100_GPIO_L4_NR,
451 /* FIXME move from irq-gpio.c */
452 extern struct irq_chip s5pc1xx_gpioint;
453 extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
455 static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip)
457 chip->chip.direction_input = s5pc1xx_gpiolib_input;
458 chip->chip.direction_output = s5pc1xx_gpiolib_output;
459 chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
462 if (chip->config == &gpio_cfg) {
465 chip->chip.to_irq = s5pc1xx_gpiolib_to_irq;
467 for (i = 0; i < chip->chip.ngpio; i++) {
468 irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
469 set_irq_chip(irq, &s5pc1xx_gpioint);
470 set_irq_data(irq, &chip->chip);
471 set_irq_handler(irq, handle_level_irq);
472 set_irq_flags(irq, IRQF_VALID);
474 } else if (chip->config == &gpio_cfg_eint)
475 chip->chip.to_irq = s5pc1xx_gpiolib_to_eint;
478 static __init void s5pc1xx_gpiolib_add(struct s3c_gpio_chip *chips,
480 void (*fn)(struct s3c_gpio_chip *))
482 for (; nr_chips > 0; nr_chips--, chips++) {
485 s3c_gpiolib_add(chips);
489 static __init int s5pc1xx_gpiolib_init(void)
491 struct s3c_gpio_chip *chips;
494 chips = s5pc100_gpio_chips;
495 nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
497 s5pc1xx_gpiolib_add(chips, nr_chips, s5pc1xx_gpiolib_link);
499 set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler);
503 core_initcall(s5pc1xx_gpiolib_init);