1 /* linux/arch/arm/plat-s3c/gpio-config.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008-2010 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C series GPIO configuration core
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/gpio.h>
20 #include <plat/gpio-core.h>
21 #include <plat/gpio-cfg.h>
22 #include <plat/gpio-cfg-helpers.h>
24 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
26 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
34 offset = pin - chip->chip.base;
36 s3c_gpio_lock(chip, flags);
37 ret = s3c_gpio_do_setcfg(chip, offset, config);
38 s3c_gpio_unlock(chip, flags);
42 EXPORT_SYMBOL(s3c_gpio_cfgpin);
44 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
49 for (; nr > 0; nr--, start++) {
50 ret = s3c_gpio_cfgpin(start, cfg);
57 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
59 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
60 unsigned int cfg, s3c_gpio_pull_t pull)
64 for (; nr > 0; nr--, start++) {
65 s3c_gpio_setpull(start, pull);
66 ret = s3c_gpio_cfgpin(start, cfg);
73 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
75 unsigned s3c_gpio_getcfg(unsigned int pin)
77 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
83 offset = pin - chip->chip.base;
85 s3c_gpio_lock(chip, flags);
86 ret = s3c_gpio_do_getcfg(chip, offset);
87 s3c_gpio_unlock(chip, flags);
92 EXPORT_SYMBOL(s3c_gpio_getcfg);
95 int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
97 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
104 offset = pin - chip->chip.base;
106 s3c_gpio_lock(chip, flags);
107 ret = s3c_gpio_do_setpull(chip, offset, pull);
108 s3c_gpio_unlock(chip, flags);
112 EXPORT_SYMBOL(s3c_gpio_setpull);
114 #ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
115 int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
116 unsigned int off, unsigned int cfg)
118 void __iomem *reg = chip->base;
119 unsigned int shift = off;
122 if (s3c_gpio_is_cfg_special(cfg)) {
125 /* Map output to 0, and SFN2 to 1 */
133 con = __raw_readl(reg);
134 con &= ~(0x1 << shift);
136 __raw_writel(con, reg);
141 unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
146 con = __raw_readl(chip->base);
151 return S3C_GPIO_SFN(con);
154 int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
155 unsigned int off, unsigned int cfg)
157 void __iomem *reg = chip->base;
158 unsigned int shift = off * 2;
161 if (s3c_gpio_is_cfg_special(cfg)) {
169 con = __raw_readl(reg);
170 con &= ~(0x3 << shift);
172 __raw_writel(con, reg);
177 unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
182 con = __raw_readl(chip->base);
186 /* this conversion works for IN and OUT as well as special mode */
187 return S3C_GPIO_SPECIAL(con);
191 #ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
192 int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
193 unsigned int off, unsigned int cfg)
195 void __iomem *reg = chip->base;
196 unsigned int shift = (off & 7) * 4;
199 if (off < 8 && chip->chip.ngpio > 8)
202 if (s3c_gpio_is_cfg_special(cfg)) {
207 con = __raw_readl(reg);
208 con &= ~(0xf << shift);
210 __raw_writel(con, reg);
215 unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
218 void __iomem *reg = chip->base;
219 unsigned int shift = (off & 7) * 4;
222 if (off < 8 && chip->chip.ngpio > 8)
225 con = __raw_readl(reg);
229 /* this conversion works for IN and OUT as well as special mode */
230 return S3C_GPIO_SPECIAL(con);
233 #endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
235 #ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
236 int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
237 unsigned int off, s3c_gpio_pull_t pull)
239 void __iomem *reg = chip->base + 0x08;
243 pup = __raw_readl(reg);
244 pup &= ~(3 << shift);
245 pup |= pull << shift;
246 __raw_writel(pup, reg);
251 s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
254 void __iomem *reg = chip->base + 0x08;
256 u32 pup = __raw_readl(reg);
260 return (__force s3c_gpio_pull_t)pup;
264 #ifdef CONFIG_S3C_GPIO_PULL_UP
265 int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
266 unsigned int off, s3c_gpio_pull_t pull)
268 void __iomem *reg = chip->base + 0x08;
269 u32 pup = __raw_readl(reg);
271 pup = __raw_readl(reg);
273 if (pup == S3C_GPIO_PULL_UP)
275 else if (pup == S3C_GPIO_PULL_NONE)
280 __raw_writel(pup, reg);
284 s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
287 void __iomem *reg = chip->base + 0x08;
288 u32 pup = __raw_readl(reg);
291 return pup ? S3C_GPIO_PULL_NONE : S3C_GPIO_PULL_UP;
293 #endif /* CONFIG_S3C_GPIO_PULL_UP */
295 #ifdef CONFIG_S5P_GPIO_DRVSTR
296 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
298 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
307 off = pin - chip->chip.base;
309 reg = chip->base + 0x0C;
311 drvstr = __raw_readl(reg);
312 drvstr = drvstr >> shift;
315 return (__force s5p_gpio_drvstr_t)drvstr;
317 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
319 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
321 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
330 off = pin - chip->chip.base;
332 reg = chip->base + 0x0C;
334 tmp = __raw_readl(reg);
335 tmp &= ~(0x3 << shift);
336 tmp |= drvstr << shift;
338 __raw_writel(tmp, reg);
342 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
343 #endif /* CONFIG_S5P_GPIO_DRVSTR */