2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * S5P - IRQ EINT support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
16 #include <linux/device.h>
17 #include <linux/gpio.h>
18 #include <linux/irqchip/arm-vic.h>
21 #include <plat/regs-irqtype.h>
27 #include <plat/gpio-cfg.h>
28 #include <mach/regs-gpio.h>
30 static inline void s5p_irq_eint_mask(struct irq_data *data)
34 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
35 mask |= eint_irq_to_bit(data->irq);
36 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
39 static void s5p_irq_eint_unmask(struct irq_data *data)
43 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
44 mask &= ~(eint_irq_to_bit(data->irq));
45 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
48 static inline void s5p_irq_eint_ack(struct irq_data *data)
50 __raw_writel(eint_irq_to_bit(data->irq),
51 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
54 static void s5p_irq_eint_maskack(struct irq_data *data)
56 /* compiler should in-line these */
57 s5p_irq_eint_mask(data);
58 s5p_irq_eint_ack(data);
61 static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type)
63 int offs = EINT_OFFSET(data->irq);
69 case IRQ_TYPE_EDGE_RISING:
70 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
73 case IRQ_TYPE_EDGE_FALLING:
74 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
77 case IRQ_TYPE_EDGE_BOTH:
78 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
81 case IRQ_TYPE_LEVEL_LOW:
82 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
85 case IRQ_TYPE_LEVEL_HIGH:
86 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
90 printk(KERN_ERR "No such irq type %d", type);
94 shift = (offs & 0x7) * 4;
97 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
99 ctrl |= newvalue << shift;
100 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
102 if ((0 <= offs) && (offs < 8))
103 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
105 else if ((8 <= offs) && (offs < 16))
106 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
108 else if ((16 <= offs) && (offs < 24))
109 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
111 else if ((24 <= offs) && (offs < 32))
112 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
115 printk(KERN_ERR "No such irq number %d", offs);
120 static struct irq_chip s5p_irq_eint = {
122 .irq_mask = s5p_irq_eint_mask,
123 .irq_unmask = s5p_irq_eint_unmask,
124 .irq_mask_ack = s5p_irq_eint_maskack,
125 .irq_ack = s5p_irq_eint_ack,
126 .irq_set_type = s5p_irq_eint_set_type,
128 .irq_set_wake = s3c_irqext_wake,
132 /* s5p_irq_demux_eint
134 * This function demuxes the IRQ from the group0 external interrupts,
135 * from EINTs 16 to 31. It is designed to be inlined into the specific
136 * handler s5p_irq_demux_eintX_Y.
138 * Each EINT pend/mask registers handle eight of them.
140 static inline void s5p_irq_demux_eint(unsigned int start)
142 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
143 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
150 irq = fls(status) - 1;
151 generic_handle_irq(irq + start);
152 status &= ~(1 << irq);
156 static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
158 s5p_irq_demux_eint(IRQ_EINT(16));
159 s5p_irq_demux_eint(IRQ_EINT(24));
162 static inline void s5p_irq_vic_eint_mask(struct irq_data *data)
164 void __iomem *base = irq_data_get_irq_chip_data(data);
166 s5p_irq_eint_mask(data);
167 writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR);
170 static void s5p_irq_vic_eint_unmask(struct irq_data *data)
172 void __iomem *base = irq_data_get_irq_chip_data(data);
174 s5p_irq_eint_unmask(data);
175 writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE);
178 static inline void s5p_irq_vic_eint_ack(struct irq_data *data)
180 __raw_writel(eint_irq_to_bit(data->irq),
181 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
184 static void s5p_irq_vic_eint_maskack(struct irq_data *data)
186 s5p_irq_vic_eint_mask(data);
187 s5p_irq_vic_eint_ack(data);
190 static struct irq_chip s5p_irq_vic_eint = {
191 .name = "s5p_vic_eint",
192 .irq_mask = s5p_irq_vic_eint_mask,
193 .irq_unmask = s5p_irq_vic_eint_unmask,
194 .irq_mask_ack = s5p_irq_vic_eint_maskack,
195 .irq_ack = s5p_irq_vic_eint_ack,
196 .irq_set_type = s5p_irq_eint_set_type,
198 .irq_set_wake = s3c_irqext_wake,
202 static int __init s5p_init_irq_eint(void)
206 if (of_have_populated_dt())
209 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
210 irq_set_chip(irq, &s5p_irq_vic_eint);
212 for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
213 irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
214 set_irq_flags(irq, IRQF_VALID);
217 irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
221 arch_initcall(s5p_init_irq_eint);