2 * arch/arm/plat-spear/time.c
4 * Copyright (C) 2009 ST Microelectronics
5 * Shiraz Hashim<shiraz.hashim@st.com>
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/clk.h>
13 #include <linux/clockchips.h>
14 #include <linux/clocksource.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
19 #include <linux/kernel.h>
20 #include <linux/time.h>
21 #include <linux/irq.h>
22 #include <asm/mach/time.h>
23 #include <mach/irqs.h>
24 #include <mach/hardware.h>
25 #include <mach/spear.h>
26 #include <mach/generic.h>
29 * We would use TIMER0 and TIMER1 as clockevent and clocksource.
30 * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
31 * they share same functional clock. Any change in one's functional clock will
32 * also affect other timer.
35 #define CLKEVT 0 /* gpt0, channel0 as clockevent */
36 #define CLKSRC 1 /* gpt0, channel1 as clocksource */
38 /* Register offsets, x is channel number */
39 #define CR(x) ((x) * 0x80 + 0x80)
40 #define IR(x) ((x) * 0x80 + 0x84)
41 #define LOAD(x) ((x) * 0x80 + 0x88)
42 #define COUNT(x) ((x) * 0x80 + 0x8C)
44 /* Reg bit definitions */
45 #define CTRL_INT_ENABLE 0x0100
46 #define CTRL_ENABLE 0x0020
47 #define CTRL_ONE_SHOT 0x0010
49 #define CTRL_PRESCALER1 0x0
50 #define CTRL_PRESCALER2 0x1
51 #define CTRL_PRESCALER4 0x2
52 #define CTRL_PRESCALER8 0x3
53 #define CTRL_PRESCALER16 0x4
54 #define CTRL_PRESCALER32 0x5
55 #define CTRL_PRESCALER64 0x6
56 #define CTRL_PRESCALER128 0x7
57 #define CTRL_PRESCALER256 0x8
59 #define INT_STATUS 0x1
61 static __iomem void *gpt_base;
62 static struct clk *gpt_clk;
64 static void clockevent_set_mode(enum clock_event_mode mode,
65 struct clock_event_device *clk_event_dev);
66 static int clockevent_next_event(unsigned long evt,
67 struct clock_event_device *clk_event_dev);
70 * Following clocksource_set_clock and clockevent_set_clock picked
71 * from arch/mips/kernel/time.c
74 void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock)
79 /* Find a shift value */
80 for (shift = 32; shift > 0; shift--) {
81 temp = (u64) NSEC_PER_SEC << shift;
83 if ((temp >> 32) == 0)
87 cs->mult = (u32) temp;
90 void __init clockevent_set_clock(struct clock_event_device *cd,
96 /* Find a shift value */
97 for (shift = 32; shift > 0; shift--) {
98 temp = (u64) clock << shift;
99 do_div(temp, NSEC_PER_SEC);
100 if ((temp >> 32) == 0)
104 cd->mult = (u32) temp;
107 static cycle_t clocksource_read_cycles(struct clocksource *cs)
109 return (cycle_t) readw(gpt_base + COUNT(CLKSRC));
112 static struct clocksource clksrc = {
114 .rating = 200, /* its a pretty decent clock */
115 .read = clocksource_read_cycles,
116 .mask = 0xFFFF, /* 16 bits */
117 .mult = 0, /* to be computed */
118 .shift = 0, /* to be computed */
119 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
122 static void spear_clocksource_init(void)
127 /* program the prescaler (/256)*/
128 writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
130 /* find out actual clock driving Timer */
131 tick_rate = clk_get_rate(gpt_clk);
132 tick_rate >>= CTRL_PRESCALER256;
134 writew(0xFFFF, gpt_base + LOAD(CLKSRC));
136 val = readw(gpt_base + CR(CLKSRC));
137 val &= ~CTRL_ONE_SHOT; /* autoreload mode */
139 writew(val, gpt_base + CR(CLKSRC));
141 clocksource_set_clock(&clksrc, tick_rate);
143 /* register the clocksource */
144 clocksource_register(&clksrc);
147 static struct clock_event_device clkevt = {
149 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
150 .set_mode = clockevent_set_mode,
151 .set_next_event = clockevent_next_event,
152 .shift = 0, /* to be computed */
155 static void clockevent_set_mode(enum clock_event_mode mode,
156 struct clock_event_device *clk_event_dev)
162 val = readw(gpt_base + CR(CLKEVT));
164 writew(val, gpt_base + CR(CLKEVT));
167 case CLOCK_EVT_MODE_PERIODIC:
168 period = clk_get_rate(gpt_clk) / HZ;
169 period >>= CTRL_PRESCALER16;
170 writew(period, gpt_base + LOAD(CLKEVT));
172 val = readw(gpt_base + CR(CLKEVT));
173 val &= ~CTRL_ONE_SHOT;
174 val |= CTRL_ENABLE | CTRL_INT_ENABLE;
175 writew(val, gpt_base + CR(CLKEVT));
178 case CLOCK_EVT_MODE_ONESHOT:
179 val = readw(gpt_base + CR(CLKEVT));
180 val |= CTRL_ONE_SHOT;
181 writew(val, gpt_base + CR(CLKEVT));
184 case CLOCK_EVT_MODE_UNUSED:
185 case CLOCK_EVT_MODE_SHUTDOWN:
186 case CLOCK_EVT_MODE_RESUME:
190 pr_err("Invalid mode requested\n");
195 static int clockevent_next_event(unsigned long cycles,
196 struct clock_event_device *clk_event_dev)
200 writew(cycles, gpt_base + LOAD(CLKEVT));
202 val = readw(gpt_base + CR(CLKEVT));
203 val |= CTRL_ENABLE | CTRL_INT_ENABLE;
204 writew(val, gpt_base + CR(CLKEVT));
209 static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
211 struct clock_event_device *evt = &clkevt;
213 writew(INT_STATUS, gpt_base + IR(CLKEVT));
215 evt->event_handler(evt);
220 static struct irqaction spear_timer_irq = {
222 .flags = IRQF_DISABLED | IRQF_TIMER,
223 .handler = spear_timer_interrupt
226 static void __init spear_clockevent_init(void)
230 /* program the prescaler */
231 writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
233 tick_rate = clk_get_rate(gpt_clk);
234 tick_rate >>= CTRL_PRESCALER16;
236 clockevent_set_clock(&clkevt, tick_rate);
238 clkevt.max_delta_ns = clockevent_delta2ns(0xfff0,
240 clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt);
242 clkevt.cpumask = cpumask_of(0);
244 clockevents_register_device(&clkevt);
246 setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq);
249 void __init spear_setup_timer(void)
251 struct clk *pll3_clk;
253 if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) {
254 pr_err("%s:cannot get IO addr\n", __func__);
258 gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K);
260 pr_err("%s:ioremap failed for gpt\n", __func__);
264 gpt_clk = clk_get_sys("gpt0", NULL);
266 pr_err("%s:couldn't get clk for gpt\n", __func__);
270 pll3_clk = clk_get(NULL, "pll3_48m_clk");
272 pr_err("%s:couldn't get PLL3 as parent for gpt\n", __func__);
276 clk_set_parent(gpt_clk, pll3_clk);
278 spear_clockevent_init();
279 spear_clocksource_init();
287 release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
290 struct sys_timer spear_sys_timer = {
291 .init = spear_setup_timer,