3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
23 select BUILDTIME_EXTABLE_SORT
24 select CLONE_BACKWARDS
26 select CPU_PM if (SUSPEND || CPU_IDLE)
27 select DCACHE_WORD_ACCESS
29 select GENERIC_ALLOCATOR
30 select GENERIC_CLOCKEVENTS
31 select GENERIC_CLOCKEVENTS_BROADCAST
32 select GENERIC_CPU_AUTOPROBE
33 select GENERIC_EARLY_IOREMAP
34 select GENERIC_IRQ_PROBE
35 select GENERIC_IRQ_SHOW
36 select GENERIC_IRQ_SHOW_LEVEL
37 select GENERIC_PCI_IOMAP
38 select GENERIC_SCHED_CLOCK
39 select GENERIC_SMP_IDLE_THREAD
40 select GENERIC_STRNCPY_FROM_USER
41 select GENERIC_STRNLEN_USER
42 select GENERIC_TIME_VSYSCALL
43 select HANDLE_DOMAIN_IRQ
44 select HARDIRQS_SW_RESEND
45 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
46 select HAVE_ARCH_AUDITSYSCALL
47 select HAVE_ARCH_BITREVERSE
48 select HAVE_ARCH_JUMP_LABEL
50 select HAVE_ARCH_SECCOMP_FILTER
51 select HAVE_ARCH_TRACEHOOK
53 select HAVE_C_RECORDMCOUNT
54 select HAVE_CC_STACKPROTECTOR
55 select HAVE_CMPXCHG_DOUBLE
56 select HAVE_CMPXCHG_LOCAL
57 select HAVE_DEBUG_BUGVERBOSE
58 select HAVE_DEBUG_KMEMLEAK
59 select HAVE_DMA_API_DEBUG
61 select HAVE_DMA_CONTIGUOUS
62 select HAVE_DYNAMIC_FTRACE
63 select HAVE_EFFICIENT_UNALIGNED_ACCESS
64 select HAVE_FTRACE_MCOUNT_RECORD
65 select HAVE_FUNCTION_TRACER
66 select HAVE_FUNCTION_GRAPH_TRACER
67 select HAVE_GENERIC_DMA_COHERENT
68 select HAVE_HW_BREAKPOINT if PERF_EVENTS
70 select HAVE_PATA_PLATFORM
71 select HAVE_PERF_EVENTS
73 select HAVE_PERF_USER_STACK_DUMP
74 select HAVE_RCU_TABLE_FREE
75 select HAVE_SYSCALL_TRACEPOINTS
77 select IRQ_FORCED_THREADING
78 select MODULES_USE_ELF_RELA
81 select OF_EARLY_FLATTREE
82 select OF_RESERVED_MEM
83 select PERF_USE_VMALLOC
88 select SYSCTL_EXCEPTION_TRACE
89 select HAVE_CONTEXT_TRACKING
91 ARM 64-bit (AArch64) Linux support.
96 config ARCH_PHYS_ADDR_T_64BIT
105 config STACKTRACE_SUPPORT
108 config LOCKDEP_SUPPORT
111 config TRACE_IRQFLAGS_SUPPORT
114 config RWSEM_XCHGADD_ALGORITHM
121 config GENERIC_BUG_RELATIVE_POINTERS
123 depends on GENERIC_BUG
125 config GENERIC_HWEIGHT
131 config GENERIC_CALIBRATE_DELAY
137 config HAVE_GENERIC_RCU_GUP
140 config ARCH_DMA_ADDR_T_64BIT
143 config NEED_DMA_MAP_STATE
146 config NEED_SG_DMA_LENGTH
158 config KERNEL_MODE_NEON
161 config FIX_EARLYCON_MEM
164 config PGTABLE_LEVELS
166 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
167 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
168 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
169 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
171 source "init/Kconfig"
173 source "kernel/Kconfig.freezer"
175 menu "Platform selection"
180 This enables support for Samsung Exynos SoC family
183 bool "ARMv8 based Samsung Exynos7"
185 select COMMON_CLK_SAMSUNG
186 select HAVE_S3C2410_WATCHDOG if WATCHDOG
187 select HAVE_S3C_RTC if RTC_CLASS
189 select PINCTRL_EXYNOS
192 This enables support for Samsung Exynos7 SoC family
194 config ARCH_FSL_LS2085A
195 bool "Freescale LS2085A SOC"
197 This enables support for Freescale LS2085A SOC.
200 bool "Hisilicon SoC Family"
202 This enables support for Hisilicon ARMv8 SoC family
205 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
209 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
212 bool "Qualcomm Platforms"
215 This enables support for the ARMv8 based Qualcomm chipsets.
218 bool "AMD Seattle SoC Family"
220 This enables support for AMD Seattle SOC Family
223 bool "NVIDIA Tegra SoC Family"
224 select ARCH_HAS_RESET_CONTROLLER
225 select ARCH_REQUIRE_GPIOLIB
229 select GENERIC_CLOCKEVENTS
232 select RESET_CONTROLLER
234 This enables support for the NVIDIA Tegra SoC family.
236 config ARCH_TEGRA_132_SOC
237 bool "NVIDIA Tegra132 SoC"
238 depends on ARCH_TEGRA
239 select PINCTRL_TEGRA124
240 select USB_ULPI if USB_PHY
241 select USB_ULPI_VIEWPORT if USB_PHY
243 Enable support for NVIDIA Tegra132 SoC, based on the Denver
244 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
245 but contains an NVIDIA Denver CPU complex in place of
246 Tegra124's "4+1" Cortex-A15 CPU complex.
249 bool "Spreadtrum SoC platform"
251 Support for Spreadtrum ARM based SoCs
254 bool "Cavium Inc. Thunder SoC Family"
256 This enables support for Cavium's Thunder Family of SoCs.
259 bool "ARMv8 software model (Versatile Express)"
260 select ARCH_REQUIRE_GPIOLIB
261 select COMMON_CLK_VERSATILE
262 select POWER_RESET_VEXPRESS
263 select VEXPRESS_CONFIG
265 This enables support for the ARMv8 software model (Versatile
269 bool "AppliedMicro X-Gene SOC Family"
271 This enables support for AppliedMicro X-Gene SOC Family
274 bool "Xilinx ZynqMP Family"
276 This enables support for Xilinx ZynqMP Family
285 This feature enables support for PCI bus system. If you say Y
286 here, the kernel will include drivers and infrastructure code
287 to support PCI bus devices.
292 config PCI_DOMAINS_GENERIC
298 source "drivers/pci/Kconfig"
299 source "drivers/pci/pcie/Kconfig"
300 source "drivers/pci/hotplug/Kconfig"
304 menu "Kernel Features"
306 menu "ARM errata workarounds via the alternatives framework"
308 config ARM64_ERRATUM_826319
309 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
312 This option adds an alternative code sequence to work around ARM
313 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
314 AXI master interface and an L2 cache.
316 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
317 and is unable to accept a certain write via this interface, it will
318 not progress on read data presented on the read data channel and the
321 The workaround promotes data cache clean instructions to
322 data cache clean-and-invalidate.
323 Please note that this does not necessarily enable the workaround,
324 as it depends on the alternative framework, which will only patch
325 the kernel if an affected CPU is detected.
329 config ARM64_ERRATUM_827319
330 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
333 This option adds an alternative code sequence to work around ARM
334 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
335 master interface and an L2 cache.
337 Under certain conditions this erratum can cause a clean line eviction
338 to occur at the same time as another transaction to the same address
339 on the AMBA 5 CHI interface, which can cause data corruption if the
340 interconnect reorders the two transactions.
342 The workaround promotes data cache clean instructions to
343 data cache clean-and-invalidate.
344 Please note that this does not necessarily enable the workaround,
345 as it depends on the alternative framework, which will only patch
346 the kernel if an affected CPU is detected.
350 config ARM64_ERRATUM_824069
351 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
354 This option adds an alternative code sequence to work around ARM
355 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
356 to a coherent interconnect.
358 If a Cortex-A53 processor is executing a store or prefetch for
359 write instruction at the same time as a processor in another
360 cluster is executing a cache maintenance operation to the same
361 address, then this erratum might cause a clean cache line to be
362 incorrectly marked as dirty.
364 The workaround promotes data cache clean instructions to
365 data cache clean-and-invalidate.
366 Please note that this option does not necessarily enable the
367 workaround, as it depends on the alternative framework, which will
368 only patch the kernel if an affected CPU is detected.
372 config ARM64_ERRATUM_819472
373 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
376 This option adds an alternative code sequence to work around ARM
377 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
378 present when it is connected to a coherent interconnect.
380 If the processor is executing a load and store exclusive sequence at
381 the same time as a processor in another cluster is executing a cache
382 maintenance operation to the same address, then this erratum might
383 cause data corruption.
385 The workaround promotes data cache clean instructions to
386 data cache clean-and-invalidate.
387 Please note that this does not necessarily enable the workaround,
388 as it depends on the alternative framework, which will only patch
389 the kernel if an affected CPU is detected.
393 config ARM64_ERRATUM_832075
394 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
397 This option adds an alternative code sequence to work around ARM
398 erratum 832075 on Cortex-A57 parts up to r1p2.
400 Affected Cortex-A57 parts might deadlock when exclusive load/store
401 instructions to Write-Back memory are mixed with Device loads.
403 The workaround is to promote device loads to use Load-Acquire
405 Please note that this does not necessarily enable the workaround,
406 as it depends on the alternative framework, which will only patch
407 the kernel if an affected CPU is detected.
411 config ARM64_ERRATUM_845719
412 bool "Cortex-A53: 845719: a load might read incorrect data"
416 This option adds an alternative code sequence to work around ARM
417 erratum 845719 on Cortex-A53 parts up to r0p4.
419 When running a compat (AArch32) userspace on an affected Cortex-A53
420 part, a load at EL0 from a virtual address that matches the bottom 32
421 bits of the virtual address used by a recent load at (AArch64) EL1
422 might return incorrect data.
424 The workaround is to write the contextidr_el1 register on exception
425 return to a 32-bit task.
426 Please note that this does not necessarily enable the workaround,
427 as it depends on the alternative framework, which will only patch
428 the kernel if an affected CPU is detected.
437 default ARM64_4K_PAGES
439 Page size (translation granule) configuration.
441 config ARM64_4K_PAGES
444 This feature enables 4KB pages support.
446 config ARM64_64K_PAGES
449 This feature enables 64KB pages support (4KB by default)
450 allowing only two levels of page tables and faster TLB
451 look-up. AArch32 emulation is not available when this feature
457 prompt "Virtual address space size"
458 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
459 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
461 Allows choosing one of multiple possible virtual address
462 space sizes. The level of translation table is determined by
463 a combination of page size and virtual address space size.
465 config ARM64_VA_BITS_39
467 depends on ARM64_4K_PAGES
469 config ARM64_VA_BITS_42
471 depends on ARM64_64K_PAGES
473 config ARM64_VA_BITS_48
480 default 39 if ARM64_VA_BITS_39
481 default 42 if ARM64_VA_BITS_42
482 default 48 if ARM64_VA_BITS_48
484 config CPU_BIG_ENDIAN
485 bool "Build big-endian kernel"
487 Say Y if you plan on running a kernel in big-endian mode.
490 bool "Multi-core scheduler support"
492 Multi-core scheduler support improves the CPU scheduler's decision
493 making when dealing with multi-core CPU chips at a cost of slightly
494 increased overhead in some places. If unsure say N here.
497 bool "SMT scheduler support"
499 Improves the CPU scheduler's decision making when dealing with
500 MultiThreading at a cost of slightly increased overhead in some
501 places. If unsure say N here.
504 int "Maximum number of CPUs (2-4096)"
506 # These have to remain sorted largest to smallest
510 bool "Support for hot-pluggable CPUs"
512 Say Y here to experiment with turning CPUs off and on. CPUs
513 can be controlled through /sys/devices/system/cpu.
515 source kernel/Kconfig.preempt
521 config ARCH_HAS_HOLES_MEMORYMODEL
522 def_bool y if SPARSEMEM
524 config ARCH_SPARSEMEM_ENABLE
526 select SPARSEMEM_VMEMMAP_ENABLE
528 config ARCH_SPARSEMEM_DEFAULT
529 def_bool ARCH_SPARSEMEM_ENABLE
531 config ARCH_SELECT_MEMORY_MODEL
532 def_bool ARCH_SPARSEMEM_ENABLE
534 config HAVE_ARCH_PFN_VALID
535 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
537 config HW_PERF_EVENTS
538 bool "Enable hardware performance counter support for perf events"
539 depends on PERF_EVENTS
542 Enable hardware performance counter support for perf events. If
543 disabled, perf events will use software events only.
545 config SYS_SUPPORTS_HUGETLBFS
548 config ARCH_WANT_GENERAL_HUGETLB
551 config ARCH_WANT_HUGE_PMD_SHARE
552 def_bool y if !ARM64_64K_PAGES
554 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
557 config ARCH_HAS_CACHE_LINE_SIZE
563 bool "Enable seccomp to safely compute untrusted bytecode"
565 This kernel feature is useful for number crunching applications
566 that may need to compute untrusted bytecode during their
567 execution. By using pipes or other transports made available to
568 the process as file descriptors supporting the read/write
569 syscalls, it's possible to isolate those applications in
570 their own address space using seccomp. Once seccomp is
571 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
572 and the task is only allowed to execute a few safe syscalls
573 defined by each seccomp mode.
580 bool "Xen guest support on ARM64"
581 depends on ARM64 && OF
584 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
586 config FORCE_MAX_ZONEORDER
588 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
591 menuconfig ARMV8_DEPRECATED
592 bool "Emulate deprecated/obsolete ARMv8 instructions"
595 Legacy software support may require certain instructions
596 that have been deprecated or obsoleted in the architecture.
598 Enable this config to enable selective emulation of these
606 bool "Emulate SWP/SWPB instructions"
608 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
609 they are always undefined. Say Y here to enable software
610 emulation of these instructions for userspace using LDXR/STXR.
612 In some older versions of glibc [<=2.8] SWP is used during futex
613 trylock() operations with the assumption that the code will not
614 be preempted. This invalid assumption may be more likely to fail
615 with SWP emulation enabled, leading to deadlock of the user
618 NOTE: when accessing uncached shared regions, LDXR/STXR rely
619 on an external transaction monitoring block called a global
620 monitor to maintain update atomicity. If your system does not
621 implement a global monitor, this option can cause programs that
622 perform SWP operations to uncached memory to deadlock.
626 config CP15_BARRIER_EMULATION
627 bool "Emulate CP15 Barrier instructions"
629 The CP15 barrier instructions - CP15ISB, CP15DSB, and
630 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
631 strongly recommended to use the ISB, DSB, and DMB
632 instructions instead.
634 Say Y here to enable software emulation of these
635 instructions for AArch32 userspace code. When this option is
636 enabled, CP15 barrier usage is traced which can help
637 identify software that needs updating.
641 config SETEND_EMULATION
642 bool "Emulate SETEND instruction"
644 The SETEND instruction alters the data-endianness of the
645 AArch32 EL0, and is deprecated in ARMv8.
647 Say Y here to enable software emulation of the instruction
648 for AArch32 userspace code.
650 Note: All the cpus on the system must have mixed endian support at EL0
651 for this feature to be enabled. If a new CPU - which doesn't support mixed
652 endian - is hotplugged in after this feature has been enabled, there could
653 be unexpected results in the applications.
658 menu "ARMv8.1 architectural features"
660 config ARM64_HW_AFDBM
661 bool "Support for hardware updates of the Access and Dirty page flags"
664 The ARMv8.1 architecture extensions introduce support for
665 hardware updates of the access and dirty information in page
666 table entries. When enabled in TCR_EL1 (HA and HD bits) on
667 capable processors, accesses to pages with PTE_AF cleared will
668 set this bit instead of raising an access flag fault.
669 Similarly, writes to read-only pages with the DBM bit set will
670 clear the read-only bit (AP[2]) instead of raising a
673 Kernels built with this configuration option enabled continue
674 to work on pre-ARMv8.1 hardware and the performance impact is
675 minimal. If unsure, say Y.
678 bool "Enable support for Privileged Access Never (PAN)"
681 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
682 prevents the kernel or hypervisor from accessing user-space (EL0)
685 Choosing this option will cause any unprotected (not using
686 copy_to_user et al) memory access to fail with a permission fault.
688 The feature is detected at runtime, and will remain as a 'nop'
689 instruction if the cpu does not implement the feature.
691 config ARM64_LSE_ATOMICS
692 bool "Atomic instructions"
694 As part of the Large System Extensions, ARMv8.1 introduces new
695 atomic instructions that are designed specifically to scale in
698 Say Y here to make use of these instructions for the in-kernel
699 atomic routines. This incurs a small overhead on CPUs that do
700 not support these instructions and requires the kernel to be
701 built with binutils >= 2.25.
710 string "Default kernel command string"
713 Provide a set of default command-line options at build time by
714 entering them here. As a minimum, you should specify the the
715 root device (e.g. root=/dev/nfs).
718 bool "Always use the default kernel command string"
720 Always use the default kernel command string, even if the boot
721 loader passes other arguments to the kernel.
722 This is useful if you cannot or don't want to change the
723 command-line options your boot loader passes to the kernel.
729 bool "UEFI runtime support"
730 depends on OF && !CPU_BIG_ENDIAN
733 select EFI_PARAMS_FROM_FDT
734 select EFI_RUNTIME_WRAPPERS
739 This option provides support for runtime services provided
740 by UEFI firmware (such as non-volatile variables, realtime
741 clock, and platform reset). A UEFI stub is also provided to
742 allow the kernel to be booted as an EFI application. This
743 is only useful on systems that have UEFI firmware.
746 bool "Enable support for SMBIOS (DMI) tables"
750 This enables SMBIOS/DMI feature for systems.
752 This option is only useful on systems that have UEFI firmware.
753 However, even with this option, the resultant kernel should
754 continue to boot on existing non-UEFI platforms.
758 menu "Userspace binary formats"
760 source "fs/Kconfig.binfmt"
763 bool "Kernel support for 32-bit EL0"
764 depends on !ARM64_64K_PAGES || EXPERT
765 select COMPAT_BINFMT_ELF
767 select OLD_SIGSUSPEND3
768 select COMPAT_OLD_SIGACTION
770 This option enables support for a 32-bit EL0 running under a 64-bit
771 kernel at EL1. AArch32-specific components such as system calls,
772 the user helper functions, VFP support and the ptrace interface are
773 handled appropriately by the kernel.
775 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
776 will only be able to execute AArch32 binaries that were compiled with
777 64k aligned segments.
779 If you want to execute 32-bit userspace applications, say Y.
781 config SYSVIPC_COMPAT
783 depends on COMPAT && SYSVIPC
787 menu "Power management options"
789 source "kernel/power/Kconfig"
791 config ARCH_SUSPEND_POSSIBLE
796 menu "CPU Power Management"
798 source "drivers/cpuidle/Kconfig"
800 source "drivers/cpufreq/Kconfig"
806 source "drivers/Kconfig"
808 source "drivers/firmware/Kconfig"
810 source "drivers/acpi/Kconfig"
814 source "arch/arm64/kvm/Kconfig"
816 source "arch/arm64/Kconfig.debug"
818 source "security/Kconfig"
820 source "crypto/Kconfig"
822 source "arch/arm64/crypto/Kconfig"