3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_GCOV_PROFILE_ALL
6 select ARCH_HAS_SG_CHAIN
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_WANT_OPTIONAL_GPIOLIB
11 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
12 select ARCH_WANT_FRAME_POINTERS
16 select AUDIT_ARCH_COMPAT_GENERIC
17 select ARM_GIC_V2M if PCI_MSI
19 select ARM_GIC_V3_ITS if PCI_MSI
20 select BUILDTIME_EXTABLE_SORT
21 select CLONE_BACKWARDS
23 select CPU_PM if (SUSPEND || CPU_IDLE)
24 select DCACHE_WORD_ACCESS
25 select GENERIC_ALLOCATOR
26 select GENERIC_CLOCKEVENTS
27 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
28 select GENERIC_CPU_AUTOPROBE
29 select GENERIC_EARLY_IOREMAP
30 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
32 select GENERIC_PCI_IOMAP
33 select GENERIC_SCHED_CLOCK
34 select GENERIC_SMP_IDLE_THREAD
35 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
37 select GENERIC_TIME_VSYSCALL
38 select HANDLE_DOMAIN_IRQ
39 select HARDIRQS_SW_RESEND
40 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
41 select HAVE_ARCH_AUDITSYSCALL
42 select HAVE_ARCH_BITREVERSE
43 select HAVE_ARCH_JUMP_LABEL
45 select HAVE_ARCH_SECCOMP_FILTER
46 select HAVE_ARCH_TRACEHOOK
48 select HAVE_C_RECORDMCOUNT
49 select HAVE_CC_STACKPROTECTOR
50 select HAVE_CMPXCHG_DOUBLE
51 select HAVE_DEBUG_BUGVERBOSE
52 select HAVE_DEBUG_KMEMLEAK
53 select HAVE_DMA_API_DEBUG
55 select HAVE_DMA_CONTIGUOUS
56 select HAVE_DYNAMIC_FTRACE
57 select HAVE_EFFICIENT_UNALIGNED_ACCESS
58 select HAVE_FTRACE_MCOUNT_RECORD
59 select HAVE_FUNCTION_TRACER
60 select HAVE_FUNCTION_GRAPH_TRACER
61 select HAVE_GENERIC_DMA_COHERENT
62 select HAVE_HW_BREAKPOINT if PERF_EVENTS
64 select HAVE_PATA_PLATFORM
65 select HAVE_PERF_EVENTS
67 select HAVE_PERF_USER_STACK_DUMP
68 select HAVE_RCU_TABLE_FREE
69 select HAVE_SYSCALL_TRACEPOINTS
71 select MODULES_USE_ELF_RELA
74 select OF_EARLY_FLATTREE
75 select OF_RESERVED_MEM
76 select PERF_USE_VMALLOC
81 select SYSCTL_EXCEPTION_TRACE
82 select HAVE_CONTEXT_TRACKING
84 ARM 64-bit (AArch64) Linux support.
89 config ARCH_PHYS_ADDR_T_64BIT
98 config STACKTRACE_SUPPORT
101 config LOCKDEP_SUPPORT
104 config TRACE_IRQFLAGS_SUPPORT
107 config RWSEM_XCHGADD_ALGORITHM
110 config GENERIC_HWEIGHT
116 config GENERIC_CALIBRATE_DELAY
122 config HAVE_GENERIC_RCU_GUP
125 config ARCH_DMA_ADDR_T_64BIT
128 config NEED_DMA_MAP_STATE
131 config NEED_SG_DMA_LENGTH
140 config KERNEL_MODE_NEON
143 config FIX_EARLYCON_MEM
146 source "init/Kconfig"
148 source "kernel/Kconfig.freezer"
150 menu "Platform selection"
155 This enables support for Samsung Exynos SoC family
158 bool "ARMv8 based Samsung Exynos7"
160 select COMMON_CLK_SAMSUNG
161 select HAVE_S3C2410_WATCHDOG if WATCHDOG
162 select HAVE_S3C_RTC if RTC_CLASS
164 select PINCTRL_EXYNOS
167 This enables support for Samsung Exynos7 SoC family
169 config ARCH_FSL_LS2085A
170 bool "Freescale LS2085A SOC"
172 This enables support for Freescale LS2085A SOC.
175 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
178 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
181 bool "Qualcomm Platforms"
184 This enables support for the ARMv8 based Qualcomm chipsets.
187 bool "AMD Seattle SoC Family"
189 This enables support for AMD Seattle SOC Family
192 bool "NVIDIA Tegra SoC Family"
193 select ARCH_HAS_RESET_CONTROLLER
194 select ARCH_REQUIRE_GPIOLIB
198 select GENERIC_CLOCKEVENTS
201 select RESET_CONTROLLER
203 This enables support for the NVIDIA Tegra SoC family.
205 config ARCH_TEGRA_132_SOC
206 bool "NVIDIA Tegra132 SoC"
207 depends on ARCH_TEGRA
208 select PINCTRL_TEGRA124
209 select USB_ULPI if USB_PHY
210 select USB_ULPI_VIEWPORT if USB_PHY
212 Enable support for NVIDIA Tegra132 SoC, based on the Denver
213 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
214 but contains an NVIDIA Denver CPU complex in place of
215 Tegra124's "4+1" Cortex-A15 CPU complex.
218 bool "Spreadtrum SoC platform"
220 Support for Spreadtrum ARM based SoCs
223 bool "Cavium Inc. Thunder SoC Family"
225 This enables support for Cavium's Thunder Family of SoCs.
228 bool "ARMv8 software model (Versatile Express)"
229 select ARCH_REQUIRE_GPIOLIB
230 select COMMON_CLK_VERSATILE
231 select POWER_RESET_VEXPRESS
232 select VEXPRESS_CONFIG
234 This enables support for the ARMv8 software model (Versatile
238 bool "AppliedMicro X-Gene SOC Family"
240 This enables support for AppliedMicro X-Gene SOC Family
243 bool "Xilinx ZynqMP Family"
245 This enables support for Xilinx ZynqMP Family
254 This feature enables support for PCI bus system. If you say Y
255 here, the kernel will include drivers and infrastructure code
256 to support PCI bus devices.
261 config PCI_DOMAINS_GENERIC
267 source "drivers/pci/Kconfig"
268 source "drivers/pci/pcie/Kconfig"
269 source "drivers/pci/hotplug/Kconfig"
273 menu "Kernel Features"
275 menu "ARM errata workarounds via the alternatives framework"
277 config ARM64_ERRATUM_826319
278 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
281 This option adds an alternative code sequence to work around ARM
282 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
283 AXI master interface and an L2 cache.
285 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
286 and is unable to accept a certain write via this interface, it will
287 not progress on read data presented on the read data channel and the
290 The workaround promotes data cache clean instructions to
291 data cache clean-and-invalidate.
292 Please note that this does not necessarily enable the workaround,
293 as it depends on the alternative framework, which will only patch
294 the kernel if an affected CPU is detected.
298 config ARM64_ERRATUM_827319
299 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
302 This option adds an alternative code sequence to work around ARM
303 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
304 master interface and an L2 cache.
306 Under certain conditions this erratum can cause a clean line eviction
307 to occur at the same time as another transaction to the same address
308 on the AMBA 5 CHI interface, which can cause data corruption if the
309 interconnect reorders the two transactions.
311 The workaround promotes data cache clean instructions to
312 data cache clean-and-invalidate.
313 Please note that this does not necessarily enable the workaround,
314 as it depends on the alternative framework, which will only patch
315 the kernel if an affected CPU is detected.
319 config ARM64_ERRATUM_824069
320 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
323 This option adds an alternative code sequence to work around ARM
324 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
325 to a coherent interconnect.
327 If a Cortex-A53 processor is executing a store or prefetch for
328 write instruction at the same time as a processor in another
329 cluster is executing a cache maintenance operation to the same
330 address, then this erratum might cause a clean cache line to be
331 incorrectly marked as dirty.
333 The workaround promotes data cache clean instructions to
334 data cache clean-and-invalidate.
335 Please note that this option does not necessarily enable the
336 workaround, as it depends on the alternative framework, which will
337 only patch the kernel if an affected CPU is detected.
341 config ARM64_ERRATUM_819472
342 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
345 This option adds an alternative code sequence to work around ARM
346 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
347 present when it is connected to a coherent interconnect.
349 If the processor is executing a load and store exclusive sequence at
350 the same time as a processor in another cluster is executing a cache
351 maintenance operation to the same address, then this erratum might
352 cause data corruption.
354 The workaround promotes data cache clean instructions to
355 data cache clean-and-invalidate.
356 Please note that this does not necessarily enable the workaround,
357 as it depends on the alternative framework, which will only patch
358 the kernel if an affected CPU is detected.
362 config ARM64_ERRATUM_832075
363 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
366 This option adds an alternative code sequence to work around ARM
367 erratum 832075 on Cortex-A57 parts up to r1p2.
369 Affected Cortex-A57 parts might deadlock when exclusive load/store
370 instructions to Write-Back memory are mixed with Device loads.
372 The workaround is to promote device loads to use Load-Acquire
374 Please note that this does not necessarily enable the workaround,
375 as it depends on the alternative framework, which will only patch
376 the kernel if an affected CPU is detected.
385 default ARM64_4K_PAGES
387 Page size (translation granule) configuration.
389 config ARM64_4K_PAGES
392 This feature enables 4KB pages support.
394 config ARM64_64K_PAGES
397 This feature enables 64KB pages support (4KB by default)
398 allowing only two levels of page tables and faster TLB
399 look-up. AArch32 emulation is not available when this feature
405 prompt "Virtual address space size"
406 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
407 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
409 Allows choosing one of multiple possible virtual address
410 space sizes. The level of translation table is determined by
411 a combination of page size and virtual address space size.
413 config ARM64_VA_BITS_39
415 depends on ARM64_4K_PAGES
417 config ARM64_VA_BITS_42
419 depends on ARM64_64K_PAGES
421 config ARM64_VA_BITS_48
428 default 39 if ARM64_VA_BITS_39
429 default 42 if ARM64_VA_BITS_42
430 default 48 if ARM64_VA_BITS_48
432 config ARM64_PGTABLE_LEVELS
434 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
435 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
436 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
437 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
439 config CPU_BIG_ENDIAN
440 bool "Build big-endian kernel"
442 Say Y if you plan on running a kernel in big-endian mode.
445 bool "Symmetric Multi-Processing"
447 This enables support for systems with more than one CPU. If
448 you say N here, the kernel will run on single and
449 multiprocessor machines, but will use only one CPU of a
450 multiprocessor machine. If you say Y here, the kernel will run
451 on many, but not all, single processor machines. On a single
452 processor machine, the kernel will run faster if you say N
455 If you don't know what to do here, say N.
458 bool "Multi-core scheduler support"
461 Multi-core scheduler support improves the CPU scheduler's decision
462 making when dealing with multi-core CPU chips at a cost of slightly
463 increased overhead in some places. If unsure say N here.
466 bool "SMT scheduler support"
469 Improves the CPU scheduler's decision making when dealing with
470 MultiThreading at a cost of slightly increased overhead in some
471 places. If unsure say N here.
474 int "Maximum number of CPUs (2-64)"
477 # These have to remain sorted largest to smallest
481 bool "Support for hot-pluggable CPUs"
484 Say Y here to experiment with turning CPUs off and on. CPUs
485 can be controlled through /sys/devices/system/cpu.
487 source kernel/Kconfig.preempt
493 config ARCH_HAS_HOLES_MEMORYMODEL
494 def_bool y if SPARSEMEM
496 config ARCH_SPARSEMEM_ENABLE
498 select SPARSEMEM_VMEMMAP_ENABLE
500 config ARCH_SPARSEMEM_DEFAULT
501 def_bool ARCH_SPARSEMEM_ENABLE
503 config ARCH_SELECT_MEMORY_MODEL
504 def_bool ARCH_SPARSEMEM_ENABLE
506 config HAVE_ARCH_PFN_VALID
507 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
509 config HW_PERF_EVENTS
510 bool "Enable hardware performance counter support for perf events"
511 depends on PERF_EVENTS
514 Enable hardware performance counter support for perf events. If
515 disabled, perf events will use software events only.
517 config SYS_SUPPORTS_HUGETLBFS
520 config ARCH_WANT_GENERAL_HUGETLB
523 config ARCH_WANT_HUGE_PMD_SHARE
524 def_bool y if !ARM64_64K_PAGES
526 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
529 config ARCH_HAS_CACHE_LINE_SIZE
535 bool "Enable seccomp to safely compute untrusted bytecode"
537 This kernel feature is useful for number crunching applications
538 that may need to compute untrusted bytecode during their
539 execution. By using pipes or other transports made available to
540 the process as file descriptors supporting the read/write
541 syscalls, it's possible to isolate those applications in
542 their own address space using seccomp. Once seccomp is
543 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
544 and the task is only allowed to execute a few safe syscalls
545 defined by each seccomp mode.
552 bool "Xen guest support on ARM64"
553 depends on ARM64 && OF
556 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
558 config FORCE_MAX_ZONEORDER
560 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
563 menuconfig ARMV8_DEPRECATED
564 bool "Emulate deprecated/obsolete ARMv8 instructions"
567 Legacy software support may require certain instructions
568 that have been deprecated or obsoleted in the architecture.
570 Enable this config to enable selective emulation of these
578 bool "Emulate SWP/SWPB instructions"
580 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
581 they are always undefined. Say Y here to enable software
582 emulation of these instructions for userspace using LDXR/STXR.
584 In some older versions of glibc [<=2.8] SWP is used during futex
585 trylock() operations with the assumption that the code will not
586 be preempted. This invalid assumption may be more likely to fail
587 with SWP emulation enabled, leading to deadlock of the user
590 NOTE: when accessing uncached shared regions, LDXR/STXR rely
591 on an external transaction monitoring block called a global
592 monitor to maintain update atomicity. If your system does not
593 implement a global monitor, this option can cause programs that
594 perform SWP operations to uncached memory to deadlock.
598 config CP15_BARRIER_EMULATION
599 bool "Emulate CP15 Barrier instructions"
601 The CP15 barrier instructions - CP15ISB, CP15DSB, and
602 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
603 strongly recommended to use the ISB, DSB, and DMB
604 instructions instead.
606 Say Y here to enable software emulation of these
607 instructions for AArch32 userspace code. When this option is
608 enabled, CP15 barrier usage is traced which can help
609 identify software that needs updating.
613 config SETEND_EMULATION
614 bool "Emulate SETEND instruction"
616 The SETEND instruction alters the data-endianness of the
617 AArch32 EL0, and is deprecated in ARMv8.
619 Say Y here to enable software emulation of the instruction
620 for AArch32 userspace code.
622 Note: All the cpus on the system must have mixed endian support at EL0
623 for this feature to be enabled. If a new CPU - which doesn't support mixed
624 endian - is hotplugged in after this feature has been enabled, there could
625 be unexpected results in the applications.
635 string "Default kernel command string"
638 Provide a set of default command-line options at build time by
639 entering them here. As a minimum, you should specify the the
640 root device (e.g. root=/dev/nfs).
643 bool "Always use the default kernel command string"
645 Always use the default kernel command string, even if the boot
646 loader passes other arguments to the kernel.
647 This is useful if you cannot or don't want to change the
648 command-line options your boot loader passes to the kernel.
654 bool "UEFI runtime support"
655 depends on OF && !CPU_BIG_ENDIAN
658 select EFI_PARAMS_FROM_FDT
659 select EFI_RUNTIME_WRAPPERS
664 This option provides support for runtime services provided
665 by UEFI firmware (such as non-volatile variables, realtime
666 clock, and platform reset). A UEFI stub is also provided to
667 allow the kernel to be booted as an EFI application. This
668 is only useful on systems that have UEFI firmware.
671 bool "Enable support for SMBIOS (DMI) tables"
675 This enables SMBIOS/DMI feature for systems.
677 This option is only useful on systems that have UEFI firmware.
678 However, even with this option, the resultant kernel should
679 continue to boot on existing non-UEFI platforms.
683 menu "Userspace binary formats"
685 source "fs/Kconfig.binfmt"
688 bool "Kernel support for 32-bit EL0"
689 depends on !ARM64_64K_PAGES
690 select COMPAT_BINFMT_ELF
692 select OLD_SIGSUSPEND3
693 select COMPAT_OLD_SIGACTION
695 This option enables support for a 32-bit EL0 running under a 64-bit
696 kernel at EL1. AArch32-specific components such as system calls,
697 the user helper functions, VFP support and the ptrace interface are
698 handled appropriately by the kernel.
700 If you want to execute 32-bit userspace applications, say Y.
702 config SYSVIPC_COMPAT
704 depends on COMPAT && SYSVIPC
708 menu "Power management options"
710 source "kernel/power/Kconfig"
712 config ARCH_SUSPEND_POSSIBLE
717 menu "CPU Power Management"
719 source "drivers/cpuidle/Kconfig"
721 source "drivers/cpufreq/Kconfig"
727 source "drivers/Kconfig"
729 source "drivers/firmware/Kconfig"
733 source "arch/arm64/kvm/Kconfig"
735 source "arch/arm64/Kconfig.debug"
737 source "security/Kconfig"
739 source "crypto/Kconfig"
741 source "arch/arm64/crypto/Kconfig"