3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ARCH_CLOCKSOURCE_DATA
11 select ARCH_HAS_DEBUG_VIRTUAL
12 select ARCH_HAS_DEVMEM_IS_ALLOWED
13 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
14 select ARCH_HAS_ELF_RANDOMIZE
15 select ARCH_HAS_GCOV_PROFILE_ALL
16 select ARCH_HAS_GIGANTIC_PAGE
18 select ARCH_HAS_SET_MEMORY
19 select ARCH_HAS_SG_CHAIN
20 select ARCH_HAS_STRICT_KERNEL_RWX
21 select ARCH_HAS_STRICT_MODULE_RWX
22 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
23 select ARCH_HAVE_NMI_SAFE_CMPXCHG if ACPI_APEI_SEA
24 select ARCH_USE_CMPXCHG_LOCKREF
25 select ARCH_SUPPORTS_MEMORY_FAILURE
26 select ARCH_SUPPORTS_ATOMIC_RMW
27 select ARCH_SUPPORTS_NUMA_BALANCING
28 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
29 select ARCH_WANT_FRAME_POINTERS
30 select ARCH_HAS_UBSAN_SANITIZE_ALL
34 select AUDIT_ARCH_COMPAT_GENERIC
35 select ARM_GIC_V2M if PCI
37 select ARM_GIC_V3_ITS if PCI
39 select BUILDTIME_EXTABLE_SORT
40 select CLONE_BACKWARDS
42 select CPU_PM if (SUSPEND || CPU_IDLE)
43 select DCACHE_WORD_ACCESS
46 select GENERIC_ALLOCATOR
47 select GENERIC_CLOCKEVENTS
48 select GENERIC_CLOCKEVENTS_BROADCAST
49 select GENERIC_CPU_AUTOPROBE
50 select GENERIC_EARLY_IOREMAP
51 select GENERIC_IDLE_POLL_SETUP
52 select GENERIC_IRQ_PROBE
53 select GENERIC_IRQ_SHOW
54 select GENERIC_IRQ_SHOW_LEVEL
55 select GENERIC_PCI_IOMAP
56 select GENERIC_SCHED_CLOCK
57 select GENERIC_SMP_IDLE_THREAD
58 select GENERIC_STRNCPY_FROM_USER
59 select GENERIC_STRNLEN_USER
60 select GENERIC_TIME_VSYSCALL
61 select HANDLE_DOMAIN_IRQ
62 select HARDIRQS_SW_RESEND
63 select HAVE_ACPI_APEI if (ACPI && EFI)
64 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
65 select HAVE_ARCH_AUDITSYSCALL
66 select HAVE_ARCH_BITREVERSE
67 select HAVE_ARCH_HUGE_VMAP
68 select HAVE_ARCH_JUMP_LABEL
69 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
71 select HAVE_ARCH_MMAP_RND_BITS
72 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
73 select HAVE_ARCH_SECCOMP_FILTER
74 select HAVE_ARCH_TRACEHOOK
75 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
78 select HAVE_C_RECORDMCOUNT
79 select HAVE_CC_STACKPROTECTOR
80 select HAVE_CMPXCHG_DOUBLE
81 select HAVE_CMPXCHG_LOCAL
82 select HAVE_CONTEXT_TRACKING
83 select HAVE_DEBUG_BUGVERBOSE
84 select HAVE_DEBUG_KMEMLEAK
85 select HAVE_DMA_API_DEBUG
86 select HAVE_DMA_CONTIGUOUS
87 select HAVE_DYNAMIC_FTRACE
88 select HAVE_EFFICIENT_UNALIGNED_ACCESS
89 select HAVE_FTRACE_MCOUNT_RECORD
90 select HAVE_FUNCTION_TRACER
91 select HAVE_FUNCTION_GRAPH_TRACER
92 select HAVE_GCC_PLUGINS
93 select HAVE_GENERIC_DMA_COHERENT
94 select HAVE_HW_BREAKPOINT if PERF_EVENTS
95 select HAVE_IRQ_TIME_ACCOUNTING
97 select HAVE_MEMBLOCK_NODE_MAP if NUMA
98 select HAVE_NMI if ACPI_APEI_SEA
99 select HAVE_PATA_PLATFORM
100 select HAVE_PERF_EVENTS
101 select HAVE_PERF_REGS
102 select HAVE_PERF_USER_STACK_DUMP
103 select HAVE_REGS_AND_STACK_ACCESS_API
104 select HAVE_RCU_TABLE_FREE
105 select HAVE_SYSCALL_TRACEPOINTS
107 select HAVE_KRETPROBES
108 select IOMMU_DMA if IOMMU_SUPPORT
110 select IRQ_FORCED_THREADING
111 select MODULES_USE_ELF_RELA
114 select OF_EARLY_FLATTREE
115 select OF_RESERVED_MEM
116 select PCI_ECAM if ACPI
120 select SYSCTL_EXCEPTION_TRACE
121 select THREAD_INFO_IN_TASK
123 ARM 64-bit (AArch64) Linux support.
128 config ARCH_PHYS_ADDR_T_64BIT
134 config ARM64_PAGE_SHIFT
136 default 16 if ARM64_64K_PAGES
137 default 14 if ARM64_16K_PAGES
140 config ARM64_CONT_SHIFT
142 default 5 if ARM64_64K_PAGES
143 default 7 if ARM64_16K_PAGES
146 config ARCH_MMAP_RND_BITS_MIN
147 default 14 if ARM64_64K_PAGES
148 default 16 if ARM64_16K_PAGES
151 # max bits determined by the following formula:
152 # VA_BITS - PAGE_SHIFT - 3
153 config ARCH_MMAP_RND_BITS_MAX
154 default 19 if ARM64_VA_BITS=36
155 default 24 if ARM64_VA_BITS=39
156 default 27 if ARM64_VA_BITS=42
157 default 30 if ARM64_VA_BITS=47
158 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
159 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
160 default 33 if ARM64_VA_BITS=48
161 default 14 if ARM64_64K_PAGES
162 default 16 if ARM64_16K_PAGES
165 config ARCH_MMAP_RND_COMPAT_BITS_MIN
166 default 7 if ARM64_64K_PAGES
167 default 9 if ARM64_16K_PAGES
170 config ARCH_MMAP_RND_COMPAT_BITS_MAX
176 config STACKTRACE_SUPPORT
179 config ILLEGAL_POINTER_VALUE
181 default 0xdead000000000000
183 config LOCKDEP_SUPPORT
186 config TRACE_IRQFLAGS_SUPPORT
189 config RWSEM_XCHGADD_ALGORITHM
196 config GENERIC_BUG_RELATIVE_POINTERS
198 depends on GENERIC_BUG
200 config GENERIC_HWEIGHT
206 config GENERIC_CALIBRATE_DELAY
212 config HAVE_GENERIC_RCU_GUP
215 config ARCH_DMA_ADDR_T_64BIT
218 config NEED_DMA_MAP_STATE
221 config NEED_SG_DMA_LENGTH
233 config KERNEL_MODE_NEON
236 config FIX_EARLYCON_MEM
239 config PGTABLE_LEVELS
241 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
242 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
243 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
244 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
245 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
246 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
248 config ARCH_SUPPORTS_UPROBES
251 config ARCH_PROC_KCORE_TEXT
254 source "init/Kconfig"
256 source "kernel/Kconfig.freezer"
258 source "arch/arm64/Kconfig.platforms"
265 This feature enables support for PCI bus system. If you say Y
266 here, the kernel will include drivers and infrastructure code
267 to support PCI bus devices.
272 config PCI_DOMAINS_GENERIC
278 source "drivers/pci/Kconfig"
282 menu "Kernel Features"
284 menu "ARM errata workarounds via the alternatives framework"
286 config ARM64_ERRATUM_826319
287 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
290 This option adds an alternative code sequence to work around ARM
291 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
292 AXI master interface and an L2 cache.
294 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
295 and is unable to accept a certain write via this interface, it will
296 not progress on read data presented on the read data channel and the
299 The workaround promotes data cache clean instructions to
300 data cache clean-and-invalidate.
301 Please note that this does not necessarily enable the workaround,
302 as it depends on the alternative framework, which will only patch
303 the kernel if an affected CPU is detected.
307 config ARM64_ERRATUM_827319
308 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
311 This option adds an alternative code sequence to work around ARM
312 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
313 master interface and an L2 cache.
315 Under certain conditions this erratum can cause a clean line eviction
316 to occur at the same time as another transaction to the same address
317 on the AMBA 5 CHI interface, which can cause data corruption if the
318 interconnect reorders the two transactions.
320 The workaround promotes data cache clean instructions to
321 data cache clean-and-invalidate.
322 Please note that this does not necessarily enable the workaround,
323 as it depends on the alternative framework, which will only patch
324 the kernel if an affected CPU is detected.
328 config ARM64_ERRATUM_824069
329 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
332 This option adds an alternative code sequence to work around ARM
333 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
334 to a coherent interconnect.
336 If a Cortex-A53 processor is executing a store or prefetch for
337 write instruction at the same time as a processor in another
338 cluster is executing a cache maintenance operation to the same
339 address, then this erratum might cause a clean cache line to be
340 incorrectly marked as dirty.
342 The workaround promotes data cache clean instructions to
343 data cache clean-and-invalidate.
344 Please note that this option does not necessarily enable the
345 workaround, as it depends on the alternative framework, which will
346 only patch the kernel if an affected CPU is detected.
350 config ARM64_ERRATUM_819472
351 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
354 This option adds an alternative code sequence to work around ARM
355 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
356 present when it is connected to a coherent interconnect.
358 If the processor is executing a load and store exclusive sequence at
359 the same time as a processor in another cluster is executing a cache
360 maintenance operation to the same address, then this erratum might
361 cause data corruption.
363 The workaround promotes data cache clean instructions to
364 data cache clean-and-invalidate.
365 Please note that this does not necessarily enable the workaround,
366 as it depends on the alternative framework, which will only patch
367 the kernel if an affected CPU is detected.
371 config ARM64_ERRATUM_832075
372 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
375 This option adds an alternative code sequence to work around ARM
376 erratum 832075 on Cortex-A57 parts up to r1p2.
378 Affected Cortex-A57 parts might deadlock when exclusive load/store
379 instructions to Write-Back memory are mixed with Device loads.
381 The workaround is to promote device loads to use Load-Acquire
383 Please note that this does not necessarily enable the workaround,
384 as it depends on the alternative framework, which will only patch
385 the kernel if an affected CPU is detected.
389 config ARM64_ERRATUM_834220
390 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
394 This option adds an alternative code sequence to work around ARM
395 erratum 834220 on Cortex-A57 parts up to r1p2.
397 Affected Cortex-A57 parts might report a Stage 2 translation
398 fault as the result of a Stage 1 fault for load crossing a
399 page boundary when there is a permission or device memory
400 alignment fault at Stage 1 and a translation fault at Stage 2.
402 The workaround is to verify that the Stage 1 translation
403 doesn't generate a fault before handling the Stage 2 fault.
404 Please note that this does not necessarily enable the workaround,
405 as it depends on the alternative framework, which will only patch
406 the kernel if an affected CPU is detected.
410 config ARM64_ERRATUM_845719
411 bool "Cortex-A53: 845719: a load might read incorrect data"
415 This option adds an alternative code sequence to work around ARM
416 erratum 845719 on Cortex-A53 parts up to r0p4.
418 When running a compat (AArch32) userspace on an affected Cortex-A53
419 part, a load at EL0 from a virtual address that matches the bottom 32
420 bits of the virtual address used by a recent load at (AArch64) EL1
421 might return incorrect data.
423 The workaround is to write the contextidr_el1 register on exception
424 return to a 32-bit task.
425 Please note that this does not necessarily enable the workaround,
426 as it depends on the alternative framework, which will only patch
427 the kernel if an affected CPU is detected.
431 config ARM64_ERRATUM_843419
432 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
434 select ARM64_MODULE_CMODEL_LARGE if MODULES
436 This option links the kernel with '--fix-cortex-a53-843419' and
437 builds modules using the large memory model in order to avoid the use
438 of the ADRP instruction, which can cause a subsequent memory access
439 to use an incorrect address on Cortex-A53 parts up to r0p4.
443 config CAVIUM_ERRATUM_22375
444 bool "Cavium erratum 22375, 24313"
447 Enable workaround for erratum 22375, 24313.
449 This implements two gicv3-its errata workarounds for ThunderX. Both
450 with small impact affecting only ITS table allocation.
452 erratum 22375: only alloc 8MB table size
453 erratum 24313: ignore memory access type
455 The fixes are in ITS initialization and basically ignore memory access
456 type and table size provided by the TYPER and BASER registers.
460 config CAVIUM_ERRATUM_23144
461 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
465 ITS SYNC command hang for cross node io and collections/cpu mapping.
469 config CAVIUM_ERRATUM_23154
470 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
473 The gicv3 of ThunderX requires a modified version for
474 reading the IAR status to ensure data synchronization
475 (access to icc_iar1_el1 is not sync'ed before and after).
479 config CAVIUM_ERRATUM_27456
480 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
483 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
484 instructions may cause the icache to become corrupted if it
485 contains data for a non-current ASID. The fix is to
486 invalidate the icache when changing the mm context.
490 config QCOM_FALKOR_ERRATUM_1003
491 bool "Falkor E1003: Incorrect translation due to ASID change"
493 select ARM64_PAN if ARM64_SW_TTBR0_PAN
495 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
496 and BADDR are changed together in TTBRx_EL1. The workaround for this
497 issue is to use a reserved ASID in cpu_do_switch_mm() before
498 switching to the new ASID. Saying Y here selects ARM64_PAN if
499 ARM64_SW_TTBR0_PAN is selected. This is done because implementing and
500 maintaining the E1003 workaround in the software PAN emulation code
501 would be an unnecessary complication. The affected Falkor v1 CPU
502 implements ARMv8.1 hardware PAN support and using hardware PAN
503 support versus software PAN emulation is mutually exclusive at
508 config QCOM_FALKOR_ERRATUM_1009
509 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
512 On Falkor v1, the CPU may prematurely complete a DSB following a
513 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
514 one more time to fix the issue.
518 config QCOM_QDF2400_ERRATUM_0065
519 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
522 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
523 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
524 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
533 default ARM64_4K_PAGES
535 Page size (translation granule) configuration.
537 config ARM64_4K_PAGES
540 This feature enables 4KB pages support.
542 config ARM64_16K_PAGES
545 The system will use 16KB pages support. AArch32 emulation
546 requires applications compiled with 16K (or a multiple of 16K)
549 config ARM64_64K_PAGES
552 This feature enables 64KB pages support (4KB by default)
553 allowing only two levels of page tables and faster TLB
554 look-up. AArch32 emulation requires applications compiled
555 with 64K aligned segments.
560 prompt "Virtual address space size"
561 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
562 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
563 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
565 Allows choosing one of multiple possible virtual address
566 space sizes. The level of translation table is determined by
567 a combination of page size and virtual address space size.
569 config ARM64_VA_BITS_36
570 bool "36-bit" if EXPERT
571 depends on ARM64_16K_PAGES
573 config ARM64_VA_BITS_39
575 depends on ARM64_4K_PAGES
577 config ARM64_VA_BITS_42
579 depends on ARM64_64K_PAGES
581 config ARM64_VA_BITS_47
583 depends on ARM64_16K_PAGES
585 config ARM64_VA_BITS_48
592 default 36 if ARM64_VA_BITS_36
593 default 39 if ARM64_VA_BITS_39
594 default 42 if ARM64_VA_BITS_42
595 default 47 if ARM64_VA_BITS_47
596 default 48 if ARM64_VA_BITS_48
598 config CPU_BIG_ENDIAN
599 bool "Build big-endian kernel"
601 Say Y if you plan on running a kernel in big-endian mode.
604 bool "Multi-core scheduler support"
606 Multi-core scheduler support improves the CPU scheduler's decision
607 making when dealing with multi-core CPU chips at a cost of slightly
608 increased overhead in some places. If unsure say N here.
611 bool "SMT scheduler support"
613 Improves the CPU scheduler's decision making when dealing with
614 MultiThreading at a cost of slightly increased overhead in some
615 places. If unsure say N here.
618 int "Maximum number of CPUs (2-4096)"
620 # These have to remain sorted largest to smallest
624 bool "Support for hot-pluggable CPUs"
625 select GENERIC_IRQ_MIGRATION
627 Say Y here to experiment with turning CPUs off and on. CPUs
628 can be controlled through /sys/devices/system/cpu.
630 # Common NUMA Features
632 bool "Numa Memory Allocation and Scheduler Support"
633 select ACPI_NUMA if ACPI
636 Enable NUMA (Non Uniform Memory Access) support.
638 The kernel will try to allocate memory used by a CPU on the
639 local memory of the CPU and add some more
640 NUMA awareness to the kernel.
643 int "Maximum NUMA Nodes (as a power of 2)"
646 depends on NEED_MULTIPLE_NODES
648 Specify the maximum number of NUMA Nodes available on the target
649 system. Increases memory reserved to accommodate various tables.
651 config USE_PERCPU_NUMA_NODE_ID
655 config HAVE_SETUP_PER_CPU_AREA
659 config NEED_PER_CPU_EMBED_FIRST_CHUNK
667 source kernel/Kconfig.preempt
668 source kernel/Kconfig.hz
670 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
673 config ARCH_HAS_HOLES_MEMORYMODEL
674 def_bool y if SPARSEMEM
676 config ARCH_SPARSEMEM_ENABLE
678 select SPARSEMEM_VMEMMAP_ENABLE
680 config ARCH_SPARSEMEM_DEFAULT
681 def_bool ARCH_SPARSEMEM_ENABLE
683 config ARCH_SELECT_MEMORY_MODEL
684 def_bool ARCH_SPARSEMEM_ENABLE
686 config HAVE_ARCH_PFN_VALID
687 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
689 config HW_PERF_EVENTS
693 config SYS_SUPPORTS_HUGETLBFS
696 config ARCH_WANT_HUGE_PMD_SHARE
697 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
699 config ARCH_HAS_CACHE_LINE_SIZE
705 bool "Enable seccomp to safely compute untrusted bytecode"
707 This kernel feature is useful for number crunching applications
708 that may need to compute untrusted bytecode during their
709 execution. By using pipes or other transports made available to
710 the process as file descriptors supporting the read/write
711 syscalls, it's possible to isolate those applications in
712 their own address space using seccomp. Once seccomp is
713 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
714 and the task is only allowed to execute a few safe syscalls
715 defined by each seccomp mode.
718 bool "Enable paravirtualization code"
720 This changes the kernel so it can modify itself when it is run
721 under a hypervisor, potentially improving performance significantly
722 over full virtualization.
724 config PARAVIRT_TIME_ACCOUNTING
725 bool "Paravirtual steal time accounting"
729 Select this option to enable fine granularity task steal time
730 accounting. Time spent executing other tasks in parallel with
731 the current vCPU is discounted from the vCPU power. To account for
732 that, there can be a small performance impact.
734 If in doubt, say N here.
737 depends on PM_SLEEP_SMP
739 bool "kexec system call"
741 kexec is a system call that implements the ability to shutdown your
742 current kernel, and to start another kernel. It is like a reboot
743 but it is independent of the system firmware. And like a reboot
744 you can start any kernel with it, not just Linux.
747 bool "Build kdump crash kernel"
749 Generate crash dump after being started by kexec. This should
750 be normally only set in special crash dump kernels which are
751 loaded in the main kernel with kexec-tools into a specially
752 reserved region and then later executed after a crash by
755 For more details see Documentation/kdump/kdump.txt
762 bool "Xen guest support on ARM64"
763 depends on ARM64 && OF
767 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
769 config FORCE_MAX_ZONEORDER
771 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
772 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
775 The kernel memory allocator divides physically contiguous memory
776 blocks into "zones", where each zone is a power of two number of
777 pages. This option selects the largest power of two that the kernel
778 keeps in the memory allocator. If you need to allocate very large
779 blocks of physically contiguous memory, then you may need to
782 This config option is actually maximum order plus one. For example,
783 a value of 11 means that the largest free memory block is 2^10 pages.
785 We make sure that we can allocate upto a HugePage size for each configuration.
787 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
789 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
790 4M allocations matching the default size used by generic code.
792 menuconfig ARMV8_DEPRECATED
793 bool "Emulate deprecated/obsolete ARMv8 instructions"
796 Legacy software support may require certain instructions
797 that have been deprecated or obsoleted in the architecture.
799 Enable this config to enable selective emulation of these
807 bool "Emulate SWP/SWPB instructions"
809 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
810 they are always undefined. Say Y here to enable software
811 emulation of these instructions for userspace using LDXR/STXR.
813 In some older versions of glibc [<=2.8] SWP is used during futex
814 trylock() operations with the assumption that the code will not
815 be preempted. This invalid assumption may be more likely to fail
816 with SWP emulation enabled, leading to deadlock of the user
819 NOTE: when accessing uncached shared regions, LDXR/STXR rely
820 on an external transaction monitoring block called a global
821 monitor to maintain update atomicity. If your system does not
822 implement a global monitor, this option can cause programs that
823 perform SWP operations to uncached memory to deadlock.
827 config CP15_BARRIER_EMULATION
828 bool "Emulate CP15 Barrier instructions"
830 The CP15 barrier instructions - CP15ISB, CP15DSB, and
831 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
832 strongly recommended to use the ISB, DSB, and DMB
833 instructions instead.
835 Say Y here to enable software emulation of these
836 instructions for AArch32 userspace code. When this option is
837 enabled, CP15 barrier usage is traced which can help
838 identify software that needs updating.
842 config SETEND_EMULATION
843 bool "Emulate SETEND instruction"
845 The SETEND instruction alters the data-endianness of the
846 AArch32 EL0, and is deprecated in ARMv8.
848 Say Y here to enable software emulation of the instruction
849 for AArch32 userspace code.
851 Note: All the cpus on the system must have mixed endian support at EL0
852 for this feature to be enabled. If a new CPU - which doesn't support mixed
853 endian - is hotplugged in after this feature has been enabled, there could
854 be unexpected results in the applications.
859 config ARM64_SW_TTBR0_PAN
860 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
862 Enabling this option prevents the kernel from accessing
863 user-space memory directly by pointing TTBR0_EL1 to a reserved
864 zeroed area and reserved ASID. The user access routines
865 restore the valid TTBR0_EL1 temporarily.
867 menu "ARMv8.1 architectural features"
869 config ARM64_HW_AFDBM
870 bool "Support for hardware updates of the Access and Dirty page flags"
873 The ARMv8.1 architecture extensions introduce support for
874 hardware updates of the access and dirty information in page
875 table entries. When enabled in TCR_EL1 (HA and HD bits) on
876 capable processors, accesses to pages with PTE_AF cleared will
877 set this bit instead of raising an access flag fault.
878 Similarly, writes to read-only pages with the DBM bit set will
879 clear the read-only bit (AP[2]) instead of raising a
882 Kernels built with this configuration option enabled continue
883 to work on pre-ARMv8.1 hardware and the performance impact is
884 minimal. If unsure, say Y.
887 bool "Enable support for Privileged Access Never (PAN)"
890 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
891 prevents the kernel or hypervisor from accessing user-space (EL0)
894 Choosing this option will cause any unprotected (not using
895 copy_to_user et al) memory access to fail with a permission fault.
897 The feature is detected at runtime, and will remain as a 'nop'
898 instruction if the cpu does not implement the feature.
900 config ARM64_LSE_ATOMICS
901 bool "Atomic instructions"
903 As part of the Large System Extensions, ARMv8.1 introduces new
904 atomic instructions that are designed specifically to scale in
907 Say Y here to make use of these instructions for the in-kernel
908 atomic routines. This incurs a small overhead on CPUs that do
909 not support these instructions and requires the kernel to be
910 built with binutils >= 2.25.
913 bool "Enable support for Virtualization Host Extensions (VHE)"
916 Virtualization Host Extensions (VHE) allow the kernel to run
917 directly at EL2 (instead of EL1) on processors that support
918 it. This leads to better performance for KVM, as they reduce
919 the cost of the world switch.
921 Selecting this option allows the VHE feature to be detected
922 at runtime, and does not affect processors that do not
923 implement this feature.
927 menu "ARMv8.2 architectural features"
930 bool "Enable support for User Access Override (UAO)"
933 User Access Override (UAO; part of the ARMv8.2 Extensions)
934 causes the 'unprivileged' variant of the load/store instructions to
935 be overriden to be privileged.
937 This option changes get_user() and friends to use the 'unprivileged'
938 variant of the load/store instructions. This ensures that user-space
939 really did have access to the supplied memory. When addr_limit is
940 set to kernel memory the UAO bit will be set, allowing privileged
941 access to kernel memory.
943 Choosing this option will cause copy_to_user() et al to use user-space
946 The feature is detected at runtime, the kernel will use the
947 regular load/store instructions if the cpu does not implement the
952 config ARM64_MODULE_CMODEL_LARGE
955 config ARM64_MODULE_PLTS
957 select ARM64_MODULE_CMODEL_LARGE
958 select HAVE_MOD_ARCH_SPECIFIC
963 This builds the kernel as a Position Independent Executable (PIE),
964 which retains all relocation metadata required to relocate the
965 kernel binary at runtime to a different virtual address than the
966 address it was linked at.
967 Since AArch64 uses the RELA relocation format, this requires a
968 relocation pass at runtime even if the kernel is loaded at the
969 same address it was linked at.
971 config RANDOMIZE_BASE
972 bool "Randomize the address of the kernel image"
973 select ARM64_MODULE_PLTS if MODULES
976 Randomizes the virtual address at which the kernel image is
977 loaded, as a security feature that deters exploit attempts
978 relying on knowledge of the location of kernel internals.
980 It is the bootloader's job to provide entropy, by passing a
981 random u64 value in /chosen/kaslr-seed at kernel entry.
983 When booting via the UEFI stub, it will invoke the firmware's
984 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
985 to the kernel proper. In addition, it will randomise the physical
986 location of the kernel Image as well.
990 config RANDOMIZE_MODULE_REGION_FULL
991 bool "Randomize the module region independently from the core kernel"
992 depends on RANDOMIZE_BASE
995 Randomizes the location of the module region without considering the
996 location of the core kernel. This way, it is impossible for modules
997 to leak information about the location of core kernel data structures
998 but it does imply that function calls between modules and the core
999 kernel will need to be resolved via veneers in the module PLT.
1001 When this option is not set, the module region will be randomized over
1002 a limited range that contains the [_stext, _etext] interval of the
1003 core kernel, so branch relocations are always in range.
1009 config ARM64_ACPI_PARKING_PROTOCOL
1010 bool "Enable support for the ARM64 ACPI parking protocol"
1013 Enable support for the ARM64 ACPI parking protocol. If disabled
1014 the kernel will not allow booting through the ARM64 ACPI parking
1015 protocol even if the corresponding data is present in the ACPI
1019 string "Default kernel command string"
1022 Provide a set of default command-line options at build time by
1023 entering them here. As a minimum, you should specify the the
1024 root device (e.g. root=/dev/nfs).
1026 config CMDLINE_FORCE
1027 bool "Always use the default kernel command string"
1029 Always use the default kernel command string, even if the boot
1030 loader passes other arguments to the kernel.
1031 This is useful if you cannot or don't want to change the
1032 command-line options your boot loader passes to the kernel.
1038 bool "UEFI runtime support"
1039 depends on OF && !CPU_BIG_ENDIAN
1042 select EFI_PARAMS_FROM_FDT
1043 select EFI_RUNTIME_WRAPPERS
1048 This option provides support for runtime services provided
1049 by UEFI firmware (such as non-volatile variables, realtime
1050 clock, and platform reset). A UEFI stub is also provided to
1051 allow the kernel to be booted as an EFI application. This
1052 is only useful on systems that have UEFI firmware.
1055 bool "Enable support for SMBIOS (DMI) tables"
1059 This enables SMBIOS/DMI feature for systems.
1061 This option is only useful on systems that have UEFI firmware.
1062 However, even with this option, the resultant kernel should
1063 continue to boot on existing non-UEFI platforms.
1067 menu "Userspace binary formats"
1069 source "fs/Kconfig.binfmt"
1072 bool "Kernel support for 32-bit EL0"
1073 depends on ARM64_4K_PAGES || EXPERT
1074 select COMPAT_BINFMT_ELF if BINFMT_ELF
1076 select OLD_SIGSUSPEND3
1077 select COMPAT_OLD_SIGACTION
1079 This option enables support for a 32-bit EL0 running under a 64-bit
1080 kernel at EL1. AArch32-specific components such as system calls,
1081 the user helper functions, VFP support and the ptrace interface are
1082 handled appropriately by the kernel.
1084 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1085 that you will only be able to execute AArch32 binaries that were compiled
1086 with page size aligned segments.
1088 If you want to execute 32-bit userspace applications, say Y.
1090 config SYSVIPC_COMPAT
1092 depends on COMPAT && SYSVIPC
1096 depends on COMPAT && KEYS
1100 menu "Power management options"
1102 source "kernel/power/Kconfig"
1104 config ARCH_HIBERNATION_POSSIBLE
1108 config ARCH_HIBERNATION_HEADER
1110 depends on HIBERNATION
1112 config ARCH_SUSPEND_POSSIBLE
1117 menu "CPU Power Management"
1119 source "drivers/cpuidle/Kconfig"
1121 source "drivers/cpufreq/Kconfig"
1125 source "net/Kconfig"
1127 source "drivers/Kconfig"
1129 source "drivers/firmware/Kconfig"
1131 source "drivers/acpi/Kconfig"
1135 source "arch/arm64/kvm/Kconfig"
1137 source "arch/arm64/Kconfig.debug"
1139 source "security/Kconfig"
1141 source "crypto/Kconfig"
1143 source "arch/arm64/crypto/Kconfig"
1146 source "lib/Kconfig"