3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_DEVMEM_IS_ALLOWED
7 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
8 select ARCH_HAS_ELF_RANDOMIZE
9 select ARCH_HAS_GCOV_PROFILE_ALL
11 select ARCH_HAS_SG_CHAIN
12 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
13 select ARCH_USE_CMPXCHG_LOCKREF
14 select ARCH_SUPPORTS_ATOMIC_RMW
15 select ARCH_SUPPORTS_NUMA_BALANCING
16 select ARCH_WANT_OPTIONAL_GPIOLIB
17 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
18 select ARCH_WANT_FRAME_POINTERS
19 select ARCH_HAS_UBSAN_SANITIZE_ALL
23 select AUDIT_ARCH_COMPAT_GENERIC
24 select ARM_GIC_V2M if PCI_MSI
26 select ARM_GIC_V3_ITS if PCI_MSI
28 select BUILDTIME_EXTABLE_SORT
29 select CLONE_BACKWARDS
31 select CPU_PM if (SUSPEND || CPU_IDLE)
32 select DCACHE_WORD_ACCESS
35 select GENERIC_ALLOCATOR
36 select GENERIC_CLOCKEVENTS
37 select GENERIC_CLOCKEVENTS_BROADCAST
38 select GENERIC_CPU_AUTOPROBE
39 select GENERIC_EARLY_IOREMAP
40 select GENERIC_IDLE_POLL_SETUP
41 select GENERIC_IRQ_PROBE
42 select GENERIC_IRQ_SHOW
43 select GENERIC_IRQ_SHOW_LEVEL
44 select GENERIC_PCI_IOMAP
45 select GENERIC_SCHED_CLOCK
46 select GENERIC_SMP_IDLE_THREAD
47 select GENERIC_STRNCPY_FROM_USER
48 select GENERIC_STRNLEN_USER
49 select GENERIC_TIME_VSYSCALL
50 select HANDLE_DOMAIN_IRQ
51 select HARDIRQS_SW_RESEND
52 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
53 select HAVE_ARCH_AUDITSYSCALL
54 select HAVE_ARCH_BITREVERSE
55 select HAVE_ARCH_HUGE_VMAP
56 select HAVE_ARCH_JUMP_LABEL
57 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
59 select HAVE_ARCH_MMAP_RND_BITS
60 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
61 select HAVE_ARCH_SECCOMP_FILTER
62 select HAVE_ARCH_TRACEHOOK
63 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
66 select HAVE_C_RECORDMCOUNT
67 select HAVE_CC_STACKPROTECTOR
68 select HAVE_CMPXCHG_DOUBLE
69 select HAVE_CMPXCHG_LOCAL
70 select HAVE_CONTEXT_TRACKING
71 select HAVE_DEBUG_BUGVERBOSE
72 select HAVE_DEBUG_KMEMLEAK
73 select HAVE_DMA_API_DEBUG
74 select HAVE_DMA_CONTIGUOUS
75 select HAVE_DYNAMIC_FTRACE
76 select HAVE_EFFICIENT_UNALIGNED_ACCESS
77 select HAVE_FTRACE_MCOUNT_RECORD
78 select HAVE_FUNCTION_TRACER
79 select HAVE_FUNCTION_GRAPH_TRACER
80 select HAVE_GENERIC_DMA_COHERENT
81 select HAVE_HW_BREAKPOINT if PERF_EVENTS
82 select HAVE_IRQ_TIME_ACCOUNTING
84 select HAVE_MEMBLOCK_NODE_MAP if NUMA
85 select HAVE_PATA_PLATFORM
86 select HAVE_PERF_EVENTS
88 select HAVE_PERF_USER_STACK_DUMP
89 select HAVE_RCU_TABLE_FREE
90 select HAVE_SYSCALL_TRACEPOINTS
91 select IOMMU_DMA if IOMMU_SUPPORT
93 select IRQ_FORCED_THREADING
94 select MODULES_USE_ELF_RELA
97 select OF_EARLY_FLATTREE
98 select OF_NUMA if NUMA && OF
99 select OF_RESERVED_MEM
100 select PERF_USE_VMALLOC
104 select SYSCTL_EXCEPTION_TRACE
106 ARM 64-bit (AArch64) Linux support.
111 config ARCH_PHYS_ADDR_T_64BIT
117 config ARM64_PAGE_SHIFT
119 default 16 if ARM64_64K_PAGES
120 default 14 if ARM64_16K_PAGES
123 config ARM64_CONT_SHIFT
125 default 5 if ARM64_64K_PAGES
126 default 7 if ARM64_16K_PAGES
129 config ARCH_MMAP_RND_BITS_MIN
130 default 14 if ARM64_64K_PAGES
131 default 16 if ARM64_16K_PAGES
134 # max bits determined by the following formula:
135 # VA_BITS - PAGE_SHIFT - 3
136 config ARCH_MMAP_RND_BITS_MAX
137 default 19 if ARM64_VA_BITS=36
138 default 24 if ARM64_VA_BITS=39
139 default 27 if ARM64_VA_BITS=42
140 default 30 if ARM64_VA_BITS=47
141 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
142 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
143 default 33 if ARM64_VA_BITS=48
144 default 14 if ARM64_64K_PAGES
145 default 16 if ARM64_16K_PAGES
148 config ARCH_MMAP_RND_COMPAT_BITS_MIN
149 default 7 if ARM64_64K_PAGES
150 default 9 if ARM64_16K_PAGES
153 config ARCH_MMAP_RND_COMPAT_BITS_MAX
159 config STACKTRACE_SUPPORT
162 config ILLEGAL_POINTER_VALUE
164 default 0xdead000000000000
166 config LOCKDEP_SUPPORT
169 config TRACE_IRQFLAGS_SUPPORT
172 config RWSEM_XCHGADD_ALGORITHM
179 config GENERIC_BUG_RELATIVE_POINTERS
181 depends on GENERIC_BUG
183 config GENERIC_HWEIGHT
189 config GENERIC_CALIBRATE_DELAY
195 config HAVE_GENERIC_RCU_GUP
198 config ARCH_DMA_ADDR_T_64BIT
201 config NEED_DMA_MAP_STATE
204 config NEED_SG_DMA_LENGTH
216 config KERNEL_MODE_NEON
219 config FIX_EARLYCON_MEM
222 config PGTABLE_LEVELS
224 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
225 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
226 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
227 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
228 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
229 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
231 source "init/Kconfig"
233 source "kernel/Kconfig.freezer"
235 source "arch/arm64/Kconfig.platforms"
242 This feature enables support for PCI bus system. If you say Y
243 here, the kernel will include drivers and infrastructure code
244 to support PCI bus devices.
249 config PCI_DOMAINS_GENERIC
255 source "drivers/pci/Kconfig"
259 menu "Kernel Features"
261 menu "ARM errata workarounds via the alternatives framework"
263 config ARM64_ERRATUM_826319
264 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
267 This option adds an alternative code sequence to work around ARM
268 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
269 AXI master interface and an L2 cache.
271 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
272 and is unable to accept a certain write via this interface, it will
273 not progress on read data presented on the read data channel and the
276 The workaround promotes data cache clean instructions to
277 data cache clean-and-invalidate.
278 Please note that this does not necessarily enable the workaround,
279 as it depends on the alternative framework, which will only patch
280 the kernel if an affected CPU is detected.
284 config ARM64_ERRATUM_827319
285 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
288 This option adds an alternative code sequence to work around ARM
289 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
290 master interface and an L2 cache.
292 Under certain conditions this erratum can cause a clean line eviction
293 to occur at the same time as another transaction to the same address
294 on the AMBA 5 CHI interface, which can cause data corruption if the
295 interconnect reorders the two transactions.
297 The workaround promotes data cache clean instructions to
298 data cache clean-and-invalidate.
299 Please note that this does not necessarily enable the workaround,
300 as it depends on the alternative framework, which will only patch
301 the kernel if an affected CPU is detected.
305 config ARM64_ERRATUM_824069
306 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
309 This option adds an alternative code sequence to work around ARM
310 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
311 to a coherent interconnect.
313 If a Cortex-A53 processor is executing a store or prefetch for
314 write instruction at the same time as a processor in another
315 cluster is executing a cache maintenance operation to the same
316 address, then this erratum might cause a clean cache line to be
317 incorrectly marked as dirty.
319 The workaround promotes data cache clean instructions to
320 data cache clean-and-invalidate.
321 Please note that this option does not necessarily enable the
322 workaround, as it depends on the alternative framework, which will
323 only patch the kernel if an affected CPU is detected.
327 config ARM64_ERRATUM_819472
328 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
331 This option adds an alternative code sequence to work around ARM
332 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
333 present when it is connected to a coherent interconnect.
335 If the processor is executing a load and store exclusive sequence at
336 the same time as a processor in another cluster is executing a cache
337 maintenance operation to the same address, then this erratum might
338 cause data corruption.
340 The workaround promotes data cache clean instructions to
341 data cache clean-and-invalidate.
342 Please note that this does not necessarily enable the workaround,
343 as it depends on the alternative framework, which will only patch
344 the kernel if an affected CPU is detected.
348 config ARM64_ERRATUM_832075
349 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
352 This option adds an alternative code sequence to work around ARM
353 erratum 832075 on Cortex-A57 parts up to r1p2.
355 Affected Cortex-A57 parts might deadlock when exclusive load/store
356 instructions to Write-Back memory are mixed with Device loads.
358 The workaround is to promote device loads to use Load-Acquire
360 Please note that this does not necessarily enable the workaround,
361 as it depends on the alternative framework, which will only patch
362 the kernel if an affected CPU is detected.
366 config ARM64_ERRATUM_834220
367 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
371 This option adds an alternative code sequence to work around ARM
372 erratum 834220 on Cortex-A57 parts up to r1p2.
374 Affected Cortex-A57 parts might report a Stage 2 translation
375 fault as the result of a Stage 1 fault for load crossing a
376 page boundary when there is a permission or device memory
377 alignment fault at Stage 1 and a translation fault at Stage 2.
379 The workaround is to verify that the Stage 1 translation
380 doesn't generate a fault before handling the Stage 2 fault.
381 Please note that this does not necessarily enable the workaround,
382 as it depends on the alternative framework, which will only patch
383 the kernel if an affected CPU is detected.
387 config ARM64_ERRATUM_845719
388 bool "Cortex-A53: 845719: a load might read incorrect data"
392 This option adds an alternative code sequence to work around ARM
393 erratum 845719 on Cortex-A53 parts up to r0p4.
395 When running a compat (AArch32) userspace on an affected Cortex-A53
396 part, a load at EL0 from a virtual address that matches the bottom 32
397 bits of the virtual address used by a recent load at (AArch64) EL1
398 might return incorrect data.
400 The workaround is to write the contextidr_el1 register on exception
401 return to a 32-bit task.
402 Please note that this does not necessarily enable the workaround,
403 as it depends on the alternative framework, which will only patch
404 the kernel if an affected CPU is detected.
408 config ARM64_ERRATUM_843419
409 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
412 select ARM64_MODULE_CMODEL_LARGE
414 This option builds kernel modules using the large memory model in
415 order to avoid the use of the ADRP instruction, which can cause
416 a subsequent memory access to use an incorrect address on Cortex-A53
419 Note that the kernel itself must be linked with a version of ld
420 which fixes potentially affected ADRP instructions through the
425 config CAVIUM_ERRATUM_22375
426 bool "Cavium erratum 22375, 24313"
429 Enable workaround for erratum 22375, 24313.
431 This implements two gicv3-its errata workarounds for ThunderX. Both
432 with small impact affecting only ITS table allocation.
434 erratum 22375: only alloc 8MB table size
435 erratum 24313: ignore memory access type
437 The fixes are in ITS initialization and basically ignore memory access
438 type and table size provided by the TYPER and BASER registers.
442 config CAVIUM_ERRATUM_23144
443 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
447 ITS SYNC command hang for cross node io and collections/cpu mapping.
451 config CAVIUM_ERRATUM_23154
452 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
455 The gicv3 of ThunderX requires a modified version for
456 reading the IAR status to ensure data synchronization
457 (access to icc_iar1_el1 is not sync'ed before and after).
461 config CAVIUM_ERRATUM_27456
462 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
465 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
466 instructions may cause the icache to become corrupted if it
467 contains data for a non-current ASID. The fix is to
468 invalidate the icache when changing the mm context.
477 default ARM64_4K_PAGES
479 Page size (translation granule) configuration.
481 config ARM64_4K_PAGES
484 This feature enables 4KB pages support.
486 config ARM64_16K_PAGES
489 The system will use 16KB pages support. AArch32 emulation
490 requires applications compiled with 16K (or a multiple of 16K)
493 config ARM64_64K_PAGES
496 This feature enables 64KB pages support (4KB by default)
497 allowing only two levels of page tables and faster TLB
498 look-up. AArch32 emulation requires applications compiled
499 with 64K aligned segments.
504 prompt "Virtual address space size"
505 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
506 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
507 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
509 Allows choosing one of multiple possible virtual address
510 space sizes. The level of translation table is determined by
511 a combination of page size and virtual address space size.
513 config ARM64_VA_BITS_36
514 bool "36-bit" if EXPERT
515 depends on ARM64_16K_PAGES
517 config ARM64_VA_BITS_39
519 depends on ARM64_4K_PAGES
521 config ARM64_VA_BITS_42
523 depends on ARM64_64K_PAGES
525 config ARM64_VA_BITS_47
527 depends on ARM64_16K_PAGES
529 config ARM64_VA_BITS_48
536 default 36 if ARM64_VA_BITS_36
537 default 39 if ARM64_VA_BITS_39
538 default 42 if ARM64_VA_BITS_42
539 default 47 if ARM64_VA_BITS_47
540 default 48 if ARM64_VA_BITS_48
542 config CPU_BIG_ENDIAN
543 bool "Build big-endian kernel"
545 Say Y if you plan on running a kernel in big-endian mode.
548 bool "Multi-core scheduler support"
550 Multi-core scheduler support improves the CPU scheduler's decision
551 making when dealing with multi-core CPU chips at a cost of slightly
552 increased overhead in some places. If unsure say N here.
555 bool "SMT scheduler support"
557 Improves the CPU scheduler's decision making when dealing with
558 MultiThreading at a cost of slightly increased overhead in some
559 places. If unsure say N here.
562 int "Maximum number of CPUs (2-4096)"
564 # These have to remain sorted largest to smallest
568 bool "Support for hot-pluggable CPUs"
569 select GENERIC_IRQ_MIGRATION
571 Say Y here to experiment with turning CPUs off and on. CPUs
572 can be controlled through /sys/devices/system/cpu.
574 # Common NUMA Features
576 bool "Numa Memory Allocation and Scheduler Support"
579 Enable NUMA (Non Uniform Memory Access) support.
581 The kernel will try to allocate memory used by a CPU on the
582 local memory of the CPU and add some more
583 NUMA awareness to the kernel.
586 int "Maximum NUMA Nodes (as a power of 2)"
589 depends on NEED_MULTIPLE_NODES
591 Specify the maximum number of NUMA Nodes available on the target
592 system. Increases memory reserved to accommodate various tables.
594 config USE_PERCPU_NUMA_NODE_ID
598 source kernel/Kconfig.preempt
599 source kernel/Kconfig.hz
601 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
602 depends on !HIBERNATION
605 config ARCH_HAS_HOLES_MEMORYMODEL
606 def_bool y if SPARSEMEM
608 config ARCH_SPARSEMEM_ENABLE
610 select SPARSEMEM_VMEMMAP_ENABLE
612 config ARCH_SPARSEMEM_DEFAULT
613 def_bool ARCH_SPARSEMEM_ENABLE
615 config ARCH_SELECT_MEMORY_MODEL
616 def_bool ARCH_SPARSEMEM_ENABLE
618 config HAVE_ARCH_PFN_VALID
619 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
621 config HW_PERF_EVENTS
625 config SYS_SUPPORTS_HUGETLBFS
628 config ARCH_WANT_HUGE_PMD_SHARE
629 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
631 config ARCH_HAS_CACHE_LINE_SIZE
637 bool "Enable seccomp to safely compute untrusted bytecode"
639 This kernel feature is useful for number crunching applications
640 that may need to compute untrusted bytecode during their
641 execution. By using pipes or other transports made available to
642 the process as file descriptors supporting the read/write
643 syscalls, it's possible to isolate those applications in
644 their own address space using seccomp. Once seccomp is
645 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
646 and the task is only allowed to execute a few safe syscalls
647 defined by each seccomp mode.
650 bool "Enable paravirtualization code"
652 This changes the kernel so it can modify itself when it is run
653 under a hypervisor, potentially improving performance significantly
654 over full virtualization.
656 config PARAVIRT_TIME_ACCOUNTING
657 bool "Paravirtual steal time accounting"
661 Select this option to enable fine granularity task steal time
662 accounting. Time spent executing other tasks in parallel with
663 the current vCPU is discounted from the vCPU power. To account for
664 that, there can be a small performance impact.
666 If in doubt, say N here.
673 bool "Xen guest support on ARM64"
674 depends on ARM64 && OF
678 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
680 config FORCE_MAX_ZONEORDER
682 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
683 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
686 The kernel memory allocator divides physically contiguous memory
687 blocks into "zones", where each zone is a power of two number of
688 pages. This option selects the largest power of two that the kernel
689 keeps in the memory allocator. If you need to allocate very large
690 blocks of physically contiguous memory, then you may need to
693 This config option is actually maximum order plus one. For example,
694 a value of 11 means that the largest free memory block is 2^10 pages.
696 We make sure that we can allocate upto a HugePage size for each configuration.
698 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
700 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
701 4M allocations matching the default size used by generic code.
703 menuconfig ARMV8_DEPRECATED
704 bool "Emulate deprecated/obsolete ARMv8 instructions"
707 Legacy software support may require certain instructions
708 that have been deprecated or obsoleted in the architecture.
710 Enable this config to enable selective emulation of these
718 bool "Emulate SWP/SWPB instructions"
720 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
721 they are always undefined. Say Y here to enable software
722 emulation of these instructions for userspace using LDXR/STXR.
724 In some older versions of glibc [<=2.8] SWP is used during futex
725 trylock() operations with the assumption that the code will not
726 be preempted. This invalid assumption may be more likely to fail
727 with SWP emulation enabled, leading to deadlock of the user
730 NOTE: when accessing uncached shared regions, LDXR/STXR rely
731 on an external transaction monitoring block called a global
732 monitor to maintain update atomicity. If your system does not
733 implement a global monitor, this option can cause programs that
734 perform SWP operations to uncached memory to deadlock.
738 config CP15_BARRIER_EMULATION
739 bool "Emulate CP15 Barrier instructions"
741 The CP15 barrier instructions - CP15ISB, CP15DSB, and
742 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
743 strongly recommended to use the ISB, DSB, and DMB
744 instructions instead.
746 Say Y here to enable software emulation of these
747 instructions for AArch32 userspace code. When this option is
748 enabled, CP15 barrier usage is traced which can help
749 identify software that needs updating.
753 config SETEND_EMULATION
754 bool "Emulate SETEND instruction"
756 The SETEND instruction alters the data-endianness of the
757 AArch32 EL0, and is deprecated in ARMv8.
759 Say Y here to enable software emulation of the instruction
760 for AArch32 userspace code.
762 Note: All the cpus on the system must have mixed endian support at EL0
763 for this feature to be enabled. If a new CPU - which doesn't support mixed
764 endian - is hotplugged in after this feature has been enabled, there could
765 be unexpected results in the applications.
770 menu "ARMv8.1 architectural features"
772 config ARM64_HW_AFDBM
773 bool "Support for hardware updates of the Access and Dirty page flags"
776 The ARMv8.1 architecture extensions introduce support for
777 hardware updates of the access and dirty information in page
778 table entries. When enabled in TCR_EL1 (HA and HD bits) on
779 capable processors, accesses to pages with PTE_AF cleared will
780 set this bit instead of raising an access flag fault.
781 Similarly, writes to read-only pages with the DBM bit set will
782 clear the read-only bit (AP[2]) instead of raising a
785 Kernels built with this configuration option enabled continue
786 to work on pre-ARMv8.1 hardware and the performance impact is
787 minimal. If unsure, say Y.
790 bool "Enable support for Privileged Access Never (PAN)"
793 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
794 prevents the kernel or hypervisor from accessing user-space (EL0)
797 Choosing this option will cause any unprotected (not using
798 copy_to_user et al) memory access to fail with a permission fault.
800 The feature is detected at runtime, and will remain as a 'nop'
801 instruction if the cpu does not implement the feature.
803 config ARM64_LSE_ATOMICS
804 bool "Atomic instructions"
806 As part of the Large System Extensions, ARMv8.1 introduces new
807 atomic instructions that are designed specifically to scale in
810 Say Y here to make use of these instructions for the in-kernel
811 atomic routines. This incurs a small overhead on CPUs that do
812 not support these instructions and requires the kernel to be
813 built with binutils >= 2.25.
816 bool "Enable support for Virtualization Host Extensions (VHE)"
819 Virtualization Host Extensions (VHE) allow the kernel to run
820 directly at EL2 (instead of EL1) on processors that support
821 it. This leads to better performance for KVM, as they reduce
822 the cost of the world switch.
824 Selecting this option allows the VHE feature to be detected
825 at runtime, and does not affect processors that do not
826 implement this feature.
830 menu "ARMv8.2 architectural features"
833 bool "Enable support for User Access Override (UAO)"
836 User Access Override (UAO; part of the ARMv8.2 Extensions)
837 causes the 'unprivileged' variant of the load/store instructions to
838 be overriden to be privileged.
840 This option changes get_user() and friends to use the 'unprivileged'
841 variant of the load/store instructions. This ensures that user-space
842 really did have access to the supplied memory. When addr_limit is
843 set to kernel memory the UAO bit will be set, allowing privileged
844 access to kernel memory.
846 Choosing this option will cause copy_to_user() et al to use user-space
849 The feature is detected at runtime, the kernel will use the
850 regular load/store instructions if the cpu does not implement the
855 config ARM64_MODULE_CMODEL_LARGE
858 config ARM64_MODULE_PLTS
860 select ARM64_MODULE_CMODEL_LARGE
861 select HAVE_MOD_ARCH_SPECIFIC
866 This builds the kernel as a Position Independent Executable (PIE),
867 which retains all relocation metadata required to relocate the
868 kernel binary at runtime to a different virtual address than the
869 address it was linked at.
870 Since AArch64 uses the RELA relocation format, this requires a
871 relocation pass at runtime even if the kernel is loaded at the
872 same address it was linked at.
874 config RANDOMIZE_BASE
875 bool "Randomize the address of the kernel image"
876 select ARM64_MODULE_PLTS
879 Randomizes the virtual address at which the kernel image is
880 loaded, as a security feature that deters exploit attempts
881 relying on knowledge of the location of kernel internals.
883 It is the bootloader's job to provide entropy, by passing a
884 random u64 value in /chosen/kaslr-seed at kernel entry.
886 When booting via the UEFI stub, it will invoke the firmware's
887 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
888 to the kernel proper. In addition, it will randomise the physical
889 location of the kernel Image as well.
893 config RANDOMIZE_MODULE_REGION_FULL
894 bool "Randomize the module region independently from the core kernel"
895 depends on RANDOMIZE_BASE
898 Randomizes the location of the module region without considering the
899 location of the core kernel. This way, it is impossible for modules
900 to leak information about the location of core kernel data structures
901 but it does imply that function calls between modules and the core
902 kernel will need to be resolved via veneers in the module PLT.
904 When this option is not set, the module region will be randomized over
905 a limited range that contains the [_stext, _etext] interval of the
906 core kernel, so branch relocations are always in range.
912 config ARM64_ACPI_PARKING_PROTOCOL
913 bool "Enable support for the ARM64 ACPI parking protocol"
916 Enable support for the ARM64 ACPI parking protocol. If disabled
917 the kernel will not allow booting through the ARM64 ACPI parking
918 protocol even if the corresponding data is present in the ACPI
922 string "Default kernel command string"
925 Provide a set of default command-line options at build time by
926 entering them here. As a minimum, you should specify the the
927 root device (e.g. root=/dev/nfs).
930 bool "Always use the default kernel command string"
932 Always use the default kernel command string, even if the boot
933 loader passes other arguments to the kernel.
934 This is useful if you cannot or don't want to change the
935 command-line options your boot loader passes to the kernel.
941 bool "UEFI runtime support"
942 depends on OF && !CPU_BIG_ENDIAN
945 select EFI_PARAMS_FROM_FDT
946 select EFI_RUNTIME_WRAPPERS
951 This option provides support for runtime services provided
952 by UEFI firmware (such as non-volatile variables, realtime
953 clock, and platform reset). A UEFI stub is also provided to
954 allow the kernel to be booted as an EFI application. This
955 is only useful on systems that have UEFI firmware.
958 bool "Enable support for SMBIOS (DMI) tables"
962 This enables SMBIOS/DMI feature for systems.
964 This option is only useful on systems that have UEFI firmware.
965 However, even with this option, the resultant kernel should
966 continue to boot on existing non-UEFI platforms.
970 menu "Userspace binary formats"
972 source "fs/Kconfig.binfmt"
975 bool "Kernel support for 32-bit EL0"
976 depends on ARM64_4K_PAGES || EXPERT
977 select COMPAT_BINFMT_ELF
979 select OLD_SIGSUSPEND3
980 select COMPAT_OLD_SIGACTION
982 This option enables support for a 32-bit EL0 running under a 64-bit
983 kernel at EL1. AArch32-specific components such as system calls,
984 the user helper functions, VFP support and the ptrace interface are
985 handled appropriately by the kernel.
987 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
988 that you will only be able to execute AArch32 binaries that were compiled
989 with page size aligned segments.
991 If you want to execute 32-bit userspace applications, say Y.
993 config SYSVIPC_COMPAT
995 depends on COMPAT && SYSVIPC
999 menu "Power management options"
1001 source "kernel/power/Kconfig"
1003 config ARCH_HIBERNATION_POSSIBLE
1007 config ARCH_HIBERNATION_HEADER
1009 depends on HIBERNATION
1011 config ARCH_SUSPEND_POSSIBLE
1016 menu "CPU Power Management"
1018 source "drivers/cpuidle/Kconfig"
1020 source "drivers/cpufreq/Kconfig"
1024 source "net/Kconfig"
1026 source "drivers/Kconfig"
1028 source "drivers/firmware/Kconfig"
1030 source "drivers/acpi/Kconfig"
1034 source "arch/arm64/kvm/Kconfig"
1036 source "arch/arm64/Kconfig.debug"
1038 source "security/Kconfig"
1040 source "crypto/Kconfig"
1042 source "arch/arm64/crypto/Kconfig"
1045 source "lib/Kconfig"