3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
24 select BUILDTIME_EXTABLE_SORT
25 select CLONE_BACKWARDS
27 select CPU_PM if (SUSPEND || CPU_IDLE)
28 select DCACHE_WORD_ACCESS
30 select GENERIC_ALLOCATOR
31 select GENERIC_CLOCKEVENTS
32 select GENERIC_CLOCKEVENTS_BROADCAST
33 select GENERIC_CPU_AUTOPROBE
34 select GENERIC_EARLY_IOREMAP
35 select GENERIC_IDLE_POLL_SETUP
36 select GENERIC_IRQ_PROBE
37 select GENERIC_IRQ_SHOW
38 select GENERIC_IRQ_SHOW_LEVEL
39 select GENERIC_PCI_IOMAP
40 select GENERIC_SCHED_CLOCK
41 select GENERIC_SMP_IDLE_THREAD
42 select GENERIC_STRNCPY_FROM_USER
43 select GENERIC_STRNLEN_USER
44 select GENERIC_TIME_VSYSCALL
45 select HANDLE_DOMAIN_IRQ
46 select HARDIRQS_SW_RESEND
47 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
48 select HAVE_ARCH_AUDITSYSCALL
49 select HAVE_ARCH_BITREVERSE
50 select HAVE_ARCH_JUMP_LABEL
52 select HAVE_ARCH_SECCOMP_FILTER
53 select HAVE_ARCH_TRACEHOOK
55 select HAVE_C_RECORDMCOUNT
56 select HAVE_CC_STACKPROTECTOR
57 select HAVE_CMPXCHG_DOUBLE
58 select HAVE_CMPXCHG_LOCAL
59 select HAVE_DEBUG_BUGVERBOSE
60 select HAVE_DEBUG_KMEMLEAK
61 select HAVE_DMA_API_DEBUG
63 select HAVE_DMA_CONTIGUOUS
64 select HAVE_DYNAMIC_FTRACE
65 select HAVE_EFFICIENT_UNALIGNED_ACCESS
66 select HAVE_FTRACE_MCOUNT_RECORD
67 select HAVE_FUNCTION_TRACER
68 select HAVE_FUNCTION_GRAPH_TRACER
69 select HAVE_GENERIC_DMA_COHERENT
70 select HAVE_HW_BREAKPOINT if PERF_EVENTS
72 select HAVE_PATA_PLATFORM
73 select HAVE_PERF_EVENTS
75 select HAVE_PERF_USER_STACK_DUMP
76 select HAVE_RCU_TABLE_FREE
77 select HAVE_SYSCALL_TRACEPOINTS
79 select IRQ_FORCED_THREADING
80 select MODULES_USE_ELF_RELA
83 select OF_EARLY_FLATTREE
84 select OF_RESERVED_MEM
85 select PERF_USE_VMALLOC
90 select SYSCTL_EXCEPTION_TRACE
91 select HAVE_CONTEXT_TRACKING
93 ARM 64-bit (AArch64) Linux support.
98 config ARCH_PHYS_ADDR_T_64BIT
107 config STACKTRACE_SUPPORT
110 config ILLEGAL_POINTER_VALUE
112 default 0xdead000000000000
114 config LOCKDEP_SUPPORT
117 config TRACE_IRQFLAGS_SUPPORT
120 config RWSEM_XCHGADD_ALGORITHM
127 config GENERIC_BUG_RELATIVE_POINTERS
129 depends on GENERIC_BUG
131 config GENERIC_HWEIGHT
137 config GENERIC_CALIBRATE_DELAY
143 config HAVE_GENERIC_RCU_GUP
146 config ARCH_DMA_ADDR_T_64BIT
149 config NEED_DMA_MAP_STATE
152 config NEED_SG_DMA_LENGTH
164 config KERNEL_MODE_NEON
167 config FIX_EARLYCON_MEM
170 config PGTABLE_LEVELS
172 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
173 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
174 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
175 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
177 source "init/Kconfig"
179 source "kernel/Kconfig.freezer"
181 source "arch/arm64/Kconfig.platforms"
188 This feature enables support for PCI bus system. If you say Y
189 here, the kernel will include drivers and infrastructure code
190 to support PCI bus devices.
195 config PCI_DOMAINS_GENERIC
201 source "drivers/pci/Kconfig"
202 source "drivers/pci/pcie/Kconfig"
203 source "drivers/pci/hotplug/Kconfig"
207 menu "Kernel Features"
209 menu "ARM errata workarounds via the alternatives framework"
211 config ARM64_ERRATUM_826319
212 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
215 This option adds an alternative code sequence to work around ARM
216 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
217 AXI master interface and an L2 cache.
219 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
220 and is unable to accept a certain write via this interface, it will
221 not progress on read data presented on the read data channel and the
224 The workaround promotes data cache clean instructions to
225 data cache clean-and-invalidate.
226 Please note that this does not necessarily enable the workaround,
227 as it depends on the alternative framework, which will only patch
228 the kernel if an affected CPU is detected.
232 config ARM64_ERRATUM_827319
233 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
236 This option adds an alternative code sequence to work around ARM
237 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
238 master interface and an L2 cache.
240 Under certain conditions this erratum can cause a clean line eviction
241 to occur at the same time as another transaction to the same address
242 on the AMBA 5 CHI interface, which can cause data corruption if the
243 interconnect reorders the two transactions.
245 The workaround promotes data cache clean instructions to
246 data cache clean-and-invalidate.
247 Please note that this does not necessarily enable the workaround,
248 as it depends on the alternative framework, which will only patch
249 the kernel if an affected CPU is detected.
253 config ARM64_ERRATUM_824069
254 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
257 This option adds an alternative code sequence to work around ARM
258 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
259 to a coherent interconnect.
261 If a Cortex-A53 processor is executing a store or prefetch for
262 write instruction at the same time as a processor in another
263 cluster is executing a cache maintenance operation to the same
264 address, then this erratum might cause a clean cache line to be
265 incorrectly marked as dirty.
267 The workaround promotes data cache clean instructions to
268 data cache clean-and-invalidate.
269 Please note that this option does not necessarily enable the
270 workaround, as it depends on the alternative framework, which will
271 only patch the kernel if an affected CPU is detected.
275 config ARM64_ERRATUM_819472
276 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
279 This option adds an alternative code sequence to work around ARM
280 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
281 present when it is connected to a coherent interconnect.
283 If the processor is executing a load and store exclusive sequence at
284 the same time as a processor in another cluster is executing a cache
285 maintenance operation to the same address, then this erratum might
286 cause data corruption.
288 The workaround promotes data cache clean instructions to
289 data cache clean-and-invalidate.
290 Please note that this does not necessarily enable the workaround,
291 as it depends on the alternative framework, which will only patch
292 the kernel if an affected CPU is detected.
296 config ARM64_ERRATUM_832075
297 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
300 This option adds an alternative code sequence to work around ARM
301 erratum 832075 on Cortex-A57 parts up to r1p2.
303 Affected Cortex-A57 parts might deadlock when exclusive load/store
304 instructions to Write-Back memory are mixed with Device loads.
306 The workaround is to promote device loads to use Load-Acquire
308 Please note that this does not necessarily enable the workaround,
309 as it depends on the alternative framework, which will only patch
310 the kernel if an affected CPU is detected.
314 config ARM64_ERRATUM_845719
315 bool "Cortex-A53: 845719: a load might read incorrect data"
319 This option adds an alternative code sequence to work around ARM
320 erratum 845719 on Cortex-A53 parts up to r0p4.
322 When running a compat (AArch32) userspace on an affected Cortex-A53
323 part, a load at EL0 from a virtual address that matches the bottom 32
324 bits of the virtual address used by a recent load at (AArch64) EL1
325 might return incorrect data.
327 The workaround is to write the contextidr_el1 register on exception
328 return to a 32-bit task.
329 Please note that this does not necessarily enable the workaround,
330 as it depends on the alternative framework, which will only patch
331 the kernel if an affected CPU is detected.
340 default ARM64_4K_PAGES
342 Page size (translation granule) configuration.
344 config ARM64_4K_PAGES
347 This feature enables 4KB pages support.
349 config ARM64_64K_PAGES
352 This feature enables 64KB pages support (4KB by default)
353 allowing only two levels of page tables and faster TLB
354 look-up. AArch32 emulation is not available when this feature
360 prompt "Virtual address space size"
361 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
362 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
364 Allows choosing one of multiple possible virtual address
365 space sizes. The level of translation table is determined by
366 a combination of page size and virtual address space size.
368 config ARM64_VA_BITS_39
370 depends on ARM64_4K_PAGES
372 config ARM64_VA_BITS_42
374 depends on ARM64_64K_PAGES
376 config ARM64_VA_BITS_48
383 default 39 if ARM64_VA_BITS_39
384 default 42 if ARM64_VA_BITS_42
385 default 48 if ARM64_VA_BITS_48
387 config CPU_BIG_ENDIAN
388 bool "Build big-endian kernel"
390 Say Y if you plan on running a kernel in big-endian mode.
393 bool "Multi-core scheduler support"
395 Multi-core scheduler support improves the CPU scheduler's decision
396 making when dealing with multi-core CPU chips at a cost of slightly
397 increased overhead in some places. If unsure say N here.
400 bool "SMT scheduler support"
402 Improves the CPU scheduler's decision making when dealing with
403 MultiThreading at a cost of slightly increased overhead in some
404 places. If unsure say N here.
407 int "Maximum number of CPUs (2-4096)"
409 # These have to remain sorted largest to smallest
413 bool "Support for hot-pluggable CPUs"
415 Say Y here to experiment with turning CPUs off and on. CPUs
416 can be controlled through /sys/devices/system/cpu.
418 source kernel/Kconfig.preempt
424 config ARCH_HAS_HOLES_MEMORYMODEL
425 def_bool y if SPARSEMEM
427 config ARCH_SPARSEMEM_ENABLE
429 select SPARSEMEM_VMEMMAP_ENABLE
431 config ARCH_SPARSEMEM_DEFAULT
432 def_bool ARCH_SPARSEMEM_ENABLE
434 config ARCH_SELECT_MEMORY_MODEL
435 def_bool ARCH_SPARSEMEM_ENABLE
437 config HAVE_ARCH_PFN_VALID
438 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
440 config HW_PERF_EVENTS
441 bool "Enable hardware performance counter support for perf events"
442 depends on PERF_EVENTS
445 Enable hardware performance counter support for perf events. If
446 disabled, perf events will use software events only.
448 config SYS_SUPPORTS_HUGETLBFS
451 config ARCH_WANT_GENERAL_HUGETLB
454 config ARCH_WANT_HUGE_PMD_SHARE
455 def_bool y if !ARM64_64K_PAGES
457 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
460 config ARCH_HAS_CACHE_LINE_SIZE
466 bool "Enable seccomp to safely compute untrusted bytecode"
468 This kernel feature is useful for number crunching applications
469 that may need to compute untrusted bytecode during their
470 execution. By using pipes or other transports made available to
471 the process as file descriptors supporting the read/write
472 syscalls, it's possible to isolate those applications in
473 their own address space using seccomp. Once seccomp is
474 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
475 and the task is only allowed to execute a few safe syscalls
476 defined by each seccomp mode.
483 bool "Xen guest support on ARM64"
484 depends on ARM64 && OF
487 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
489 config FORCE_MAX_ZONEORDER
491 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
494 menuconfig ARMV8_DEPRECATED
495 bool "Emulate deprecated/obsolete ARMv8 instructions"
498 Legacy software support may require certain instructions
499 that have been deprecated or obsoleted in the architecture.
501 Enable this config to enable selective emulation of these
509 bool "Emulate SWP/SWPB instructions"
511 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
512 they are always undefined. Say Y here to enable software
513 emulation of these instructions for userspace using LDXR/STXR.
515 In some older versions of glibc [<=2.8] SWP is used during futex
516 trylock() operations with the assumption that the code will not
517 be preempted. This invalid assumption may be more likely to fail
518 with SWP emulation enabled, leading to deadlock of the user
521 NOTE: when accessing uncached shared regions, LDXR/STXR rely
522 on an external transaction monitoring block called a global
523 monitor to maintain update atomicity. If your system does not
524 implement a global monitor, this option can cause programs that
525 perform SWP operations to uncached memory to deadlock.
529 config CP15_BARRIER_EMULATION
530 bool "Emulate CP15 Barrier instructions"
532 The CP15 barrier instructions - CP15ISB, CP15DSB, and
533 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
534 strongly recommended to use the ISB, DSB, and DMB
535 instructions instead.
537 Say Y here to enable software emulation of these
538 instructions for AArch32 userspace code. When this option is
539 enabled, CP15 barrier usage is traced which can help
540 identify software that needs updating.
544 config SETEND_EMULATION
545 bool "Emulate SETEND instruction"
547 The SETEND instruction alters the data-endianness of the
548 AArch32 EL0, and is deprecated in ARMv8.
550 Say Y here to enable software emulation of the instruction
551 for AArch32 userspace code.
553 Note: All the cpus on the system must have mixed endian support at EL0
554 for this feature to be enabled. If a new CPU - which doesn't support mixed
555 endian - is hotplugged in after this feature has been enabled, there could
556 be unexpected results in the applications.
561 menu "ARMv8.1 architectural features"
563 config ARM64_HW_AFDBM
564 bool "Support for hardware updates of the Access and Dirty page flags"
567 The ARMv8.1 architecture extensions introduce support for
568 hardware updates of the access and dirty information in page
569 table entries. When enabled in TCR_EL1 (HA and HD bits) on
570 capable processors, accesses to pages with PTE_AF cleared will
571 set this bit instead of raising an access flag fault.
572 Similarly, writes to read-only pages with the DBM bit set will
573 clear the read-only bit (AP[2]) instead of raising a
576 Kernels built with this configuration option enabled continue
577 to work on pre-ARMv8.1 hardware and the performance impact is
578 minimal. If unsure, say Y.
581 bool "Enable support for Privileged Access Never (PAN)"
584 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
585 prevents the kernel or hypervisor from accessing user-space (EL0)
588 Choosing this option will cause any unprotected (not using
589 copy_to_user et al) memory access to fail with a permission fault.
591 The feature is detected at runtime, and will remain as a 'nop'
592 instruction if the cpu does not implement the feature.
594 config ARM64_LSE_ATOMICS
595 bool "Atomic instructions"
597 As part of the Large System Extensions, ARMv8.1 introduces new
598 atomic instructions that are designed specifically to scale in
601 Say Y here to make use of these instructions for the in-kernel
602 atomic routines. This incurs a small overhead on CPUs that do
603 not support these instructions and requires the kernel to be
604 built with binutils >= 2.25.
613 string "Default kernel command string"
616 Provide a set of default command-line options at build time by
617 entering them here. As a minimum, you should specify the the
618 root device (e.g. root=/dev/nfs).
621 bool "Always use the default kernel command string"
623 Always use the default kernel command string, even if the boot
624 loader passes other arguments to the kernel.
625 This is useful if you cannot or don't want to change the
626 command-line options your boot loader passes to the kernel.
632 bool "UEFI runtime support"
633 depends on OF && !CPU_BIG_ENDIAN
636 select EFI_PARAMS_FROM_FDT
637 select EFI_RUNTIME_WRAPPERS
642 This option provides support for runtime services provided
643 by UEFI firmware (such as non-volatile variables, realtime
644 clock, and platform reset). A UEFI stub is also provided to
645 allow the kernel to be booted as an EFI application. This
646 is only useful on systems that have UEFI firmware.
649 bool "Enable support for SMBIOS (DMI) tables"
653 This enables SMBIOS/DMI feature for systems.
655 This option is only useful on systems that have UEFI firmware.
656 However, even with this option, the resultant kernel should
657 continue to boot on existing non-UEFI platforms.
661 menu "Userspace binary formats"
663 source "fs/Kconfig.binfmt"
666 bool "Kernel support for 32-bit EL0"
667 depends on !ARM64_64K_PAGES || EXPERT
668 select COMPAT_BINFMT_ELF
670 select OLD_SIGSUSPEND3
671 select COMPAT_OLD_SIGACTION
673 This option enables support for a 32-bit EL0 running under a 64-bit
674 kernel at EL1. AArch32-specific components such as system calls,
675 the user helper functions, VFP support and the ptrace interface are
676 handled appropriately by the kernel.
678 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
679 will only be able to execute AArch32 binaries that were compiled with
680 64k aligned segments.
682 If you want to execute 32-bit userspace applications, say Y.
684 config SYSVIPC_COMPAT
686 depends on COMPAT && SYSVIPC
690 menu "Power management options"
692 source "kernel/power/Kconfig"
694 config ARCH_SUSPEND_POSSIBLE
699 menu "CPU Power Management"
701 source "drivers/cpuidle/Kconfig"
703 source "drivers/cpufreq/Kconfig"
709 source "drivers/Kconfig"
711 source "drivers/firmware/Kconfig"
713 source "drivers/acpi/Kconfig"
717 source "arch/arm64/kvm/Kconfig"
719 source "arch/arm64/Kconfig.debug"
721 source "security/Kconfig"
723 source "crypto/Kconfig"
725 source "arch/arm64/crypto/Kconfig"