2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/reset/sun50i-a64-ccu.h>
50 interrupt-parent = <&gic>;
59 compatible = "arm,cortex-a53", "arm,armv8";
62 enable-method = "psci";
66 compatible = "arm,cortex-a53", "arm,armv8";
69 enable-method = "psci";
73 compatible = "arm,cortex-a53", "arm,armv8";
76 enable-method = "psci";
80 compatible = "arm,cortex-a53", "arm,armv8";
83 enable-method = "psci";
89 compatible = "fixed-clock";
90 clock-frequency = <24000000>;
91 clock-output-names = "osc24M";
96 compatible = "fixed-clock";
97 clock-frequency = <32768>;
98 clock-output-names = "osc32k";
102 compatible = "arm,psci-0.2";
107 compatible = "arm,armv8-timer";
108 interrupts = <GIC_PPI 13
109 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
111 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
113 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
115 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
119 compatible = "simple-bus";
120 #address-cells = <1>;
125 compatible = "allwinner,sun50i-a64-mmc";
126 reg = <0x01c0f000 0x1000>;
127 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
128 clock-names = "ahb", "mmc";
129 resets = <&ccu RST_BUS_MMC0>;
131 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
132 max-frequency = <150000000>;
134 #address-cells = <1>;
139 compatible = "allwinner,sun50i-a64-mmc";
140 reg = <0x01c10000 0x1000>;
141 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
142 clock-names = "ahb", "mmc";
143 resets = <&ccu RST_BUS_MMC1>;
145 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
146 max-frequency = <150000000>;
148 #address-cells = <1>;
153 compatible = "allwinner,sun50i-a64-emmc";
154 reg = <0x01c11000 0x1000>;
155 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
156 clock-names = "ahb", "mmc";
157 resets = <&ccu RST_BUS_MMC2>;
159 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
160 max-frequency = <200000000>;
162 #address-cells = <1>;
166 usb_otg: usb@01c19000 {
167 compatible = "allwinner,sun8i-a33-musb";
168 reg = <0x01c19000 0x0400>;
169 clocks = <&ccu CLK_BUS_OTG>;
170 resets = <&ccu RST_BUS_OTG>;
171 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
172 interrupt-names = "mc";
175 extcon = <&usbphy 0>;
179 usbphy: phy@01c19400 {
180 compatible = "allwinner,sun50i-a64-usb-phy";
181 reg = <0x01c19400 0x14>,
184 reg-names = "phy_ctrl",
187 clocks = <&ccu CLK_USB_PHY0>,
189 clock-names = "usb0_phy",
191 resets = <&ccu RST_USB_PHY0>,
193 reset-names = "usb0_reset",
199 ehci1: usb@01c1b000 {
200 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
201 reg = <0x01c1b000 0x100>;
202 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&ccu CLK_BUS_OHCI1>,
204 <&ccu CLK_BUS_EHCI1>,
205 <&ccu CLK_USB_OHCI1>;
206 resets = <&ccu RST_BUS_OHCI1>,
207 <&ccu RST_BUS_EHCI1>;
213 ohci1: usb@01c1b400 {
214 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
215 reg = <0x01c1b400 0x100>;
216 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&ccu CLK_BUS_OHCI1>,
218 <&ccu CLK_USB_OHCI1>;
219 resets = <&ccu RST_BUS_OHCI1>;
225 ccu: clock@01c20000 {
226 compatible = "allwinner,sun50i-a64-ccu";
227 reg = <0x01c20000 0x400>;
228 clocks = <&osc24M>, <&osc32k>;
229 clock-names = "hosc", "losc";
234 pio: pinctrl@1c20800 {
235 compatible = "allwinner,sun50i-a64-pinctrl";
236 reg = <0x01c20800 0x400>;
237 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
243 interrupt-controller;
244 #interrupt-cells = <3>;
246 i2c1_pins: i2c1_pins {
251 mmc0_pins: mmc0-pins {
252 pins = "PF0", "PF1", "PF2", "PF3",
255 drive-strength = <30>;
259 mmc1_pins: mmc1-pins {
260 pins = "PG0", "PG1", "PG2", "PG3",
263 drive-strength = <30>;
267 mmc2_pins: mmc2-pins {
268 pins = "PC1", "PC5", "PC6", "PC8", "PC9",
269 "PC10","PC11", "PC12", "PC13",
270 "PC14", "PC15", "PC16";
272 drive-strength = <30>;
276 uart0_pins_a: uart0@0 {
281 uart1_pins: uart1_pins {
286 uart1_rts_cts_pins: uart1_rts_cts_pins {
292 uart0: serial@1c28000 {
293 compatible = "snps,dw-apb-uart";
294 reg = <0x01c28000 0x400>;
295 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
303 uart1: serial@1c28400 {
304 compatible = "snps,dw-apb-uart";
305 reg = <0x01c28400 0x400>;
306 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
314 uart2: serial@1c28800 {
315 compatible = "snps,dw-apb-uart";
316 reg = <0x01c28800 0x400>;
317 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
325 uart3: serial@1c28c00 {
326 compatible = "snps,dw-apb-uart";
327 reg = <0x01c28c00 0x400>;
328 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
336 uart4: serial@1c29000 {
337 compatible = "snps,dw-apb-uart";
338 reg = <0x01c29000 0x400>;
339 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
348 compatible = "allwinner,sun6i-a31-i2c";
349 reg = <0x01c2ac00 0x400>;
350 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
359 compatible = "allwinner,sun6i-a31-i2c";
360 reg = <0x01c2b000 0x400>;
361 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
365 #address-cells = <1>;
370 compatible = "allwinner,sun6i-a31-i2c";
371 reg = <0x01c2b400 0x400>;
372 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
376 #address-cells = <1>;
380 gic: interrupt-controller@1c81000 {
381 compatible = "arm,gic-400";
382 reg = <0x01c81000 0x1000>,
386 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
387 interrupt-controller;
388 #interrupt-cells = <3>;
392 compatible = "allwinner,sun6i-a31-rtc";
393 reg = <0x01f00000 0x54>;
394 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;