2 * DTS file for AMD Seattle SoC
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
8 compatible = "amd,seattle";
9 interrupt-parent = <&gic0>;
13 gic0: interrupt-controller@e1101000 {
14 compatible = "arm,gic-400", "arm,cortex-a15-gic";
16 #interrupt-cells = <3>;
19 reg = <0x0 0xe1110000 0 0x1000>,
20 <0x0 0xe112f000 0 0x2000>,
21 <0x0 0xe1140000 0 0x2000>,
22 <0x0 0xe1160000 0 0x2000>;
23 interrupts = <1 9 0xf04>;
24 ranges = <0 0 0 0xe1100000 0 0x100000>;
26 compatible = "arm,gic-v2m-frame";
28 reg = <0x0 0x00080000 0 0x1000>;
33 compatible = "arm,armv8-timer";
34 interrupts = <1 13 0xff04>,
41 compatible = "arm,armv8-pmuv3";
53 compatible = "simple-bus";
59 * dma-ranges is 40-bit address space containing:
60 * - GICv2m MSI register is at 0xe0080000
61 * - DRAM range [0x8000000000 to 0xffffffffff]
63 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
65 /include/ "amd-seattle-clks.dtsi"
67 sata0: sata@e0300000 {
68 compatible = "snps,dwc-ahci";
69 reg = <0 0xe0300000 0 0xf0000>;
70 interrupts = <0 355 4>;
71 clocks = <&sataclk_333mhz>;
75 /* This is for Rev B only */
76 sata1: sata@e0d00000 {
78 compatible = "snps,dwc-ahci";
79 reg = <0 0xe0d00000 0 0xf0000>;
80 interrupts = <0 354 4>;
81 clocks = <&sataclk_333mhz>;
87 compatible = "snps,designware-i2c";
88 reg = <0 0xe1000000 0 0x1000>;
89 interrupts = <0 357 4>;
90 clocks = <&miscclk_250mhz>;
95 compatible = "snps,designware-i2c";
96 reg = <0 0xe0050000 0 0x1000>;
97 interrupts = <0 340 4>;
98 clocks = <&miscclk_250mhz>;
101 serial0: serial@e1010000 {
102 compatible = "arm,pl011", "arm,primecell";
103 reg = <0 0xe1010000 0 0x1000>;
104 interrupts = <0 328 4>;
105 clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
106 clock-names = "uartclk", "apb_pclk";
111 compatible = "arm,pl022", "arm,primecell";
112 reg = <0 0xe1020000 0 0x1000>;
114 interrupts = <0 330 4>;
115 clocks = <&uartspiclk_100mhz>;
116 clock-names = "apb_pclk";
121 compatible = "arm,pl022", "arm,primecell";
122 reg = <0 0xe1030000 0 0x1000>;
124 interrupts = <0 329 4>;
125 clocks = <&uartspiclk_100mhz>;
126 clock-names = "apb_pclk";
128 #address-cells = <1>;
132 gpio0: gpio@e1040000 { /* Not available to OS for B0 */
134 compatible = "arm,pl061", "arm,primecell";
136 reg = <0 0xe1040000 0 0x1000>;
138 interrupts = <0 359 4>;
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 clocks = <&miscclk_250mhz>;
142 clock-names = "apb_pclk";
145 gpio1: gpio@e1050000 { /* [0:7] */
147 compatible = "arm,pl061", "arm,primecell";
149 reg = <0 0xe1050000 0 0x1000>;
151 interrupt-controller;
152 #interrupt-cells = <2>;
153 interrupts = <0 358 4>;
154 clocks = <&miscclk_250mhz>;
155 clock-names = "apb_pclk";
158 gpio2: gpio@e0020000 { /* [8:15] */
160 compatible = "arm,pl061", "arm,primecell";
162 reg = <0 0xe0020000 0 0x1000>;
164 interrupt-controller;
165 #interrupt-cells = <2>;
166 interrupts = <0 366 4>;
167 clocks = <&miscclk_250mhz>;
168 clock-names = "apb_pclk";
171 gpio3: gpio@e0030000 { /* [16:23] */
173 compatible = "arm,pl061", "arm,primecell";
175 reg = <0 0xe0030000 0 0x1000>;
177 interrupt-controller;
178 #interrupt-cells = <2>;
179 interrupts = <0 365 4>;
180 clocks = <&miscclk_250mhz>;
181 clock-names = "apb_pclk";
184 gpio4: gpio@e0080000 { /* [24] */
186 compatible = "arm,pl061", "arm,primecell";
188 reg = <0 0xe0080000 0 0x1000>;
190 interrupt-controller;
191 #interrupt-cells = <2>;
192 interrupts = <0 361 4>;
193 clocks = <&miscclk_250mhz>;
194 clock-names = "apb_pclk";
199 compatible = "amd,ccp-seattle-v1a";
200 reg = <0 0xe0100000 0 0x10000>;
201 interrupts = <0 3 4>;
205 pcie0: pcie@f0000000 {
206 compatible = "pci-host-ecam-generic";
207 #address-cells = <3>;
209 #interrupt-cells = <1>;
211 bus-range = <0 0x7f>;
212 msi-parent = <&v2m0>;
213 reg = <0 0xf0000000 0 0x10000000>;
215 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
217 <0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
218 <0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
219 <0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
220 <0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>;
223 dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
225 /* I/O Memory (size=64K) */
226 <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
227 /* 32-bit MMIO (size=2G) */
228 <0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
229 /* 64-bit MMIO (size= 124G) */
230 <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
233 /* Perf CCN504 PMU */
234 ccn: ccn@0xe8000000 {
235 compatible = "arm,ccn-504";
236 reg = <0x0 0xe8000000 0 0x1000000>;
237 interrupts = <0 380 4>;
240 ipmi_kcs: kcs@e0010000 {
242 compatible = "ipmi-kcs";
243 device_type = "ipmi";
244 reg = <0x0 0xe0010000 0 0x8>;
245 interrupts = <0 389 4>;
246 interrupt-names = "ipmi_kcs";